2023 The 8th International Conference on Computer and Communication Systems
Survey and Comparison of Pipeline of Some RISC
and CISC System Architectures
Yan He
School of Electronic Science and Engineering
Nanjing University
2023 8th International Conference on Computer and Communication Systems (ICCCS) | 978-1-6654-5612-8/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICCCS57501.2023.10150975
Nanjing, China
MF21230031@smail.nju.edu.cn
Abstract—Instruction set is a set of instructions used by CPU
to calculate and control computer system, and is the interface
between hardware and software. There are two common
instruction sets: CISC and RISC. Pipeline technology is widely
used in instruction set processor design to improve the efficiency
of executing instructions. This paper introduces the difference
between CISC and RISC in pipeline implementation, introduces
the basic pipelining and two advanced pipelining - superscalar
and superpipelining in detail, and introduces several pipelining
using CISC and RISC architecture processors, including ARM,
RISC-V, Longarch, and X86.
Keywords—Pipeline, superscalar, superpipelining, CISC, RISC,
processor
I. INTRODUCTION
If the computer is to obey the command, it must be in the
language of the computer. The basic words in a computer
language are called instructions, and all the instructions of a
computer are called the instruction set of the computer [1]. In
general, instruction set architectures define supported
instructions, data types, registers, hardware support for
managing main memory, basic features (such as memory
consistency, addressing mode, virtual memory), and a set of
implemented input/output models.
The Instruction Set architecture is mainly divided into
Complex Instruction Set Computer (CISC) and Reduced
Instruction Set Computer (RISC). In the 1960s, people changed
the original task to be completed by multiple instructions to be
completed by one Instruction, and the computer that executes
these Complex instructions is called CISC. But with the
development of computer technology, the number of
instructions also increases, making the complex instruction set
more complex. It was found that only 20% of the instructions
defined by the CISC instruction set were frequently used and
80% were rarely used. Therefore, RISC became popular in the
1980s. The biggest difference between RISC and CISC lies in
the simplicity of its instructions. Multiple instructions are used
to complete the tasks that can be completed by one instruction
in a complex instruction set [2].
Compared with reduced instructions, complex instructions
introduce problems to the pipeline technology widely used in
modern processor technology: the execution of instructions in
microprocessors is generally divided into "prefetch", "fetching
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Xiangning Chen
School of Electronic Science and Engineering
Nanjing University
Nanjing, China
shining@nju.edu.cn
operands", "operation", "storage" and other operations. First of
all, for complex instructions, their execution times are different.
Some can be completed in 4 or 5 clock cycles, while others
require dozens. Even for simple instructions, different
addressing methods will result in different execution times.
What's worse, the length of instructions is also different, and
the length of the same instruction will vary with different
addressing methods. For these instructions, how to design the
pipeline length? If the pipeline is designed according to the
shortest instruction, the pipeline will be interrupted when
encountering complex instructions; If the pipeline is designed
according to the longest instruction, some stages will be
skipped when executing shorter instructions, so that the
pipeline cannot be fully filled. RISC have a fixed length and
few addressing modes. Most of them are simple instructions
and can be completed in a clock cycle.
Secondly, CISC has a complex instruction format due to
its variable instruction length. In contrast, RISC has fewer
instruction formats, and the source register field positions in
each instruction are the same. This symmetry means that the
decoding stage can start to read the register stack while
determining the reference type. If the instruction format is
asymmetric, the decoding stage needs to be divided into two
parts to deepen the pipeline level.
Then, CISC does not have special memory operation
instructions. Many instructions can operate the memory.
Taking one instruction often requires several consecutive
memory operations, making memory access operations
frequent and without rules to follow. RISC uses special load
instructions and store instructions to access memory. Other
ordinary instructions cannot access memory, making RISC
memory operands only appear in access instructions. All
operands must be aligned in the memory, and there is no need
to worry that a data transmission instruction needs to access the
memory twice. The requested data can be transmitted between
the processor and memory in the first level pipeline[3].
Although RISC has more advantages in using pipelines, it
does not mean that CISC cannot use pipelines. In order to
facilitate pipeline design, various CISC system CPUs have
introduced the concept of micro-operations instructions. In the
pipeline pre fetching and pre decoding stages, hardware
decoders are used to translate the corresponding internal simple
instruction (microcode) sequences, and then sent to the
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 processor pipeline for execution. A common CISC instruction
is converted into one or more micro operation instructions with
the same length, fixed format and similar RISC instruction
form, which can draw on the advantages of RISC architecture.
II. PIPELINE
A. Basic Pipeline
Pipelining is a technology to realize the overlapping
execution of multiple instructions, similar to the production
pipeline [1]. The pipeline structure divides the execution of an
instruction into several steps called stages, and each stage is
completed within a clock cycle. Each stage completes a
specific function and produces a (intermediate) result. Each
stage is composed of an input register and a subsequent
combined logical data path, which is connected with the input
register of the next stage. The clock signal can be sent to the
input registers at all stages at the same time. Each clock pulse
urges each stage to send the completed results to the next level
at the same time [4].
TABLE I. MIPS PIPELINE
The classic MIPS five level pipeline which is mentioned
most in computer architecture textbooks. As shown in Table
1,The life cycle of an instruction in this pipeline is divided into
the following steps: 1) IF(instruction fetch):fetch instructions
from the memory. 2)ID(instruction decode): The instruction
decodes while reading the register. After decoding, the operand
register index required by the instruction is obtained. You can
use this index to fetch the operand from the Register File.
3)EX(execution): Perform operations or calculate addresses.
4)MEM(memory access): fetch the operands from the data
store. 5)WB(write-back): Write the result back to the register.
If it is an ordinary operation instruction, the result value comes
from the result calculated in the "execution" stage; if it is a load
instruction, the result comes from the data read from the
memory in the "memory access" stage[5]. The time required
for each stage to complete the specified processing task may be
different, but the clock cycle needs to be selected to ensure that
the slowest level can complete the task. if the pipeline does not
pause, it can theoretically achieve the performance of
completing one instruction per clock cycle, increasing the
number of instructions executed simultaneously and the rate at
which instructions start and end. Pipelining does not reduce the
execution time of a single instruction, also known as latency.
MIPS five level pipeline still needs 5 clock cycles to complete
an instruction [6].
B. Superscalar
Superscalar method is a pipeline technology that uses
multiple independent instructions, which depends on the ability
to execute multiple instructions in parallel. The bottom of Fig.
2 shows a superscalar implementation that executes two
instructions in parallel. Its essence is the ability to execute
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instructions independently in different pipelines. This concept
can be further developed to allow instructions to be executed in
a sequence different from the original program sequence[7].
The superscalar processor fetches multiple instructions at a
time, and then tries to find several instructions that are
unrelated to each other and can be executed in parallel. If the
input of an instruction depends on the output of the previous
instruction, the instruction cannot be parallel at the same time,
nor can it be executed before the previous instruction. Once
this correlation is confirmed, the processor can transmit and
complete instructions in a different order from the original
code. By using more registers or renaming register references
in the original code, the processor can remove some
unnecessary dependencies[8]. Compared with RISC, CISC has
more limitations in using superscalar method. Because the
specific length of any instruction is not known in advance, it
must be decoded at least partially before taking subsequent
instructions. This prevents instruction fetching required by
superscalar pipelining. Although superscalar techniques are
more suitable for RISC or RISC like structures, superscalar
methods can also be applied to CISC structures through micro-
operations. The most famous example is Pentium. The original
Pentium has a certain superscalar capability. It uses two
discrete integer execution units. Pentium Pro introduces a
comprehensive superscalar design concept. Subsequent
Pentium models have more sophisticated and powerful
superscalar designs[3].
Fig. 1. Superscalar and superpipeline.
C. Super Pipelining
The tasks completed in most pipeline stages only need less
time than half of the clock cycle[3]. Thus, in a two-stage super
pipelined microprocessor, the task completed by each pipelined
segment can be divided into two non overlapping parts and
each part can be executed within half a clock cycle. In this way,
as shown in the middle of Fig. 1,double the internal clock
frequency allows two tasks to be completed in one external
clock cycle. The super pipelined processor can transmit
multiple instructions in a clock cycle. It can also be said that
 the machine cycle can be shortened by increasing the number
of pipeline stages. In the same time, the super pipelining
execute more machine instructions[9]. Another advantage of
super pipelining is to improve the dominant frequency. The
more pipeline stages, the thinner the pipeline is cut, and the
less hardware logic each pipeline contains. The less hardware
logic between the two registers, the higher the frequency.
Of course, more pipeline stages will consume more
registers and more area overhead. Another problem with deep
processor pipelines is that it is impossible to know whether the
conditional jump result will jump or not at the instruction
fetching stage of the pipeline, so it can only be predicted. At
the end of the pipeline, it is possible to know whether the
branch should jump or not through actual operations. If the
prediction results do not match, you need to "Pipeline Flush" --
discard all the prefetched error instruction streams. Retrieve the
correct instruction stream. If the pipeline is deep, more error
instruction streams will be prefetched, discarded and restarted,
wasting power and losing performance [10].
It is precisely because of the different advantages and
disadvantages of processor pipeline depth, according to
different application scenarios, the pipeline depth of today's
processors is developing towards two different extremes. On
the one hand, the progression is getting deeper and deeper. In
2004, Pentium 4 (Prescott) reached an amazing 31; On the
other hand, it becomes shallower and shallower, the shallowest
can reach two stages.
III. PIPELINING OF SEVERAL RISC AND CISC PROCESSORS
A. ARM
The ARM core uses a RISC architecture. Most ARM
processors support two instruction sets: 32-bit ARM instruction
set and 16 bit Thumb instruction set.
The previous classic processor series of ARM include
ARM7, ARM9, ARM11.ARM7, which is a Von Neumann
structure. As shown in Fig.2,it uses a typical three-stage
pipeline and is divided into fetching, decoding, and execution.
The execution unit completes a lot of work, including reading
and writing operations of registers and memories related to
operands, ALU operations, and data transmission between
related devices. Therefore, it takes up multiple clock cycles.
Fig. 2. RM7 pipeline.
As shown in Fig.3, ARM9 is a Harvard architecture, which
uses five level pipeline technology. ARM9 adds two stages of
access memory and write back results after fetching
instructions, decoding, and executing. Access memory is
responsible for loading and storing data specified in
instructions, extracting, symbol expanding, and loading data
through byte or halfword loading commands. But access to
memory and write back results are only valid for load (LDR)
and store command (STR), and other instructions do not need
to execute these two stages. At the same time, ARM9 transfers
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the operation of reading registers to the decoding unit, which
makes the functions of various components of the pipeline
more balanced [11].
Fig. 3. ARM9 pipeline.
As shown in Fig.4,ARM11 selects pipeline of Scalar
architecture. On the back end of the pipeline, three parallel
component structures are used, ALU (arithmetic logic unit),
MAC (multiple/aggregate). LS (Load/Store). LS pipeline is
specially used for processing access operation instructions to
separate data access operations from data arithmetic operations,
so as to execute instructions more effectively. Considering that
different instructions require different execution times, when
three types of instructions are sent to the pipeline successively,
they can be executed simultaneously, allowing random
execution [12].
Fig. 4. ARM11 pipeline.
ARM Cortex A series architecture, under which ARM
imports Superscalar architecture pipeline, enabling the
processor to process more than one instruction set in parallel in
a cycle Taking Cortex A8 as an example, it supports the 13
stage integer pipeline(see Table 2) and the 10 stage NEON
multimedia instruction set pipeline(see Table 3). Taking the
integer processing instruction set as an example, Cortex A8
supports Dual Issue and In Order Pipeline. Unlike the previous
ARM core, which can only process one integer processing
instruction set at a time, Cortex A8 uses superscalar technology
to issue two integer processing instruction sets together, The
two instruction sets are processed in parallel by two integer
arithmetic logic units Pipeline in a cycle [14].
From the classic ARM series to the current Cortex series,
the structure of ARM processors is developing towards a
complex stage, but what has not changed is the CPU's access
instructions and address relationships. That is, no matter how
many stages of pipelines, the current PC position can be judged
according to the operating characteristics of the original three-
stage pipeline. PC always points to the instruction fetching, not
to the instruction executing or the instruction decoding.
Generally speaking, people habitually agree that the instruction
being executed is the reference point, which is called the
current first instruction. Therefore, PC always points to the
third instruction. In the execution phase, when ARM is in the
state, the PC always points to the instruction address+8 bytes;
When the processor is in thumb state, the PC always points to
the instruction address+4 bytes; When the branch instruction is
 executed or the PC is directly modified for branching, the
ARM kernel will refresh its pipeline; An instruction at the
execution stage completes its execution even if an interrupt is
raised.

TABLE II. CORTEX A INTEGER PIPELINE

13-Stage Integer Pipeline
F F F D D D D D E0 E E E E E
0 1 2 0 1 2 3 4 1 2 3 4 5
Instruction Instruction Decode Architec ALU/MUL Pipeline 0
Fetch With Dual-Issues tural Fig. 6. The Boom Core pipeline.
ALU Pipeline 1
Register
File Load/Store Pipeline 0 C. Longarch
or 1 At the beginning, Loongson used MIPS instruction set, but
in 2019, Loongson started to design a completely independent
TABLE III. CORTEX A NEON PIPELINE new instruction set, realizing completely independent design
10-Stage NEON Pipeline from the instruction system to the CPU, that is, LoongArch
architecture. LoongArch is a RISC,Godson3A5000 is the first
M0 M1 M2 M3 N0 N1 N2 N3 N4 N5
Godsonprocessor to realize Godson architecture[17]. The basic
NEON NEON NEON Integer ALU Pipe pipeline includes 12 stages, including PC, fetch, pre decoding,
Instruction Instruction Instruction Integer MUL Pipe decoding I, decoding II, register renaming, scheduling, issuing,
Queue Decode File Integer Shift Pipe
reading registers, executing, submitting I, and submitting II.
None-IEEE FP Add Pipe The first stage PC accesses the cache according to the PC
value; The second stage refers to fetching instructions after the
None-IEEE FP Mul Pipe
cache access query is completed; The third stage of pre
IEEE FP Engine decoding is to parse instructions and predict the direction and
Load/Store Permute Pipe target of branch instructions. Directly predicts the PC value of
subsequent instructions based on the PC value used for
fetching. If there is no branch instruction predicted as a jump in
B. RISC-V the fetched instructions, the PC fetches the instructions in
Rocket Core is an open source RISC-V processor core backward order. If the fetched instruction has branch
developed by Berkeley, which can be generated by Rocket instructions that are jump instructions, you need to update the
Chip, a SoC generator developed by Berkeley. RISC-V is an PC value according to the earliest one of these instructions;
open source RISC instruction set first released by the The fourth and fifth stages of decoding take instructions from
University of California, Berkeley in 2010. Since Rocket Core the instruction queue for decoding, translate the instruction
is an open source processor core launched at the same time as code into the internal code convenient for the functional unit to
Berkeley developed RISC-V architecture, it can be said to be process, and identify the instruction type, the required register
the well-known open source RISC-V Core. As shown in Fig.5, number and the immediate number that may be included; The
launch the five level pipeline executed in sequence[15]. sixth stage register renaming is for disordered execution; The
seventh stage scheduling is queue item allocation, that is,
selecting an empty item in the related queue for instructions;
The eighth stage of issue is to issue instructions from the issue
queue to the corresponding components; The ninth stage write
register is the operand required for reading; The tenth stage of
execution is operand calculation and address calculation; The
Fig. 5. The Rocket Core pipeline.
11th stage commit 1 and the 12th stage commit 2 are the
Berkeley also developed a superscalar out of order instructions that have been renamed but not submitted in the
transmission and out of order execution processor core, which pipeline. After writeback, these instructions are submitted in
also requires Rocket Chip generation. As shown in Fig.6,the the order of instructions.
BOOM pipeline is divided into 10 stages, namely Fetch,
Decode, Register Rename, Dispatch, Issue, Register Read, D. X86
Execute, Memory, Writeback and Commit. However, in the The x86 architecture is a representative variable instruction
actual implementation process, the Register Rename is divided length CISC instruction architecture. CISC instructions vary in
into two parts, which are combined with decoding and length and execution cycle, To complete an instruction pipeline,
dispatching respectively; The two stages of issuing and reading it requires one clock cycle to implement one instruction, which
the register are also combined; While submission is requires the following two points: on the one hand, the
asynchronous, it is not considered in the pipeline. Therefore, integration of the cache into the pipeline; on the other hand,
the 10 stages are actually compressed in the 7-stage pipeline pipelining the instruction decoder into two stages to provide a
shown in the figure[16]. sustained throughput of 1 instruction per clock, while decoding
the complex instruction formats of the CISC Architecture.

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 Intel's first pipeline was introduced in the i486 chip. The instruction into one or more fixed length RISC instructions; 3)
five level pipeline is Fetch, D1, D2, EX, and WB .Where, FI: The superscalar pipeline organization can perform micro
fetch the instruction from the cache. Since the entire cache line operations in disorder; 4) Submit the execution results of each
is obtained from the cache, most instructions do not need this micro operation to the register group in the order of the original
stage. On average, about 5 instructions will be acquired.D1: program flow[20].
main instruction decode. Up to three instruction bytes can be
decoded. Decode the operation that occurs in D2 stage, TABLE IV. PENTIUM 4 PIPELINE
determine the length of the instruction, and guide the 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2
instruction aligner/prefetch queue to the next instruction. D2: 0 1 2 3 4 5 6 7 8 9 0
TC TC D A Rena Q Sch Disp RF E F B D
secondary instruction decode, and memory address Next Fetc ri ll me u x l r ri
computation. Each clock decodes a memory displacement field IP h v o e g C v
e c s k e
of 1 to 4 bytes, or an immediate constant of 1 to 4 bytes. If TC Next IP=Pointer to the next instruction of trace cache TC Fetch=Trace cache fetch
there are both memory shifts and direct constants in the Alloc=Alloc Rename=Register Rename
Que=Micro operation queue Sch=Micro operation scheduling
instruction, decoding requires two D2 cycles [18]. Disp=Dispatch RF=register group
Ex=Exection Flgs=Flag
Br Ck=Branch check
PF Fetch and align instruction
IV. CONCLUSION
Decode instruction Generate
In the past, most of the new isas conceived were mainly
D1
control word RISC. RISC technology has formed two technical styles: one is
the super pipeline style that deepens the traditional pipeline,
D2 Decode control word Generate Decode control word Generate
and the other is the superscalar style that allows multiple
memory address memory address instructions to enter the pipeline per clock. Of course, many
CPUs now use superscalars together with super pipelining
Decode control word Generate Decode control word Generate technology. However, as CISC ISA, x86 is still very popular. It
E
memory address memory address converts x86 macro instructions into micro operations (Intel's
uops and AMD's ROPS). The use of uops (or ROPS) allows
WB Write result Write result
RISC style execution cores to be used to implement super
pipelines and superscalars. At present, the boundary between
U pipe V pipe RISC and CISC is not so obvious. RISC and CISC are
gradually integrated, which is equally important for pipeline
Fig. 7. Pentium superscalar pipeline. research on variable length instruction sets and pipeline
research on fixed length instruction sets.
The classic Pentium series pipeline is similar to the i486
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