ee101_hw_on_datapath.

fm

EE101 Homework on Datapath Design (based on ee201l_hw_8)

Instructor: G. Puvvada
Datapath Design

1. Datapath and control design:

You are given two 4-bit unsigned numbers, P and Q. You need to compare them and deposit the
smaller in SMALL_REG and the bigger in BIG_REG. Given on below is a complete data path.
Notice that you can bring either P or Q on bus #1 (B_ONE) or bus #2 (B_TWO). SMALL_REG is
tied only to B_ONE where as BIG_REG is tied only to B_TWO.

1.1 Datapath

March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 1 / 10 C Copyright 2017 Gandhi Puvvada
ee101_hw_on_datapath.fm

1.2 4-state state machine

1.1.1 Complete the state diagram below by writing state transition conditions.
Note: There is a tendency to write (P > Q) and such conditions but the datapath has FGS as comparator
output (and not P > Q or Q > P). FGS stands for First greater than the Second. Since the comparator is tied
to the Bus #1 (first bus) and Bus #2 (the second bus) the comparator can only say whether what is on the
first bus is greater than (or not) compared to the value standing on Bus #2. If you had put

PQL
Load P (from B_ONE) into Small.
/RESET 1 Load Q (from B_TWO) into BIG.

I CPQ
START

START
Initial Compare
P with Q
1 QPL
Load Q (from B_ONE) into Small.
Load P (from B_TWO) into BIG.
on B_ONE on B_TWO

1.1.2 Complete the one-hot implementation of the above 4-state state machine on page 3.
Before you produce the outputs, answer the following questions.

1.1.2.1 Can we say that whenever we put P or Q on one of the two buses, we may put the other on the other bus?
YES / NO

1.1.2.2 Can we say that, in the initial state, we may drive the buses even though it is not necessary? YES / NO

1.1.2.3 Can we say that we either load both SMALL_REG and BIG_REG or load none? YES / NO

1.1.3 Complete the waveform on page 4

March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 2 / 10 C Copyright 2017 Gandhi Puvvada
ee101_hw_on_datapath.fm
March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 3 / 10 C Copyright 2017 Gandhi Puvvada
 ee101_hw_on_datapath.fm
Tickmarks @ 50n
March 9, 2017March 9, 2017 9:45 pm

Properties
Labels @ 200n 0.0m 200n 400n 600n 800n 1u 1.2u 1.4u 1.6u 1.8u 2u 2.2u 2.4u

SYS_CLK wire

/RESET wire

START wire

QI wire

QCPQ wire

QPQL wire
EE101 Homework on Datapath, Control Unit, and Waveforms 4 / 10

QQPL wire

/P2B1 wire

/Q2B1 wire

/P2B2 wire

/Q2B2 wire

FGS wire

/SMALL_LOAD wire

/BIG_LOAD wire

P wire[3:0] 06 03
Q wire[3:0] 02 05
SMALL wire[3:0] XX 02 03
A
A
BIG wire[3:0] XX 06 A
A
A
A
05
C Copyright 2017 Gandhi Puvvada

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ee101_hw_on_datapath.fm

1.2 3-state state machine

1.2.1 The state machine design in 1.1 above is a ___________ (Mealy / Moore) as the outputs
generated are not influenced by the inputs. The outputs are completely determined by the current state.

Let us now reduce the states by combining CPQ and PQL into CPQL "Compare PQ and Load".
The load operation is conditional in the CPQL state as can be seen below.

This 3-state state machine is a ___________ (Mealy / Moore).

Complete the state diagram below.

/RESET
CPQL
I Compare P (on B_ONE) with Q (on B_TWO).
START

START
Initial If appropriate
Load P (from B_ONE) into Small.
Load Q (from B_TWO) into BIG.
1 QPL
Load Q (from B_ONE) into Small.
Load P (from B_TWO) into BIG.

1.2.2 Complete the one-hot implementation of the 3-state state machine on page 6 .

1.2.3 Complete the waveform on page 7 .

1.2.4 Mr. Bruin says that he can combine all the three states CPQ, PQL, and QPL of the original Moore
machine into one state in the Mealy machine state diagram shown below by him.

/RESET CPQL
Compare P (on B_ONE) with Q (on B_TWO).
I If (FGS)
Load P (from B_ONE) into Small. 1
START

START
Initial Load Q (from B_TWO) into BIG.
else // if (FGS)
Load Q (from B_ONE) into Small.
Load P (from B_TWO) into BIG.

Please explain to Mr. Bruin why his plan does not work for the given datapath and what changes need to
be made to the datapath to make his design to work. ___________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
___________________________________________________________________________________
March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 5 / 10 C Copyright 2017 Gandhi Puvvada
ee101_hw_on_datapath.fm
March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 6 / 10 C Copyright 2017 Gandhi Puvvada
 ee101_hw_on_datapath.fm
Tickmarks @ 50n
March 9, 2017March 9, 2017 9:45 pm

Properties
Labels @ 150n 0.0m 150n 300n 450n 600n 750n 900n 1.05u 1.2u 1.35u 1.5u 1.65u 1.8u 1.95u 2.1u 2.25u 2.4u

SYS_CLK wire

/RESET wire

START wire

QI wire

QCPQL wire

QQPL wire

/P2B1 wire
EE101 Homework on Datapath, Control Unit, and Waveforms 7 / 10

/Q2B1 wire

/P2B2 wire

/Q2B2 wire

FGS wire

/SMALL_LOAD wire

/BIG_LOAD wire

P wire[3:0] 04 09
Q wire[3:0] 08 01
AA
AA
SMALL wire[3:0] XX 04 AA
AA
AA
01
AA
BIG wire[3:0] XX 08 09
C Copyright 2017 Gandhi Puvvada

Page 1 of 1, Row 1, Column 1

ee101_hw_on_datapath.fm

2. Problem to solve: Add the smaller of P and Q to the smaller of X and Y and deposit the sum in
the register S. P, Q, X, Y and S are all 4-bit unsigned numbers.

S <== smaller {P, Q} + smaller {X, Y}

2.1 The DPU: The DPU (Data Path Unit) below is complete.
Please analyze the same and answer the following questions.

2.1.1 Among P, Q, X and Y _____ and ____ can be led to any of the two buses whereas ____ can only
go on to BUS #1 and ______ can only go on to Bus #2.

2.1.2 Describe the relation to be satisfied among the six control signals, P2B1, P2B2, Q2B1, Q2B2,
X2B1, and Y2B2 so that there will not be any bus-contention (collision on the bus).
Describe the relation in words as well as in boolean equation form.

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________

________________________________________________________________________
March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 8 / 10 C Copyright 2017 Gandhi Puvvada
ee101_hw_on_datapath.fm

2.1.3 Which of the following operations are feasible (to perform in one clock) using this data path?
Circle the ones that are feasible and cross-out others.

Compare P and Q Compare X and Y

Compare P and X Compare Q and Y

S <= P + Q S <= P + X S <= P + Y

S <= Q + Q S <= X + X S <= Y

2.2 State diagram for the CU (Control Unit) to perform

S <= smaller {P, Q} + smaller {X, Y}

Complete all missing transition conditions in the following state diagram. To arrive at the state
transition conditions, consider whether it is appropriate to use actual signals such as FLS (or
FLS) which are available in the datapath or whether it is appropriate to use fictitious signals (not
available in the datapath) such as P>Q, X>Y, etc.
If P = Q and X = Y, which of the following sums gets deposited in S as per your state diagram?
Circle the right one(s).
P+X P+Y Q+X Q+Y

1
1
3
Q SPX
S <- P + X
2 Q XY1
Compare
X, Y 4
~Reset Q SPY
0 On BUS #1 S <- P + Y
1 Q PQ
QI START
Compare
START Initial
P, Q
6
On BUS #2 Q SQX
On BUS #1 5 S <- Q + X
Q xy2
Compare
X, Y 7
Q SQY
1 On BUS #2 S <- Q + Y

March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 9 / 10 C Copyright 2017 Gandhi Puvvada
ee101_hw_on_datapath.fm

2.3 Assuming that a ONE-HOT method is used for implementing this state machine, complete the
OFL (Output Function Logic) table below and produce the 7 outputs using standard gates (AND,
OR, NAND, NOR, INVERTER).

OFL (Output Function Logic) Table

Output

S_LOAD
Control

Q2B1

Q2B2

X2B1

Y2B2
P2B1

P2B2
Current
State

QI
QPQ
QXY1
QXY2
QSPX
QSPY
QSQX
QSQY

P2B1

P2B2

Q2B1

Q2B2

X2B1

Y2B2

S_LOAD

March 9, 2017March 9, 2017 9:45 pm EE101 Homework on Datapath, Control Unit, and Waveforms 10 / 10 C Copyright 2017 Gandhi Puvvada
3 ( 66 points) min. Make A close to B -- Mealy State machine design

3.1 This question is based on ee354L_MT_Fall2019 exam Q#4. First please go through the "Make A
close to B" question and its solution provided to you through EE457_HW1A. This question is a
modification of that question. It makes sense only after you go through that original question.

Here also, A and B are 12-bit unsigned numbers, A is initially less than B, and we add initially
100’s to A until it either becomes equal to B or goes beyond B (overshoots). But, if it overshoots,
we immediately subtract a 100 to take it back to below B, and start adding 10’s until either it (the
A) equals B or overshoots again. If it overshoots, we subtract a 10 to take it back to below B.
So, the final reported A is either equal to B, or just below B (i.e. A falls into the range [B-9 : B]).
We use a Flag F to distinguish if we should be adding 100’s or 10’s and should be subtracting a
100 or a 10 if it overshoots. The Flag also helps in exit condition. Complete the design below.
~RESET

START Your C1 = _______________________

C1

INI ADJ
(INITIAL) (ADJUST)
START if (A B)
A <= Ain; if (A B) //lines to set F
B <= Bin; if (F == ) if (F == )
F <= 0; A <= A + 100; A <= A - 100;
else else

DONE
C1

Miss Trojan used At (for A temporary) and avoided subtractions. She adds 100’s or 10’s to At.
She copies At to A only if At is "good" (i.e. if At is less than or equal to B). If At overshoots,
she reinitializes At with the current A (which would never go beyond B). Complete the design.
~RESET

START Your C2 = _______________________

C2

INI ADJ
(INITIAL) (ADJUST) //lines to set F
START if (At B)
A <= Ain; if (At B)
At <= Ain; if (F == ) A <= At;
B <= Bin; At <= At + 100; if (At B)
F <= 0; else

DONE
C2

C Copyright 2020 Gandhi Puvvada

3.1.1 Complete entries in the tables below until you reach the DONE state.

4 ( 48 points) min. Array processing -- state machine

This question is based on ee354L_MT_Fall2019 A[I] B[J] C[K]

exam Q#5. Here, we have two 10-element arrays, 0 5 0 5 0 4
A[I] and B[J]. We need to take even numbers 1 5 1 20 1 20
from these two arrays and deposit into C[K]. The 2 4 2 5 2 2
C[K] is a 20-element array to cater for the 3 2 3 5 3 8
extreme case of all even elements in A[I] and B[J]. 4 5 4 8 4 10
We need to alternate between A[I] and B[J]. First 5 5 5 18 5 18
we search A[I] for an even element in it and 6 5 6 5 6 6
deposit that even element into C[I]. Then we 7 10 7 5 7 12
search B[I] for an even element in it and deposit 8 5 8 6 8
that even element into C[I]. One of the two arrays, 9 5 9 12 9
A[I] or B[J], will exhaust first. Then we transfer
18
the even elements of the remaining array into
19
C[K] (i.e. we empty-out that remaining array).
Notice that, no element in A[I] or B[J] needs more
than one clock to process it. Since, we do not waste any clocks, the process completes exactly in
20 clocks!

While it is possible to simultaneously search both A[I] and B[J] for their respective even numbers
and keep them ready, let us not do that for this question.

Complete the state diagram on the next page and state sequence below for the above data.

C Copyright 2020 Gandhi Puvvada

 The RTL inside the states is partially complete. Incrementation of the three indexes, I, J, and K
is left out for you to complete.

Complete the RTL in the states and also the 10 state transition conditions.
~RESET

START

INI
(INITIAL)
I <= 0;
J <= 0;
K <= 0;
START

SEAI SEBJ
(Search A[I]) (Search B[J])

if (A[I][0] == 0) if (B[J][0] == 0)
C[K] <= A[I]; C[K] <= B[J];

To INI
1

DONE

EMBJ EMAI
(Empty-Out B[J]) (Empty-Out A[I])

if (B[J][0] == 0) if (A[I][0] == 0)
C[K] <= B[J]; C[K] <= A[I];
K <= K + 1;

C Copyright 2020 Gandhi Puvvada

 ee102_midterm2_Sp2005_Question_5.fm

5 ( 8 + 6 + 8 + 6 + 6 = 34 points) 30 min.
8
pts 5.1 Reproduced below is the state diagram for the divider from your classnotes. A student has
modified state transition conditions on the two diverging arrows on the "C" state as shown.
X>Y
START Modified design Note
X>= Y
~RESET

C
C
Does it work? Yes / No START
(COMPARE
and UPDATE)
I
(INITIAL) (COMPARE
START
X <== XIN;
and UPDATE)
If X >= Y
If it works, explain how it is
Y <== YIN; X <== X - Y; better or worse in performance?
Q <== 0; Q <== Q + 1;
If it does not work, state why it does not work. Note
END
X>Y
X
>=
EN Y D
D
(DONE)

Classnotes design

6
pts 5.2 In light of the above question, can you suggest an improvement to the Moore machine for the
divider (reproduced from the classnotes below) by modifying the state transition conditions only?
START
1
Explanation of improvement (if possible)
~RESET

or explanation why no improvement is possible:

I C U
(INITIAL) START (COMPARE) X>= Y (UPDATE)
X <== XIN; X <== X - Y;
Y <== YIN; Q <== Q + 1;
Q <== 0;
END
X>

EN D
=Y

D
(DONE)

Classnotes design

4/29/2005 EE102L Midterm #2 - Spring 2005 1 / 2 C Copyright 2005 Gandhi Puvvada

 ee102_midterm2_Sp2005_Question_5.fm

8 5.3.1 Miss Trojan suggested a better Moore machine for the divider (better than the one in the classnotes
pts and reproduced above) as shown below.
Using the example 40 / 2 = 20, R=0, explain
START "If" removed X > = Y
~RESET

Note: "+"
why this is better than our classnotes design.
I C U
(COMPARE X>=Y (UNDO)
(INITIAL) START and UPDATE)
X <== XIN; X <== X + Y;
Y <== YIN; X <== X - Y; Q <== Q - 1;
Q <== 0; Q <== Q + 1;
END

1 Note: "-"
EN D
D
(DONE)

6
pts 5.3.2 Mr. Trojan says that there is still a little more to improve by playing with the state transition
arrows and conditions! Can you guess what is in his mind by completing the design below?
Using the example, 40 / 2 = 20, R=0, explain why
START "If" removed
~RESET

this is little more better than Miss Trojan’s design.

Note: "+"
I C U
(INITIAL) (COMPARE (UNDO)
START and UPDATE)
X <== XIN; X <== X + Y;
Y <== YIN; X <== X - Y; Q <== Q - 1;
Q <== 0; Q <== Q + 1;
END

1 Note: "-"
EN D
D
(DONE)

6
pts 5.3.3 Mr. Trojan says that the resulting datapath of Miss Trojan’s design or his design is a little more
expensive. Please explain.
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________
____________________________________________________________________________

4/29/2005 EE102L Midterm #2 - Spring 2005 2 / 2 C Copyright 2005 Gandhi Puvvada

 ee102_midterm2_Sp2005.fm

4 ( 8 points) 5 min.
Design a special down counter which counts down (7, 6, 5, ...). However, it shall always skip 4.
So the sequence shall be 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0, 7, 6, 5, 3, 2, 1, 0, ......
Use the mux. to skip 4.
Subtracter
Register
Mux
A0
A1
A2 S0 I00 D Q
S1 I01 LSB
1 S2 I02 Y0 Q0
B0
0 B1 Y1 D Q Q1
B2 I10 Y2 Q2
0
I11
I12 D Q
S
SysClk

5 ( 8 + 6 + 8 + 6 + 6 = 34 points) 30 min.
8
pts 5.1 Reproduced below is the state diagram for the divider from your classnotes. A student has
modified state transition conditions on the two diverging arrows on the "C" state as shown.
X>Y
START Modified design Note
~RESET

X>= Y
C
C
Does it work? Yes / No START
(COMPARE
and UPDATE)
I
(INITIAL) (COMPARE
START
X <== XIN;
and UPDATE)
If X >= Y
If it works, explain how it is
Y <== YIN; X <== X - Y; better or worse in performance?
Q <== 0; Q <== Q + 1;
If it does not work, state why it does not work. Note
END
X>Y
X>
=Y
X
>=
Y

EN D
D
(DONE)

Classnotes design

6
pts 5.2 In light of the above question, can you suggest an improvement to the Moore machine for the
divider (reproduced from the classnotes below) by modifying the state transition conditions only?
START
1
Explanation of improvement (if possible)
~RESET

or explanation why no improvement is possible:

I C U
(INITIAL) START (COMPARE) X>= Y (UPDATE)
X <== XIN; X <== X - Y;
Y <== YIN; Q <== Q + 1;
Q <== 0;
END
X>
=Y
X
>=
Y

EN D
D
(DONE)

Classnotes design

EE102L Midterm #2 - Spring 2005 7 / 10 C Copyright 2005 Gandhi Puvvada