Week 4: Assignment 4

Q1: The two types of device scaling are _____.

a. Constant current scaling and constant voltage scaling.
b. Constant current scaling and constant channel length scaling.
c. Constant field scaling and constant voltage scaling.
d. Constant field scaling and constant channel length scaling.
Ans: (c) constant field scaling and constant voltage scaling
Q2: The CMOS inverter can be used as an amplifier when:
a. NMOS operates in linear region and PMOS operates in saturation region.
b. NMOS operates in saturation region and PMOS operates in linear region.
c. Both NMOS and PMOS operates in linear region.
d. Both NMOS and PMOS operates in saturation region.
Ans: (d) Both NMOS and PMOS operates in saturation region.
Q3: Noise margin of CMOS inverter is _____ that of a BJT based inverter.
a. Greater than
b. Smaller than
c. Equal to
d. None of the above
Ans: (a) greater than
Q4: An ideal inverter exhibits ____ input impedance and ____ output impedance.
a. High; High
b. High; Low
c. Low; High
d. Low; Low
Ans: (b) High; Low
Q5: In a CMOS inverter, increasing the PMOS width improves _______, but it also degrades ______.
a. tpHL; tpLH
b. tpLH; tpHL
c. VOH; VOL
d. VOL; VOH
Ans: (b) tpLH; tpHL
Q6: Find the optimal size of inverter A2 and A3 in the following inverter chain (in terms of size of A1).
Consider input capacitance of A1 to be C1 and load capacitance CL = 27C1

a. A2 = 3 A1; A3 = 9 A1
 b. A2 = 9 A1; A3 = 3 A1
c. A2 = 13 A1; A3 = 14 A1
d. A2 = 14 A1; A3 = 13 A1
Ans: (a) A2 = 3 A1; A3 = 9 A1
Q7: For the inverter chain shown below, find the minimum delay through the inverter chain. Consider
self-loading (γ=1), input capacitance of A1 to be C1 and load capacitance CL = 27C1 .

a. 18 tp0
b. 15 tp0
c. 12 tp0
d. 9 tp0
Ans: (c) 12 tp0
Q8: Increasing fan-out of a CMOS inverter _____ the propagation delay.
a. Increases
b. Decreases
c. Does not affect
d. Decreases exponentially.
Ans: (a) increases
Q9: A fast CMOS inverter can be made by keeping ______.
a. High output capacitance
b. Low output capacitance
c. High on resistance
d. Low input impedance
Ans: (b) Low output capacitance
Q10: The intrinsic delay of an inverter is _________ the transistor size and _______ the physical
layout and the technology parameter.
a. Independent of; Independent of
b. Independent of; Depends on
c. Dependent on; Independent of
d. Dependent on; Depends on
Ans: (b) Independent of; Depends on
 Week 4: Assignment 4: Brief Explanation

Q1. Explanation:
Two types of scaling are constant field scaling and constant voltage scaling.
Constant field scaling: it yields the reduction in power-delay-product of the transistor. Hence it
requires the reduction in power supply for the feature size.
Constant voltage scaling: this is preferred scaling technique as it provides voltage compatibility with
other technologies.
Q2. Explanation:
When both NMOS and PMOS are in saturation, the inverter remains in its transition region. Here
small changes in input voltage can cause a large change in output voltage.
Q3. Explanation:
Noise margin of CMOS inverter is greater than BJT based inverter.
Q4. Explanation:
An ideal inverter exhibits high input impedance and low output impedance.
Q5. Explanation:
Improving the PMOS width improves tpLH of the inverter increasing the charging current, but it also
degrades tPHL by causing a large parasitic capacitance. Because as you go on increasing the PMOS
width right, the PMOS itself might be doing very good, but then it will start loading your external
load capacitance.
Q6. Explanation:
CL/C1 has to be evenly distributed across N=3 stages
𝑁 3
𝑓 = √𝐹 = √27 = 3

𝐴2 = 𝑓𝐴1 = 3𝐴1 ; 𝐴3 = 𝑓 2 𝐴1 = 9𝐴1

Q7. Explanation:
𝑁
√𝐹
𝑡𝑝 = 𝑁𝑡𝑝𝑜 (1 + ) = 3 × (1 + 3) = 12 𝑡𝑝𝑜
𝛾

Q8. Explanation:
Increasing fan-out of a CMOS inverter increases the propagation delay.
Q9. Explanation:
A fast CMOS inverter can be made by keeping low output capacitance and decreasing the on
resistance of the transistors.
Q10. Explanation:
The intrinsic delay of inverter is independent of the transistor size and depends on the physical layout
and the technology parameter.