UNIT II: ELEMENTS OF IOT

2.1 Hardware Components- Computing- Arduino

The Internet of Things (IoT) is a scenario in which objects, animals or people are provided with
single identifiers and the capability to automatically transfer and the capability to automatically
transfer data more to a network without requiring human-to-human or human-to-computer
communication.

Arduino Board:
 An Arduino is actually a microcontroller based kit.
 It is basically used in communications and in controlling or operating many devices.
 Arduino UNO board is the most popular board in the Arduino board family.
 In addition, it is the best board to get started with electronics and coding.
 Some boards look a bit different from the one given below, but most Arduino’s have
majority of these components in common.
 It consists of two memories- Program memory and the data memory.
 The code is stored in the flash program memory, whereas the data is stored in the data
memory.
 Arduino Uno consists of 14 digital input/output pins (of which 6 can be used as PWM
outputs), 6 analog inputs, a 16 MHz crystal oscillator, a USB connection, a power jack,
an ICSP header, and a reset button
16.AREF
17.Arduino Reset 15.Digital I/O

14.TX and RX

LEDs

1.Power
13.Power
USB LED

indicator
4.Crystal Oscillator

12.ICSP pin
3.Voltage

Regulator
11.Main
microcontroller

2.Power
(Barrel Jack)

5.Arduino Reset 6,7,8,9.Pins (3.3,

10.Analog pins
5, GND, Vin)

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 1. Power USB
Arduino board can be powered by using the USB cable from your computer.
All you need to do is connect the USB cable to the USB connection (1).
2. Power (Barrel Jack)
Arduino boards can be powered directly from the AC mains power supply by
connecting it to the Barrel Jack (2).
3. Voltage Regulator
The function of the voltage regulator is to control the voltage given to the
Arduino board and stabilize the DC voltages used by the processor and other
elements.
4. Crystal Oscillator
The crystal oscillator helps Arduino in dealing with time issues. How does
Arduino calculate time? The answer is, by using the crystal oscillator. The number
printed on top of the Arduino crystal is 16.000H9H. It tells us that the frequency is
16,000,000 Hertz or 16 MHz.
5,17.Arduino Reset
You can reset your Arduino board, i.e., start your program from the
beginning. You can reset the UNO board in two ways. First, by using the reset button
(17) on the board. Second, you can connect an external reset button to the Arduino
pin labelled RESET (5).
6,7,8,9.Pins (3.3, 5, GND, Vin)
• 3.3V (6) − Supply 3.3 output volt
• 5V (7) − Supply 5 output volt
• Most of the components used with Arduino board works fine with 3.3 volt and 5 volt.
• GND (8)(Ground) − There are several GND pins on the Arduino, any of
which can beused to ground your circuit.
• Vin (9) − This pin also can be used to power the Arduino board from an
external powersource, like AC mains power supply.
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 10. Analog pins
The Arduino UNO board has six analog input pins A0 through A5. These pins
can read the signal from an analog sensor like the humidity sensor or temperature sensor
and convert it into a digital value that can be read by the microprocessor.

11. Main microcontroller

Each Arduino board has its own microcontroller (11). You can assume it as
the brain of your board. The main IC (integrated circuit) on the Arduino is slightly
different from board to board. The microcontrollers are usually of the ATMEL
Company. You must know what IC your board has before loading up a new program
from the Arduino IDE. This information is available on the top of the IC. For more
details about the IC construction and functions, you can refer to the data sheet.

12. ICSP pin

Mostly, ICSP (12) is an AVR, a tiny programming header for the Arduino
consisting of MOSI, MISO, SCK, RESET, VCC, and GND. It is often referred to as
an SPI (Serial Peripheral Interface), which could be considered as an "expansion" of
the output. Actually, you are slaving the output device to the master of the SPI bus.

13. Power LED indicator

This LED should light up when you plug your Arduino into a power source to
indicate that your board is powered up correctly. If this light does not turn on, then there
is something wrong with the connection.

14. TX and RX LEDs

On your board, you will find two labels: TX (transmit) and RX (receive). They
appear in two places on the Arduino UNO board. First, at the digital pins 0 and 1, to
indicate the pins responsible for serial communication. Second, the TX and RX led (13).
The TX led flashes with different speed while sending the serial data. The speed of
flashing depends on the baud rate used by the board. RX flashes during the receiving
process.

15. Digital I/O

The Arduino UNO board has 14 digital I/O pins (15) (of which 6 provide PWM
(Pulse Width Modulation) output. These pins can be configured to work as input digital
pins to read logic values (0 or 1) or as digital output pins to drive different modules like
LEDs, relays, etc. The pins labeled “~” can be used to generate PWM.

16. AREF
AREF stands for Analog Reference. It is sometimes, used to set an external
reference voltage (between 0 and 5 Volts) as the upper limit for the analog input pins.

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2.2 Hardware Components- Computing- Raspberry Pi

The Internet of Things (IoT) is a scenario in which objects, animals or people are
provided with single identifiers and the capability to automatically transfer and the
capability to automatically transfer data more to a network without requiring human-
to-human or human-to-computer communication.

Raspberry Pi

 The Raspberry Pi is a very cheap computer that runs Linux, but it also
provides a set of GPIO (general purpose input/output) pins that allow you to
control electronic components for physical computing and explore the Internet
of Things (IoT).
 Raspberry Pi was basically introduced in 2006.
 A Raspberry Pi is of small size i.e., of a credit card sized single board
computer, which is developed in the United Kingdom(U.K) by a foundation
called Raspberry Pi.

 There have been three generations of Raspberry Pis: Pi 1, Pi 2, and Pi 3

 The first generation of Raspberry (Pi 1) was released in the year 2012, that
has two typesof models namely model A and model B.
 Raspberry Pi can be plugged into a TV, computer monitor, and it uses a
standardkeyboard and mouse.
 All models feature on a Broadcom system on a chip (SOC), which includes
chip graphics processing unit GPU (a Video Core IV), an ARM compatible
and CPU.
 The CPU speed ranges from 700 MHz to 1.2 GHz for the Pi 3 and on
board memoryrange from 256 MB to 1 GB RAM.
 Most boards have one to four USB slots, composite video output, HDMI
and a 3.5 mmphone jack for audio. Some models have Wi-Fi and Bluetooth.
 Several generations of Raspberry Pis have been released.
 All models feature a Broadcom system on a chip (SoC) with an integrated
ARM- compatible central processing unit (CPU) and on-chip graphics
processing unit (GPU).
 Processor speed ranges from 700 MHz to 1.4 GHz for the Pi 3 Model B+ or
1.5 GHz for the Pi 4; on-board memory ranges from 256 MB to 1 GB with
up to 4 GB available onthe Pi 4 random-access memory (RAM).
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Components and Peripherals

 Voltages: Two 5V pins and two 3V3 pins are present on the board, as well
as a number of ground pins (0V). The remaining pins are all general purpose
3V3 pins
 A GPIO pin designated as an output pin can be set to high (3V3) or low (0V).
A GPIO pin designated as an input pin can be read as high (3V3) or low (0V).
 Processor & RAM: Raspberry based on ARM11 processor. Latest version
supports 700MHz processor and 512MB SDRAM. The Central processing
unit is the brain of the raspberry pi board and that is responsible for carrying
out the instructions of the computer through logical and mathematical
operations.

 Ethernet: The Ethernet port of the raspberry pi is the main gateway for
communicating with additional devices. The raspberry pi Ethernet port is used
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 to plug your home router to access the internet.

 USB Ports: It has 2 USB ports. USB port provides current up to 100mA. For
connecting devices that draw current more than 100mA, an external USB
powered hub is required.
 Ethernet Port: It has standard RJ45 Ethernet port. Connect Ethernet cable or
USB wifi adapter to provide internet connectivity.
 HDMI Output: It supports both audio and video output. Connect raspberry Pi
to monitor using HDMI cable.
 Composite video Output: Raspberry comes with a composite video output
with an RCAjack that supports both PAL and NTSC video output.
 Audio Output: It has 3.5mm audio output jack. This audio jack is used for
providing audio output to old television along with RCA jack for video.
 GPIO Pins: It has a number of general purpose input/output pins. These pins
are used to connect other electronic components. For example, you can
connect it to the temperature sensor to transmit digital data.
 Display Serial Interface (DSI): DSI interface are used to connect an LCD
panel to Raspberry PI.
 Cameral Serial Interface(CSI): CSI interface are used to connect a camera
module to Raspberry PI.
 SD Card slot: Raspberry does not have built in OS and storage. Plug in an
SD card loaded with Linux to SD card slot.
 Power Input: Raspberry has a micro USP connector for power input.
 Memory: The raspberry pi model A board is designed with 256MB of
SDRAM and model B is designed with 51MB.Raspberry pi is a small size PC
compare with other PCs. The normal PCs RAM memory is available in
gigabytes. But in raspberry pi board, the RAM memory is available more than
256MB or 512MB
 Status LEDs: Raspberry has 5 status LEDs.

Status LED Function

ACT SD card Access
PWR 3.3V power is present
FDX Full duplex LAN Connected
LNK Link/Network Activity
100 100 Mbit LAN connected
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Raspberry PI Interfaces:

 It supports SPI, serial and I2C interfaces for data transfer.

 Serial: Serial Interface on Raspberry has receiver (Rx) and Transmit (Tx) pins
for communication with serial peripherals.
 SPI: Serial Peripheral Interface (SPI) is a synchronous serial data protocol
used for communicating with one or more peripheral devices. In an SPI
connection, there is one master device and one or more peripheral devices.
There are 5 pins Raspberry for SPI interface.
o MISO (Master in Slave Out): Master line for sending data to the peripherals.
o MOSI (Master Out Slave In): Slave Line for sending data to the master.
o SCK (Serial Clock): Clock generated by master to synchronize data
transmission.
o CE0 (Chip Enable 0): To enable or disable devices.
o CE1 (Chip Enable 1): To enable or disable devices.
 I2C: I2C Interface pins are used to connect hardware modules. I2C
interface allowssynchronous data transfer with two pins: SDA(data line) and
SCL (Clock Line)

Features of Raspberry PPI

1. Where the system processing is huge. They can process high end programs for
applications like Weather Station, Cloud server, gaming console etc. With 1.2GHz
clock speed and 1 GB RAM RASPBERRY PI can perform all those advanced
functions.

2. RASPBERRY PI 3 has wireless LAN and Bluetooth facility by which you can
setup WIFI HOTSPOT for internet connectivity.

3. RASPBERRY PI had dedicated port for connecting touch LCD display which is a
feature that completely omits the need of monitor.

4. RASPBERRY PI also has dedicated camera port so one can connect camera
without any hassle to the PI board.

5. RASPBERRY PI also has PWM outputs for application use.

6. It supports HD steaming

Applications

 Hobby projects.
 Low cost PC/tablet/laptop
 IoT applications
 Media center
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  Robotics
 Industrial/Home automation
 Server/cloud server
 Print server
 Security monitoring
 Web camera
 Gaming
 Wireless access point
2.3 ARM Cortex-A class processor

The ARM Cortex-A is a group of 32-bit and 64-bit RISC ARM processor cores. The cores are
intended for application use.

The group consists of 32-bit cores: ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-
A8, ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15, ARM Cortex-A17 MP
Core,[1] and ARM Cortex-A32,[2]

64-bit cores: ARM Cortex-A34, ARM Cortex-A35, ARM Cortex-A53, ARM Cortex-A55, ARM
Cortex-A57, ARM Cortex-A72, ARM Cortex-A73, ARM Cortex-A75, ARM Cortex-A76, ARM
Cortex-A77, ARM Cortex-A78, ARM Cortex-A510 and ARM Cortex-32 bitA710.

64-bit 64-bit 32- bit

Year Core Year Core Year Core

2012 Cortex-A53 2018 Cortex-A76 2005 Cortex-A8

2012 Cortex-A57 2018 Cortex-A65AE 2007 Cortex-A9

2015 Cortex-A35 2018 Cortex-A76AE 2009 Cortex-A5

2015 Cortex-A72 2019 Cortex-A77 2010 Cortex-A15

2016 Cortex-A34 2020 Cortex-A78 2011 Cortex-A7

2016 Cortex-A73 2021 Cortex-A510 2013 Cortex-A12

2017 Cortex-A55 2021 Cortex-A710 2014 Cortex-A17

2017 Cortex-A75 2016 Cortex-A32

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The Memory Management Unit

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical
addresses. It also controls accesses to and from external memory.

The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:

 Page table entries that support:

 16MB super sections. The processor supports super sections that consist of 16MB
blocks of memory.
 1MB sections.
 64KB large pages.
 4KB small pages.

The L1 memory system

The L1 memory system has:

 separate instruction and data caches each with a fixed line length of 32 bytes
 64-bit data paths throughout the memory system
 support for four sizes of memory page
 export of memory attributes for external memory systems
 Support for Security Extensions.

Performance Monitoring Unit

Each Cortex-R52 core includes performance monitors which implement the Arm PMUv3
architecture. These enable you to gather various statistics on the operation of the core and its
memory system during runtime. These provide useful information about the behavior of the
processor that you can use when debugging or profiling code.

The PMU provides four counters. Each counter can count any of the events available in the core.
The absolute counts recorded might vary because of pipeline effects. This has negligible effect
except in cases where the counters are enabled for a short time.

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FEATURES

The Cortex-A35 processor includes the following features:

 Full implementation of the Armv8-A A64, A32, and T32 instruction sets.

 In-order pipeline with direct and indirect branch prediction.

 Separate Level 1 (L1) data and instruction side memory systems with a Memory
Management Unit (MMU).
 Level 2 (L2) memory system that provides cluster memory coherency.

 Optional L2 cache.

 Cache protection in the form of Error Correction Code (ECC) or parity on all RAM
instances, except for the L2 victim RAMS.
 There are two implementation options:
 CPU cache protection.

 Snoop Control Unit (SCU)-L2 cache protection.

2.4 ARM CORTEX-M CLASS PROCESSOR

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm
Holdings. These cores are optimized for low-cost and energy-efficient integrated circuits, which
have been embedded in tens of billions of consumer devices.[1] Though they are most often the
main component of microcontroller chips, sometimes they are embedded inside other types of
chips too. The Cortex-M family consists of Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3,
Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55. The Cortex-M4 /
M7 / M33 / M35P / M55 cores have an FPU silicon option, and when included in the silicon
these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the
core variant.

The ARM Cortex-M family are ARM microprocessor cores which are designed for use
in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as
dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management
controllers, I/O controllers, system controllers, touch screen controllers, smart battery
controllers, and sensors controllers.
The main difference from the Cortex-A core is that there is no memory management
unit (MMU). A full-fledged operating system does not normally run on this class of processor.
Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping
away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward.
Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from
32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.

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 32-bit 32-bit

Year Core Year Core

2004 Cortex-M3 2014 Cortex-M7

2007 Cortex-M1 2016 Cortex-M23

2009 Cortex-M0 2016 Cortex-M33

2010 Cortex-M4 2018 Cortex-M35P

2012 Cortex-M0 2020 Cortex-M55

Silicon customization
Integrated Device Manufacturers (IDM) receives the ARM
Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to
perform architectural level optimizations and extensions. This allows the manufacturer to
achieve custom design goals, such as higher clock speed, very low power consumption,
instruction set extensions (including floating point), optimizations for size, debug support, etc.
To determine which components have been included in a particular ARM CPU chip, consult the
manufacturer datasheet and related documentation.
Some of the silicon options for the Cortex-M cores are:

 SysTick timer: A 24-bit system timer that extends the functionality of both the processor and
the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an
additional configurable priority SysTick interrupt Though the SysTick timer is optional, it is
very rare to find a Cortex-M microcontroller without it. If a Cortex-M33 microcontroller has
the Security Extension option, then it has two SysTicks, one Secure and one Non-secure.
 Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For
example, writing to an alias word will set or clear the corresponding bit in the bit-band
region. This allows every individual bit in the bit-band region to be directly accessible from a
word-aligned address. In particular, individual bits can be set, cleared, or toggled from
C/C++ without performing a read-modify-write sequence of instructions. Though the bit-
band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller
without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.
 Memory Protection Unit (MPU): Provides support for protecting regions of memory through
enforcing privilege and access rules. It supports up to eight different regions, each of which
can be split into a further eight equal-size sub-regions.
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 Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines,
data, stacks. Other than cache, it is typically the fastest RAM in the microcontroller.

Instruction sets
The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture, the Cortex-M3 implements
the ARMv7-M architecture, the Cortex-M4 / Cortex-M7 implements the ARMv7E-
M architecture, the Cortex-M23 / M33 / M35P implement the ARMv8-M architecture, and the
Cortex-M55 implements the ARMv8.1-M architecture. The architectures are binary instruction
upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available
for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-
M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute
without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P. Only
Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-
bit ARM instruction set isn't supported.
All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1,
some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 /
Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions
of the Cortex-M family.

2.5 ARM CORTEX-M0 PROCESSOR ARCHITECTURE

2.5.1 INTRODUTION

The Cortex-M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad
range of embedded applications. It offers significant benefits to developers, including:

 simple, easy-to-use programmers model

 highly efficient ultra-low power operation
 excellent code density
 deterministic, high-performance interrupt handling
 Upward compatibility with the rest of the Cortex-M processor family.

The Cortex-M0 processor is built on a high-performance processor core, with a 3-stage pipeline
von Neumann architecture, making it ideal for demanding embedded applications. The processor
is extensively optimized for low power and area, and delivers exceptional power efficiency
through its efficient instruction set, providing high-end processing hardware including either:

 a single-cycle multiplier, in designs optimized for high performance

 A 32-cycle multiplier, in designs optimized for low area.

The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt Controller
(NVIC), to deliver industry-leading interrupt performance. The NVIC:

 includes a non-maskable interrupt (NMI)

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  provides:
 a zero-jitter interrupt option
 Four interrupt priority levels.

The tight integration of the processor core and NVIC provides fast execution of interrupt service
routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to abandon and restart load-multiple and store-
multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any
code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead
when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with sleep mode. Optionally, sleep mode
support can include a deep sleep function that enables the entire device to be rapidly powered
down.

Cortex-M0 processor features

 high code density with 32-bit performance

 tools and binaries upwards-compatible across the Cortex-M processor family
 integrated low-power sleep modes
 fast code execution permits slower processor clock or increases sleep mode time
 hardware multiplier
 zero-jitter interrupt handling
 Extensive debug capabilities.

2.5.2 ARCHITECTURE:

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Key features of Arm Cortex-M0 core

 Armv6-M architecture
 Bus interface AHB-lite , Von Neumann bus architecture
 Thumb/Thumb-2 subset instruction support
 3-stages pipeline
 Non-maskable interrupt + 1 to 32 physical interrupts
 Wakeup interrupt controller
 Hardware single-cycle ((32x32) multiply
 Several sleep modes, with integrated Wait For Interrupt (WFI) and Wait for Event (WFE)
plus sleep on exit capability, sleep and deep sleep signals
 Several retention modes are available depending on the implementation
 JTAG and Serial Wire Debug ports with up to 4 breakpoints and 2 watch points

The small footprint of the core allows it to either be used as a single core in small devices or as
an additional embedded companion core when specific hardware isolation or task partitioning is
required. Thanks to the advancements in silicon manufacturing technologies, the lithography
process moved from 180 to 90nm and lower, and the core silicon real-estate now reaches
0.03mm² in 90nm lithography.

The Cortex-M0 core does not impact the trade-off to be made among the elements of the typical
MCU architecture based on I/O, analog and non-volatile memories. The bus size (8, 16 or 32
bits) is therefore no longer relevant when partitioning MCU portfolios.

M0-based microcontrollers are widely used and offer high benefits in entry-level applications.
They meet computing performance requirements and their basic architecture allows M0 MCUs
to reach ultra-low-power performance in applications where the number of switching gates is
minimized. The Cortex®-M0 core reduces noise emissions and meets performance requirements
using an optimal clock speed.

The dynamic power of the core ranges from 5 to 50µW/MHz, depending on the technology used.
However, the core itself is not representative of the overall power consumption of a device and is
not the only factor to take into account. It is therefore important to carefully read product
datasheets.

2.6 ARM CORTEX – MO BLOCK DIAGRAM

ARM Cortex is categorized into three classes:

(1) Cortex-A: High performance (2) Cortex-M: Low power, low cost (3) Cortex-R: real-time
applications.
The Cortex-M0 is the smallest core in Cortex-M category, and it is the core that we will
implement. The ARM architecture adapted in Cortex-M0 is ARMv6-M the core has 3 stages and
a single Advanced High performance (AHB) Lite interface .Cortex-M0 implements the
following instructions:
• All 16-bit Thumb-1 instructions from ARMv7-M except CBZ, CBNZ, IT.
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 • The 32-bit Thumb-2 instructions BL, DMB, DSB, ISB, MRS, MSR.
Fig. 1 shows the Cortex-M0 functional block diagram. The relationship between cores and other
modules such as interrupt controller and debug modules are stated. In this paper we only
implement

The core and use AHB-Lite interface to communicate with external memory. Debug access port
(DAP), wakeup interrupt controller (WIC), and other optional modules are not implemented.

B. Pipeline Stages in Cortex-M0

The three pipeline stages in Cortex- M0: (1) Fetch (2) decode and (3) Execute. The first step in
implementation of the processor core is to get this 3-stage pipeline in place.

C. AMBA AHB-Lite Interface

The most common Advanced Microcontroller Bus Architecture (AMBA) Advanced High-
performance Bus (AHB)-Lite slaves are internal memory devices, external memory interfaces,
and high bandwidth peripherals. A pair of decoders and multiplexers can interface memories as
slave modules with the master (Cortext-M0). The second implementation step is designing AHB-
Lite interface to add program memory, and stack to Cortex-M0 using the mechanism depicted.

D. Cortex-M0 Instructions
Considering all instruction formats and variations, ARM Cortex-m0 has seventy 16-bit and six
32-bit instructions. We categorize all instructions into five
Groups:
1. Arithmetic: Move, Add, Subtract, Multiply, Shift, Rotate, Extend.
2. Logic: AND, XOR, OR, Bit clear, Move NOT, AND test.
3. Memory: Store, Load, Push, Pop.
4. Flow control: Compare, Branch.
5. Hint and Barriers.
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2.7 CORTEX-M0 INSTRUCTION SET SUMMARY
The Cortex M0 processor implements a version of the Thumb instruction set. Table 1 lists the
supported instructions.
Note

In Table 1:

angle brackets, <>, enclose alternative forms of the operand

braces, {}, enclose optional operands and mnemonic parts

the Operands column is not exhaustive.

For more information on the instructions and operands, see the instruction descriptions.

Table 1 Cortex-M0 instructions

Mnemonic Operands Brief description Flags See

ADC, ADD, RSB,

ADCS {Rd,} Rn, Rm Add with Carry N,Z,C,V
SBC, and SUB

{Rd,} Rn, ADC, ADD, RSB,

ADD{S} Add N,Z,C,V
<Rm|#imm> SBC, and SUB

PC-relative Address to
ADR Rd, label - ADR
Register

ADC, ADD, RSB,

ANDS {Rd,} Rn, Rm Bitwise AND N,Z
SBC, and SUB

{Rd,} Rm, ASR, LSL, LSR, and

ASRS Arithmetic Shift Right N,Z,C
<Rs|#imm> ROR

B{cc} label Branch {conditionally} - B, BL, BX, and BLX

AND, ORR, EOR,

BICS {Rd,} Rn, Rm Bit Clear N,Z
and BIC

BKPT #imm Breakpoint - BKPT

BL label Branch with Link - B, BL, BX, and BLX

BLX Rm Branch indirect with Link - B, BL, BX, and BLX

BX Rm Branch indirect - B, BL, BX, and BLX

CMN Rn, Rm Compare Negative N,Z,C,V CMP and CMN

CMP Rn, <Rm|#imm> Compare N,Z,C,V CMP and CMN

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Mnemonic Operands Brief description Flags See

Change Processor State,

CPSID i - CPS
Disable Interrupts

Change Processor State,

CPSIE i - CPS
Enable Interrupts

DMB - Data Memory Barrier - DMB

Data Synchronization
DSB - - DSB
Barrier

AND, ORR, EOR,

EORS {Rd,} Rn, Rm Exclusive OR N,Z
and BIC

Instruction Synchronization
ISB - - ISB
Barrier

Load Multiple registers,

LDM Rn{!}, reglist - LDM and STM
increment after

Load Register from PC- Memory access

LDR Rt, label -
relative address instructions

Rt, [Rn, Memory access

LDR Load Register with word -
<Rm|#imm>] instructions

Rt, [Rn, Memory access

LDRB Load Register with byte -
<Rm|#imm>] instructions

Rt, [Rn, Memory access

LDRH Load Register with halfword -
<Rm|#imm>] instructions

Rt, [Rn, Load Register with signed Memory access

LDRSB -
<Rm|#imm>] byte instructions

Rt, [Rn, Load Register with Memory access

LDRSH -
<Rm|#imm>] signed halfword instructions

{Rd,} Rn, ASR, LSL, LSR, and

LSLS Logical Shift Left N,Z,C
<Rs|#imm> ROR

{Rd,} Rn, ASR, LSL, LSR, and

LSRS Logical Shift Right N,Z,C
<Rs|#imm> ROR

MOV{S} Rd, Rm Move N,Z MOV and MVN

Move to general register

MRS Rd, spec_reg - MRS
from special register

17
Mnemonic Operands Brief description Flags See

Move to special register

MSR spec_reg, Rm N,Z,C,V MSR
from general register

MULS Rd, Rn, Rm Multiply, 32-bit result N,Z MULS

MVNS Rd, Rm Bitwise NOT N,Z MOV and MVN

NOP - No Operation - NOP

AND, ORR, EOR,

ORRS {Rd,} Rn, Rm Logical OR N,Z
and BIC

POP reglist Pop registers from stack - PUSH and POP

PUSH reglist Push registers onto stack - PUSH and POP

REV, REV16, and

REV Rd, Rm Byte-Reverse word -
REVSH

Byte-Reverse REV, REV16, and

REV16 Rd, Rm -
packed halfwords REVSH

Byte-Reverse REV, REV16, and

REVSH Rd, Rm -
signed halfword REVSH

ASR, LSL, LSR, and

RORS {Rd,} Rn, Rs Rotate Right N,Z,C
ROR

ADC, ADD, RSB,

RSBS {Rd,} Rn, #0 Reverse Subtract N,Z,C,V
SBC, and SUB

ADC, ADD, RSB,

SBCS {Rd,} Rn, Rm Subtract with Carry N,Z,C,V
SBC, and SUB

SEV - Send Event - SEV

Store Multiple registers,

STM Rn!, reglist - LDM and STM
increment after

Rt, [Rn, Memory access

STR Store Register as word -
<Rm|#imm>] instructions

Rt, [Rn, Memory access

STRB Store Register as byte -
<Rm|#imm>] instructions

Rt, [Rn, Memory access

STRH Store Register as halfword -
<Rm|#imm>] instructions

SUB{S} {Rd,} Rn, Subtract N,Z,C,V ADC, ADD, RSB,

18
Mnemonic Operands Brief description Flags See

<Rm|#imm> SBC, and SUB

SVC #imm Supervisor Call - SVC

SXTB Rd, Rm Sign extend byte - SXT and UXT

SXTH Rd, Rm Sign extend halfword - SXT and UXT

TST Rn, Rm Logical AND based test N,Z TST

UXTB Rd, Rm Zero extend a byte - SXT and UXT

UXTH Rd, Rm Zero extend a halfword - SXT and UXT

WFE - Wait For Event - WFE

WFI - Wait For Interrupt - WFI

19
2.8 ARM a n d T H U M B Instruction Set
Conditional Instruction

Shifted register Instruction

Arithmetic Instruction

Logical Instruction
Comparison

Single register load/store