Chris Auth and Adithya Shankar
Evolution of Transistors
Humble Beginnings to the Ubiquitous Present
I
n 2022, I B I S Wo r ld
reported that ~93%
of American house-
holds own at least one
computer. In fact, most
of us are very much plugged into ei-
ther our smartphones or computers
or both for a significant portion of
our lives [1]. Every one of these devic-
es is powered by billions of transis-
tors; the most powerful desktop CPU
today, Intel’s 13th-generation Raptor
Lake, is powered by ~12 billion tran-
sistors. Just to give some context into
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the enormity of this number, the first
transistor was developed by J. Bard-
een and W. Brattain in 1947, 75 years
ago (Figure 1). Intel’s cutting-edge Pen-
tium 4 microprocessor introduced at
the dawn of the 21st century in 2000
contained 42 million transistors.
Today’s microprocessors have ~300
times as many transistors as they
did, just about 20 years back. While
both the invention and commercial-
ization of transistors were responsi-
ble for the birth of Silicon Valley, the
explosive scaling and evolution of
transistor technology have both fu-
eled growth far beyond that of Silicon
Valley. Advances from medical innova-
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tions to highly ­complex simulations to
sophisticated artificial intelligence all
have been made possible in one way or
another by the evolution of transistor
technology in the last few decades.
The evolution of transistors can be
divided into three eras, namely the
pre-transistor era from 1900 to 1947,
the early transistor evolution from
1947 to 2000, and what we call the
golden age of transistors from 2000
onwards. While the pre-2000 era of
transistor invention and Dennard
scaling has been critical in the evolution
of transistors, a rich volume of litera-
ture is available on the invention and
evolution of transistors during this
1943-0582/23©2023IEEE
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 time [3], [4]. This article will focus
mainly on the post-2000 postconven-
tional scaling era, of which less has
been written but where tremendous
transistor innovation and creativity
radically redesigned the transistor
from head to toe.
Pre-Transistor Era—1900–1947
Based on Edison’s discovery that elec-
trons leaving a carbon filament are
attracted to a plate, the simplest vac-
uum tube was invented in 1904 by
John Ambrose Fleming [5], a signifi-
cant technological achievement at the
time, which then developed into the
triode vacuum tube in 1906. Electrons
flow unidirectionally from cathode to
anode in a vacuum tube, which can
be modulated by the voltage of the
grids. This invention made possible
the development of an array of devic-
es, including radio and long-distance
telephone signal transmission.
While vacuum tubes led to the ad-
vent of electronics, they were bulky,
had poor reliability, and consumed
significant power, making them un-
suitable for most operations. This
presented an opportunity for a new
device to take over.
Early Transistor Evolution—1947–2000
The concept of a field-effect tran-
sistor (FET) was first proposed by
physicist Julius Edgar back in 1926
[6]. However, it wasn’t until 1947
that the first transistor, a point-
contact transistor, was demonstrat-
ed at Bell Labs by two physicists,
John Bardeen and Walter Brattain
[7], [8]. This transistor used two
closely spaced gold contacts on a
plastic triangle held against a block
of germanium crystal. Current ap-
plied to one of the two gold con-
tacts modulated the current flowing
through the germanium and out
through the second contact. In fact,
a small change in current through
one contact caused a large change
through the other, thereby acting
as a n a mplifier. While point-con-
tact transistors were a significant
breakthrough and began the devel-
opment of solid-state devices, their
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In fact, Dennard scaling drove much of Moore’s
law through the 1980s and 1990s, successfully
scaling from ~10 µm to ~100 nm, two orders
of magnitude!
design had significant limitations.
This led to the invention of the bi-
polar junction transistor (BJT) by
Shockley two years later [9]. As the
name suggests, these transistors
have two junctions and, hence, can
exist in two forms: PNP and NPN.
The size of the “sandwiched” layer
determined the extent of the am-
plification of the current out of the
collector over the current applied to
the base. This planted the seed for
transistor scaling, which would be
taking the industry by storm over
the next several decades.
The earliest forms of BJTs were
commercialized in the form of mesa
transistors and sold by Fairchild
Semiconductors [10]. While the mesa
transistors had widespread applica-
tions and were commercially viable,
they had significant manufacturing
problems; for instance, the base-col-
lector junction, a very small region,
tended to gather defects, and with
existing manufacturing capabilities,
it was extremely difficult to clean
up, causing the malfunction of a sig-
nificant number of transistors. This
led to some of the most noteworthy
developments in solid-state devices
(a)
FIGURE 1: (a) The first transistor, 1947. (Source: Adapted from [2].) (b) The latest cutting-edge
transistor architecture, also called gate all around or RibbonFET.
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of the 20th century. Jean Hoerni in-
vented a planar process wherein it
was proposed that instead of remov-
ing silicon oxide from the entire sur-
face, it could be left in place over
junctions at the surface [11]. This
planar approach would protect these
junctions from contaminants that
mesa transistors were susceptible
to. This planar process led to a far
more profound invention in the form
of integrated circuits connecting
resistors, capacitors, and transis-
tors with interconnect components.
While both Robert Noyce and Jack
Kilby received patents on the inven-
tion of integrated circuits, each sepa-
rately [12], [13], only Jack Kilby was
recognized with a Nobel prize for it
in 2000 as Robert Noyce had passed
away by then.
Moder n integ rated circuits,
for the most part, are not based on
bipolar transistors; rather, they in-
corporate metal-oxide-semiconductor
FETs (MOSFETs). In 1959, Bell Labs
researchers Mohamed Atalla and
Dawon Kahng demonstrated the
first successful insulated-gate FETS
by thermally growing oxide on Si as
the gate oxide to reduce the trapped
(b)
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Moving to FinFETs or gate-all-around or
vertical transistors sounded like science
fiction, something for the future.
charge density [14]. Following this
work, RCA and Fairchild made exem-
plary progress in MOS stability work
during the 1960s, but the device was
significantly slower than bipolar
transistors and was seldom adopted
in circuits. Because of the ability to
scale MOSFETs much further than
BJTs and the ease of integrating them
into very large-scale integrated cir-
cuits (VLSIs), MOSFETs gradually took
their place, and the application of
BJTs dwindled.
In 1965, based on the pace of ear-
ly transistor development, Gordon
Moore predicted that the number
of transistors in an integrated cir-
cuit would continue to double every
year [Figure 2(a)]; he then updated
his prediction a decade later in 1975
to state that the number of transis-
tors in a microchip would double
every two years [Figure 2(b)]. The
latter came to be popularly known
as Moore’s law. Over time, this law
turned from an observation to a
milestone for the semiconductor in-
dustry to hit, making it the under-
current of the digital evolution of the
past half-century.
In the early 70s, Robert Dennard,
a researcher at IBM, published a se-
ries of seminal articles postulating
that as transistors grew smaller,
power density (power per unit area),
would stay constant [16]. Now known
as Dennard scaling, this theory rec-
ommended using a few rules for scal-
ing to achieve MOSFET circuits with
low standby power dissipation. This
scaling law drove much of transistor
scaling until the early 2000s through
dramatic gate length and oxide thick-
ness scaling. In fact, Dennard scaling
drove much of Moore’s law through
the 1980s and 1990s, successfully
scaling from ~10 µm to ~100 nm, two
orders of magnitude!
End of Conventional Scaling—
2000s and Beyond
With the dot-com boom cresting in
late 2000, transistor scaling got re-
ally exciting! The geometric dimen-
sional scaling of planar transistors
that worked so successfully in the
1980s and 1990s was starting to
show its faults. Gate oxide thickness
scaling was leading to higher and
higher gate oxide leakage through
tunneling. Source/drain (S/D) ex-
ternal resistance (Rext) was increas-
ing with the aggressive scaling of
the junction depths, leading to de-
graded drive currents. In addition,
supply voltage (Vcc) scaling didn’t
follow a constant electric field, lead-
ing to the degraded reliability of the
devices. Meanwhile, the higher dop-
ing in the channel was degrading
mobility in the device. The chorus
had started getting louder—“The
end is coming.”
While the end of Dennard scaling
was becoming obvious, the demand
for higher speed and higher density
transistors was greater than ever.
Three topics were dominating the
discussions at conferences, in indus-
try meeting rooms, and in academic
lecture halls.
The first was to change the gate
stack, moving to either high-gate
dielectric constant materials (Hi-k)
and/or metal gates. Higher gate ox-
ide capacitance would allow better
gate control, improved short-channel

16 M
1M it
Bipolar Logic Lim
Bipolar Arrays 1M
64 K MOS Logic
MOS Arrays
Components (Chip)
Components (Chip)

64 K
4K
4K

256
256

16 16

1 1
60 65 70 75 80 60 65 70 75 80 85
Year Year
(a) (b)

FIGURE 2: (a) The approximate component count for integrated circuits versus the year of introduction with the solid line representing
Moore’s law prediction of 1965. (b) Updated Moore’s law prediction presented in the 1975 IEEE International Electron Devices Meeting (IEDM)
by Gordon Moore. K: thousands; M: millions. (Source: Adapted from [15].)

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TECHNOLOGY.
 characteristics, and higher drive cur-
rent. In 2000, neither of these was
ready for high-volume manufactur-
ing despite years of research.
The second popular idea was
to change the channel, either with
silicon-on-insulator (SOI) substrates
or by moving to III-V channels or to
introduce biaxial strain. SOI had a
couple of options, either “partially
depleted,” which provided some im-
provement in short-channel effects
and reduced junction capacitance, or
“fully depleted,” which had ideal gate
control and greatly reduced short-
channel effects. While SOI has found
success in some markets and con-
tinues to be used today, substrate
costs and scalability concerns have
prevented large-scale adoption. Simi-
larly, while III-V and biaxial strain
both promised higher mobility chan-
nels, high substrate costs and defects
have limited their use.
The third idea was to leave pla-
nar devices and change the archi-
tecture. Research groups across
the globe were proposing radical
options such as FinFETs or gate-all-
around or vertical transistors or
vertical surrounding-gate transis-
tors. These were a scary proposition
for a generation of transistor device
experts who had, for decades, built
numerous successful technology
nodes with planar transistors. Mov-
ing to FinFETs or gate-all-around
or vertical transistors sounded like
science fiction, something for the
future. The industry stalwarts were
looking at each other, tacitly asking,
“What’s Next?”
Under the overcast skies of these
concerns, the development of the
90-nm technology generation com-
menced. Two observations were made
that ended up being key to the pro-
gression of the transistor for the next
two decades. The first was that, in
an effort to reduce Rext by increasing
the PMOS S/D doping, several groups
were experimenting with etching the
S/D regions and depositing highly B-
doped SiGe regions. The results were
jaw-dropping, with performance gains
much higher than would be expected
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Leaving the traditional silicon dioxide gate
dielectric with a polysilicon gate electrode
was a daunting undertaking.
with solely a reduction in Rext. Addi-
tionally, the gains depended on the
length of the S/D region. The second
observation was with the introduc-
tion of a silicon nitride capping layer
on the transistor to assist the contact
etch in stopping on the S/D region.
When the capping layer was added,
the performance of the transistors
was dependent on the thickness of
the capping layer, and interestingly,
it was better for NMOS and worse
for PMOS. Furthermore, if a raised
PMOS S/D was used, it alleviated the
impact of the capping layer on the
PMOS performance. Both of these ob-
servations suggested the presence of
uniaxial strain as a significant force
in the performance of the transistor:
a compressive strain on the PMOS
channel caused by the larger lattice
of the SiGe S/D and a tensile strain on
the NMOS channel caused by a ten-
sile silicon nitride capping layer [17].
Silicon is a piezoresistive material,
meaning that the mechanical lattice
strain of the channel atoms can be
exploited to improve transistor mo-
bility and drive current.
1,000
1V
100
Control
Ioff (nA/µm)
10
1
0.1
0.4 0.5
FIGURE 3: With uniaxial strain, the PMOS transistor showed 30% more Id-Sat at a given Ioff
or 50× lower leakage (Ioff) at a given Id-Sat. (Source: Adapted from [17].)
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The introduction of uniaxial strain
to enhance transistor performance
shook the semiconductor world and be-
came the industry standard for strain
implementation. At the 90-nm node,
the PMOS transistor showed a drive cur-
rent in the saturation regime (Id-Sat) gain
of 30% or 50× lower leakage current
(Ioff) (Figure 3). For the 65-nm node, Ge
concentrations were increased in the
SiGe S/Ds, and the SiGe S/D junction
was brought closer to the channel to
increase the drive enhancement fur-
ther. Meanwhile, on the NMOS side,
a thicker and more tensile capping
layer was introduced for the NMOS
transistor along with a novel stress
memorization technique. These came
close to doubling the drive current
enhancement on both the NMOS and
PMOS side relative to an unstrained
transistor. Other stressor techniques
were studied and employed across
the industry to improve transistor
performance—for instance, adding a
compressive nitride contact etch stop
layer for PMOS transistors [18].
The addition of mechanical stress-
ors for mobility enhancement has led
1.2 V
30% Strained
50×
0.6 0.7 0.8 0.9
Id-Sat (nA/µm)
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While the short-channel benefit of FinFETs was
appealing, the process challenges with FinFETs
deterred all but the most daring device engineers.
to a plethora of layout-dependent ef-
fects that impacted designers. This
has led to pre- to postlayout simula-
tion gaps resulting in design itera-
tions [19], [20]. The breakthrough of
adding uniaxial strain enabled addi-
tional scaling [21], [22] but the chal-
lenges of scaling remained at the
forefront of technical conversations.
Gate dielectric thickness scaling was
losing steam through 90- and 65-nm
technology nodes. The industry-stan-
dard silicon oxynitride (SiON) gate di-
electrics were simply running out of
atoms. (The industry migrated from
a pure silicon dioxide gate dielectric
to SiON when p+ polysilicon was in-
troduced in PMOS.) As the gate dielec-
tric thickness was scaled thinner and
thinner, the gate leakage was growing
exponentially. Meanwhile, depletion
in the polysilicon gate, due to the lim-
ited conductivity of polysilicon, was
also becoming a limiter for inversion
gate oxide thickness reduction. Sig-
nificant resources had been dedicat-
ed to the research of alternative high
permittivity or Hi-k dielectrics to use
for the gate dielectric. A Hi-k dielec-
tric enables the use of a thicker gate
100
10
Normalized Gate Leakage
~1,000×
1 In the development of a metal-gate
SiON/ Poly 65 nm
0.1
0.01
0.001
Hi-k + MG 45 nm
0.0001
PMOS
0.00001
–1.2 –1 –0.8 –0.6 –0.4 –0.2
VGS (V)
FIGURE 4: Hi-K + metal gate provided >25× reduction in leakage on NMOS and ~1,000×
reduction in leakage on PMOS. MG: metal gate; Poly: polysilicon; VGS: gate-to-source voltage.
(Source: Adapted from [23].)
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TECHNOLOGY.
dielectric to significantly suppress
tunneling leakage while maintaining
and/or improving gate coupling to
the channel. But the degradation of
mobility in the channel with the in-
troduction of the Hi-k dielectric was a
significant stumbling block.
Even strain engineering was see-
ing the impact of the shrinking gate
pitch. On the NMOS side, as the space
between the gates was shrinking, the
drive current benefit of the strained
tensile capping layer was reduced,
and similarly, on the PMOS side, the
benefit of compressive strain from
the embedded SiGe S/D was shrunk
with the scaling of the pitch.
In the midst of these challenges,
the definition of the 45-nm technol-
ogy node began. The first order of
business was to decide on the gate
stack. Leaving the traditional silicon
dioxide gate dielectric with a poly-
silicon gate electrode was a daunt-
ing undertaking. The introduction
of silicon dioxide enabled the MOS
transistor to become a reality and
was the foundation of the CMOS pro-
cess for >40 years, so there was a
large contingent that was looking for
SiON / Poly 65 nm
>25×
Hi-k + MG 45 nm
NMOS
0 0.2 0.4 0.6 0.8 1 1.2
options to continue to squeak a few
more generations without the large-
scale disruption of overhauling the
gate stack. The cupboard was bare,
though, with no promising alterna-
tives to replacing the gate stack. The
question that plagued the communi-
ty was what challenge to embark on
first—replace the gate dielectric with
a Hi-k material or replace the poly-
silicon gate with a highly conductive
metal gate.
Instead of choosing one or the
other, the industry decided to dive
into both at once. Significant prog-
ress had taken place in the under-
standing of Hi-k and metal-gate
stacks over the preceding five years
(Figure 4). The degraded mobil-
ity and reliability from Hi-k gate
dielectrics were resolved by com-
bining the Hi-k gate dielectric with
a metal gate. One major problem
was solved, but the introduction of
metal gates along with Hi-k intro-
duced several new issues. Two work-
function metals would be needed to
support both NMOS and PMOS de-
vices, and a high-conductivity bulk
metal material would be needed. The
new gate stack would also need to be
compatible with the uniaxial strain
performance enhancement that had
been so successful over the past two
generations. Looking at this list of
challenges, it would be easy to won-
der if it was worth leaving SiON +
polysilicon gates, but the gate leak-
age benefit was a compelling −25×
on NMOS and an astounding 1,000×
on PMOS. The verdict from the data
was loud and clear.
process flow, there were two front
runners. One was called gate first.
This was similar to the existing flow
with the SiON gate dielectric swapped
for a Hi-k gate dielectric stack of
SiO2+HfO2, and the polysilicon gate
was replaced with a metal-gate stack
that had two different work-function
metal layers. While this provided a
familiar look and feel to the tradi-
tional flow, it introduced constraints
on thermal processing for S/D epi-
taxy and dopant activation, and it
 also limited the choice of metals that the device reliability and transis- duced a complication for the NMOS
could be used. The second flow in- tor mobility. tensile capping layer. In this flow, the
troduced the Hi-k gate dielectric but With the change in gate stack wafer is polished back to the dummy
continued to use a polysilicon gate achieved, the question returned to gate to enable the replacement of the
that was a dummy layer. The poly- strain incorporation. Along with gate gate with metal. This polish would also
silicon dummy gate would remain pitch scaling, the gate-last flow intro- release the strain in the film, so a new
in place through S/D formation, and
after forming the interlayer dielectric
0 (ILD0), the dummy gate would be
removed. The work-function metals
would be deposited and patterned,
Dep. Hi-k and Patt. Met. 1 and Patt. Met. 2 and S/D Formation and
and a bulk metal would be deposited Met. 1 Dep. Met. 2 Etch Gates Contacts
and polished back.
This “Hi-k-first, gate-last” flow
had significant advantages, allowing
a high thermal budget for the S/D
epitaxy and dopant activation an- (a)
neals and a low thermal budget for
the work-function metals. This pro-
Dep. and Patt. S/D Formation Rem. Gate and Dep. Met. 2 + Fill
vided a broader set of options for the
Hi-k + Dummy and ILD Patt. Met. 1 and Polish
metal gate without the constraints on Gate Dep./Polish
the thermal budget. While this “Hi-
k-first, gate-last” approach was the
initial introduction of a Hi-k + metal-
gate process, a third approach, “gate
(b)
last,” has ultimately been the indus-
try-standard method of realizing this
change [22]. The “gate-last” approach Dep. and Patt. S/D Formation Rem. Gate, Dep. Met. 2 + Fill
Dummy Gate and ILD Dep. Hi-k and and Polish
is a similar flow to the “Hi-k-first,
Dep./Polish Patt. Met. 1
gate-last” flow with the exception
that the Hi-k film is also deposited
after the S/D and ILD0 processing
and dummy polysilicon (poly) remov-
al immediately prior to the metal- (c)
gate depositions (see Figure 5). With
the Hi-k deposited later in the flow, FIGURE 5: (a)–(c) Flows illustrating different metal-gate flow options. (a) Gate-first flow.
the subsequent thermal processing (b) Hi-K-first gate-last flow. (c) Gate-last flow. Dep.: deposit; Met.: metal; Patt.: pattern;
can be optimized to maximize both Rem.: removal.

GPa GPa
–0.04 0.22 –0.04 0.22
0.1 0.1
–0.02 –0.02
–0.02 –0.14 –0.02 –0.14
–0.26 –0.26
–0.38 –0.38
0 –0.5 0 –0.5
–0.62 –0.62
0.02 –0.74 0.02 –0.74
–0.86 –0.86
–0.98 –0.98
0.04 –1.1 0.04 –1.1
–1.22 –1.22
–1.34 –1.34
0.06 –1.46 0.06 –1.46
–1.58 –1.58
0.08 –1.7 0.08 –1.7
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
(a) (b)

FIGURE 6: (a) and (b) Stress contours in the PMOS transistor before and after the removal of the polysilicon dummy gate. Stress in the channel
is shown to increase 50% from ~0.8 GPa to >1.2 GPa. (a) Before gate removal. (b) After gate removal. (Source: Adapted from [24].)

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 method of introducing strain was need-
ed. The most significant component in
gate pitch was the contact, along with
the gate itself. This presented an op-
portunity to use a compressive gate
fill material and a tensile contact mate-
rial to introduce tensile strain into the
channel. Since the PMOS had raised
S/Ds and a thicker work-function metal,
it was possible to protect it from the
tensile strain.
To maintain the benefit of PMOS
strain with the scaled gate pitch, two
methods were employed—one was
to increase the percentage of Ge in
the SiGe film, and the second was to
reduce the distance from the SiGe to
the gate edge. Both these methods
were used in the 65-nm node and
were further extended to the 45-nm
node [21]. But there was one more
piece of magic. By removing the
dummy gate in the gate-last flow, the
stress in the channel was enhanced
by 50% (Figure 6)! This resulted in
marked increases in drive current
gain of more than 50%. This was a
new and unexpected benefit of the
metal gate’s last flow.
Transistor
Scaling
Introduction of
Uniaxial Strain
End of
Conventional
Dennard
Scaling Era 90 nm
130 nm
FIGURE 7: The evolution of transistor technology since the 130-nm node, as we enter the postconventional scaling era or the “golden” era of
transistor evolution.
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Introducing the Hi-k/metal gate
marked a significant increase in the
number of elements incorporated
into the building of a modern silicon-
based chip. In the 1980s, there were
on the order of 10 elements. This in-
creased modestly to ~15 elements in
the 1990s, but this exploded to >50
elements used through the manufac-
turing process in the 2000s (Figure 7).
This rapid increase provided suffi-
cient options that, along with the in-
troduction of immersion lithography,
enabled continued ­ advancement to
the 32-nm node. At this point, a new
problem started surfacing. While the
gate pitch continued to scale at ~0.7×
per technology node, the gate length
scaling had significantly slowed
down after the 65-nm node. Where
the gate used to occupy 15% of the
gate pitch at the start of the century,
it now occupied more than 30%.
The limiter for gate length scaling
was short-channel effects; moreover,
ionized impurity scattering was lim-
iting the channel doping levels that
had earlier been increasing as per
Dennard scaling. The short-channel
10 nm
7 nm
4 nm
14 nm
22 nm
32 nm
45 nm
65 nm Introduction and Scaling of
Tri-Gate or FinFET Transistors
Hi-k and Metal Gate,
Both Introduced in
Tandem
2000 – Early 2020s
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TECHNOLOGY.
effect is described in detail elsewhere
but is simply the need to increase the
threshold voltage (Vt) of the transistor
as the gate length is scaled to meet
the off-state leakage current require-
ments. To increase Vt, the channel
doping is increased, leading to mobil-
ity degradation and thus degrading
the drive current. The need was clear;
something was needed to improve
short-channel effects, enabling a low
off-state leakage current with low Vt
while maintaining a low channel dop-
ing for high mobility.
The ideal solution would be a very
thin channel where, with very low
channel doping, the gate work func-
tion would fully deplete the channel.
This would both maximize the chan-
nel control for reduced short-channel
effects, thereby reducing the off-state
leakage, and increase the mobility for
high performance. While the concept
of the solution was clear, the means
to that end were not. While there were
several options, fully depleted SOI was
the most obvious. Surrounding-gate
or gate-all-around structures had also
been around for more than a decade.
Shift to Gate-All-Around or
RibbonFET architecture as
we enter the Angstrom era;
Provides complete gate
control.
Time
 The most promising, though, was the
tri-gate or FinFET structure. This was
a brand-new architecture that deviat-
ed from decades of planar processing.
It would require a very narrow sliver
or “fin” of silicon to be raised from the
substrate with the gate laid over it,
providing gate control on both sides
of the fin. This would fully deplete the
fin, enabling near-ideal room-temper-
ature subthreshold slopes of 60 mV
per decade of current.
While the short-channel benefit of
FinFETs was appealing, the process
challenges with FinFETs deterred all
but the most daring device engineers.
First, FinFETs introduced a nonplanar
surface accompanied by high aspect
ratios for all subsequent process-
ing. Creating the fins themselves re-
quired innovation; for instance, the
width of the fins needed to be sub-
wits of lithography capabilities in
the 2010 timeframe. The narrow fins,
or thin channel, also introduced high
Rext to the S/D that had to be over-
come. On top of these challenges,
the integration of Hi-k/metal-gate
and strain features with FinFETs,
which were so meticulously incorpo-
rated into the planar process, added
to the discomfort of proceeding
with FinFETs.
Given a problem statement, engi-
neers are an amazing group. They took
The baton of this evolution was passed through
multiple generations, each coming up with
innovations that made further miniaturization
and higher performance possible.
on each of these problems and defined
solutions. The narrow fins were pat-
terned with a self-aligned pitch divi-
sion process that used a deposited
spacer to define the fin width. The Rext
limitations were to be overcome with
the same raised S/D processing that
was used to introduce strain. Now it
was added on the NMOS side as well.
The strain on the PMOS was extended
by increasing the peak Ge concentra-
tion further beyond 50%, and SiGe
now underlapped the gate to form the
tip region. The result was a process
that provided a 37% improvement
in delay or a 50% reduction in active
power. Outstanding short-channel and
drain-induced barrier-lowering (DIBL)
characteristics also enabled a 100-mV
reduction in Vt [26] (Figure 8).
One of the key benefits of FinFETs
was its scalability. As the fin pitch is
scaled, the drive/fin can be maintained
since the transistor “width” is now in
the vertical direction. This provided
dual benefits of drive per top-down
width increase and the dead space
capacitance reduction, thereby con-
tinuing the trajectory of performance
gain while scaling density. This made
FinFETs the key transistor structure of
multiple subsequent technology nodes.
This brings us to today, where the
industry is undergoing another seis-
mic shift in transistor architecture.
Gate-all-around, or RibbonFET, tran-
sistors (see Figure 7) are in relentless
development [27], [28]. Industry-wide
adoption is expected in the next one
to two years. This represents the ul-
timate transistor architecture with
complete gate control, at least until
the next innovation comes along to
shake up the industry again.
Future
The astounding digitization of our
world in the 21st century has brought
with it an insatiable demand for high-
performance and low-power transis-
tors in the existing market segments;
moreover, the industry is seeing rising
demand from new segments, includ-
ing super and quantum computing.
While the chorus that “Moore’s law has
reached its end” is ever louder, the

2 0.5
NMOS 32 nm Vds = 0.05 V
0.4
1.8
0.3
37%
Transistor Gate Delay

1.6 Faster 0.2

32-nm 0.1
1.4 Planar 22 nm
Vt (V)

0
1.2 –0.1
–0.2 V 22 nm
1 –0.2
22-nm –0.3
0.8 Tri-Gate –0.4
PMOS 32 nm
0.6 –0.5
0.5 0.6 0.7 0.8 0.9 1 1.1 25 30 35 40
Operating Voltage (V) Lgate (nm)
(a) (b)

FIGURE 8: (a) A 22-nm tri-gate (FinFET) process provided a 37% improvement in delay and as a result, a 50% reduction in active power for
a given delay. (b) Linear threshold voltage versus gate length for NMOS and PMOS transistors show that FinFETs also enabled a 100-mV
­reduction in Vt owing to outstanding short-channel and drain-induced barrier-lowering (DIBL) benefits. Vds: drain-to-source voltage.
(Source: Adapted from [26].)

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 progress and promise of Moore’s law
will continue through transistor ar-
chitecture evolution—3D transistors
in the near future—and new mate-
rial discoveries—such as 2D mate-
rials. The evolution of 3D transistors
will continue through the next de-
cade. The baton of this evolution was
passed through multiple generations,
each coming up with innovations that
made further miniaturization and
higher performance possible. As we
write this review, that baton is on to
the next generation to innovate and
deliver to the world even higher per-
formance transistors than the world
has ever seen.
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About the Authors
Chris Auth (chris.auth@intel.com) is
the vice president of Technology De-
velopment and director of advanced
transistor development at Intel Cor-
poration, Hillsboro, OR 97124 USA.
He leads the Advanced Technology
Development and Analytics Group. In
this role, he is responsible for lead-
ing the development of Intel’s Intel 7
high-performance CMOS logic transis-
tor and interconnect processes along
with the functional groups driving
the development of next-genera-
tion technologies. He joined Intel in
1997 and led the team responsible
for introducing the industry’s first
use of strained silicon for transis-
tor enhancement into the 90-nm and
65-nm CMOS flows. From 2005 to
2008, he led the process develop-
ment and introduction of the indus-
try-first high-k/metal-gate process
for the 45-nm CMOS flow. He led the
process development and introduc-
tion of the industry-first tri-gate pro-
cess into the 22-nm CMOS flow. He
holds 17 patents in semiconductor
devices and manufacturing and has
authored/coauthored 30 articles on
semiconductor process development.
He and his colleagues have also been
honored twice with a SEMI Award for
North America, which recognized
that the techniques pioneered by the
team were widely adopted across the
semiconductor industry. He received
his bachelor’s degree in electrical
engineering from the University of
Washington and earned his master’s
and doctoral degrees in electrical en-
gineering from Stanford University. In
2015, he was named a Fellow of IEEE
for his contributions to strained sili-
con transistor technology.
Adithya Shankar (adithya.shankar@
intel.com) is a technical assistant in
technology development supporting
the Advanced Technology Develop-
ment and Analytics Group, Intel Cor-
poration, Hillsboro, OR 97124 USA. In
this role, he supports the functional
groups driving the development of
next-generation technologies with de-
velopment, operations, logistics, and
internal/external communications.
Previously, he has been an etch pro-
cess development engineer develop-
ing leading-edge plasma etches for
10-nm, Intel 7 and Intel 4 intercon-
nects. He received his bachelor’s de-
gree in chemical technology from the
Institute of Chemical Technology, his
M.S. degree in chemical engineering
from Northwestern University, and his
M.B.A. degree from the University of
Chicago Booth School of Business.