DE Question Bank

Branch: ECS Class: SE ECS[ATKT]

A.Y=2023-2024

Q) [V.Imp-Similar Problems]

Convert the decimal number (123)10 to their octal, hexadecimal, BCD and gray
code equivalent.

Q) Convert the decimal number (175.23)10 to their octal, hexadecimal, BCD and
gray code equivalent.

[Same problem maybe asked for other number systems and their conversion]

Q) Minimize the function f1(P,Q,R,S)=∑m(2,5,6,9,12,13,15)+d(7,8) and

implement using minimum number of only NAND gates.

[V.Imp-similar Problems].

Q) Design 2 bit comparator and implement using logic gates. .[V.Imp]

Q) Define propagation delay, noise margin power dissipation, fan in and fan
out. [V.Imp]

Q) Explain the characteristics of logic families. [V.Imp]

Q) Design and implement half adder or full adder circuit or half or full
subtractor. [V.Imp]

Q) Implement and explain the 4 bit BCD adder using the IC 7483. [V.Imp]

Q) Differentiate between mealy and Moore machine. [V.Imp]

Or

Problems on mealy and Moore machine may be asked

Q) Explain the working of two neither input CMOS NOR gate with neat
diagram. Mealy and Moore machine. [V.Imp]

Q) Implement CMOS as a NAND and NOR Gate. [V.Imp]

Q) Explain standard TTL circuit operation with appropriate circuit diagram.

[V.Imp]

Q) Write short note on Hamming Code. [V.Imp]

Or

Q) A 7 bit hamming code is received as 1011011.Assume even parity and state

whether received code is correct or wrong,if wrong then locate the bit error.

[V.Imp-Similar Problems]

Q) Draw the circuit diagram of TTL NAND gate with totem pole output and
explain it’s working with the truth table. [V.Imp]

Q) Design and implement the following expressions using a single 8:1

Multiplexer. [V.Imp]

F(A,B,C,D)=∑m(0,1,3,5,7,10,11,13,14,15)

Or

F(A,B,C,D)=∑m(0,1,3,4,8,9,15)

Q) Write a VHDL code for 8:1 multiplexer using data flow modelling. [V.Imp]

Q) Explain, what is master slave JK flip Flop and state its advantages. [V.Imp]

Q) Design and implement D FF(flip Flop) using T FF and JK FF using D FF.

[V.Imp]

Q) Design and implement D FF(flip Flop) using JK FF and T FF using SR FF.

[V.Imp]

Q) Reduce the following state table using the partition method of state
reduction. [VVV.Imp]
Q) Implement the following function using PLA. [VVV.Imp]

F1=∑m(0,3,4,7 and F2=)=∑m(01,2,5,7))

OR

Implement the following function using PLA.

F1=∑m(0,1,3,4) and F2=)=∑m(1,2,3,4,5)

Q) Write a VHDL program/code and explain the design procedure of 8 bit

counter. [V.Imp]

Q) Explain the Structural VHDL description of 2 to 4 decoder in detail. [V.Imp]

Q) Write the Verilog code for T- Flip Flop.

Q) Write a Verilog HDL code for implementing the half subtractor. [V.Imp]

Q) Write a code in Verilog HDL to implement the 4-bit up-down counter.

[V.Imp]

Q) Explain the working of 3 bit asynchronous counter with proper tuning

diagram. [V.Imp]

Q) Draw Johnson counter circuit, and neat waveforms, specify the application
of the same. [V.Imp]

Q) Implement and explain synchronous counter MSI counter using IC 74163.

[V.Imp]
Q) Write a VHDL program/code and explain the design procedure of 8 bit
counter. [V.Imp]

Q) Design mod-6 counter by using MOD-8 counter. [V.Imp]

Q) Explain the FPGA architecture with neat diagrams. [V.Imp]

ALL THE BEST