Lecture-2

ALU-2
Multiplication
CSE-2823
Computer Architecture

Dr. Md. Waliur Rahman Miah

Associate Professor, CSE, DUET
1
 Today’s Topic

Arithmetic and logical processing unit

(ALU)
Multiplication

Ref:
Ch-9 Stallings
Ch-3 Hennessy-Petterson
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET 2
 Multiplication
• Complex
• Work out partial product for each digit
• Take care with place value (column)
• Add partial products

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Multiplication Example
1011  Multiplicand (11; decimal)
x 1101  Multiplier (13; decimal)
1011  Partial products
0000x Note: if multiplier bit is 1 then
1011xx copy multiplicand (place value)
1011xxx otherwise zero
10001111  Product (143 dec)

Note:
1. Need double length for storing result
2. Add and shift to achieve multiplication
Dr. Md. Waliur Rahman Miah Dept of CSE, DUET
 Unsigned Binary Multiplication

FIGURE 3.3: First version of the multiplication hardware. (Source: Patterson- Pg-184)
 Flowchart for
Unsigned Binary
Multiplication

FIGURE 3.4 : The first multiplication algorithm

Execution of Example
 Refined hardware of multiplication

Multiplier

FIGURE 3.5 : Refined version of the multiplication hardware.

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Multiplying Negative Numbers
• This does not work!
• Solution 1
– Convert to positive if required
– Multiply as above
– If signs were different, negate answer
• Solution 2
– Booth’s algorithm

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Booth’s
Algorithm

Figure 9.12 Booth’s

Algorithm for Twos Result = A Q
Complement Multiplication
[Stallings pg-321]
Example of Booth’s Algorithm-1
M (Multiplicand) X Q(Multiplier) = AQ (Product)
(+ 7 ) X ( + 3 ) = ( + 21 )

Result = ( + 21 )
 Example of Booth’s Algorithm-2
Multiplicand = M = +7 = 0111
Multiplier = Q = -3 = 1101
A Q Q-1 M Comments
0000 1101 0 0111 Initial Values
1001 1101 0 0111 Q0Q-1 = 10; A <= A-M
1100 1110 1 0111 Right-Shift AQQ-1 preserve sign bit
0011 1110 1 0111 Q0Q-1 = 01; A <= A+M
0001 1111 0 0111 Right-Shift AQQ-1 preserve sign bit
1010 1111 0 0111 Q0Q-1 = 10; A <= A-M
1101 0111 1 0111 Right-Shift AQQ-1 preserve sign bit
1101 0111 1 0111 Q0Q-1 = 11; A <= A (no change)
1110 1011 1 0111 Right-Shift AQQ-1 preserve sign bit
Result = ( - 21 )
Product = AQ = 11101011 = -21
 Faster Multiplication

FIGURE 3.7 Fast multiplication hardware. Rather than use a single 32-bit adder 31 times,
this hardware “unrolls the loop” to use 31 adders and then organizes them to minimize
delay.

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET

 Reference
[1] Patterson, D. A., & Hennessy, J. L. (2014). Computer
organization and design: The hardware/software
interface (5th ed.). Burlington, MA: Morgan Kaufmann
Publishers.
[2] William Stallings, (2010), Computer Organization and
Architecture,(8th Ed), Prentice Hall Upper Saddle River, NJ
07458.
[3] Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig
Manjikian, (2012), Computer Organization and
Embedded Systems (6th Ed), McGraw-Hill, New York, NY
10020.
[4] M. Morris Mano (1993), Computer System Architecture
(3rd Ed), Prentice-Hall Inc. USA. (Ch-10-Comp Arith)

Dr. Md. Waliur Rahman Miah Dept of CSE, DUET 14