Timing Diagram of 8085

Instructions
 Timing Diagram
• Timing Diagram is a graphical representation.

• Timing diagram of 8085 instructions represents the

execution time taken by each instruction in a
graphical format.

• The execution time is represented in T-states.

 Machine Cycle, T State and Instruction
Cycle
• T-State:
– The processor takes a definite time to execute the machine
cycles. The time taken by the processor to execute a machine
cycle is expressed in T-states.
– A portion of an operation carried out in one system clock period
is called as T-state.
– One T-state is equal to the time period of the internal clock
signal of the processor. The T-state starts at the falling edge of a
clock
• Machine Cycles Of 8085 Microprocessor

– The time required to access the memory or input/output devices is called machine

cycle.

• Machine cycles of 8085:

– The 8085 microprocessor has 5 basic machine cycles. They are

– Opcode fetch cycle (4T)

– Memory read cycle (3 T)

– Memory write cycle (3 T)

– I/O read cycle (3 T)

– I/O write cycle (3 T)

• Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when

the 8085 processor executes an instruction, it will execute some of the machine cycles in

a specific order.
 Instruction Cycle

The time required to execute an instruction is called

instruction cycle.
Different Operations of 8085 With Respect to the Status of Various Signals
µP-8085 consists of two status output pins. So, µP will output 2 bit number on S1S0 status pins
to inform external devices about current status of µP or the machine cycle which µP is executing.
The output of S1S0 pins and the status of µP is given in the table below:

Status Pins Status

S1 S0
0 0 Halt
0 1 Write M/C
1 0 Read M/C
1 1 Opcode Fetch

•When S1S0 = 00, ie µP is in halt state, it will not use external bus, so any other device can use
external bus if required.
•For reading and writing operation, µP will generate RD and WR’ signals in the second clock cycle
whereas S1S0 signals are generated in the first clock cycle of machine cycle.
•So, S1S0 signals can be used as reading and writing signals in first clock cycle if required.
•S1S0 signals can be used to distinguish whether µP is reading data from memory (S1S0=10) or
opcode from memory (S1S0=11)
 Opcode Fetch Machine Cycle Of 8085

• Each instruction of the processor has one byte opcode.

• The opcodes are stored in memory. So, the processor executes the
opcode fetch machine cycle to fetch the opcode from memory.

• Hence, every instruction starts with opcode fetch machine cycle.

• The time taken by the processor to execute the opcode fetch cycle is
4T.

• In this time, the first, 3 T-states are used for fetching the opcode
from memory and the remaining T-states are used for internal
operations by the processor.
• The total time required by µP to transfer 8-bit instruction opcode from
selected memory location to instruction register and to decode this opcode is
called OFMC
– T1 Clock Cycle: µP will transfer 16-bit memory location address from PC to
address pins A15 –A8 and AD7-AD0. To latch 8 LSBs of address AD7 to AD0 pins
µP gives logic 1 pulse on ALE. At the same time µP gives IO/M’=0 and the status
output S1S0=11. The 16 bit memory location address with IO/M’=0 is used to select
1 memory location.

– T2 Clock Cycle: µP will remove 8 LSBs of address from address pins AD7 to AD0
pins. So, AD7 to AD0 pins becomes floating and then µP gives RD’=0. So 8 bit
instruction opcode is transferred from selected memory location to µP data pins
AD7-AD0.

– T3 Clock Cycle: µP will transfer 8 bit instruction code from data pins AD7-AD0 to
IR.

– T4 Clock Cycle: The 8 bit instruction opcode is transferred from instruction

register to instruction decoder, decoded and corresponding instruction is executed.
Operand Fetch /Memory Read/IO Read
Machine Cycle or Bus Cycle
• The memory read machine cycle is executed by
the processor to read a data byte from memory.
The processor takes 3T states to execute this
cycle.
• The instructions which have more than one byte
word size will use the machine cycle after the
opcode fetch machine cycle.
• The total time required by µP to transfer operand (2nd and
3rd byte of instruction code) from one memory location to
internal 8 bit registers of µP is called as OPRFMC. (3
Clock Cycles).
• The total time required by µP to transfer 8 bit data from
one memory location to internal 8 bit registers of µP is
called as MRMC. (3 Clock Cycles).
• The total time required by µP to transfer operand from
one IO port to accumulator of µP is called as IORMC. (3
Clock Cycles).
• T1 Clock Cycle: µP will transfer 16 bit memory location address or 8 bit IO port
address on address pins A15 to A8 and AD& to AD0. To latch 8 LSBs of address of
AD& to ADO pins, µP gives ALE=1. To indicate that the address on address bus is
of IO port/memory, µP gives IO/M’=1/0 respectively. At the same time, µP will
output status S1S0=10. 16 bit memory location address with IO/M’=0 is used to
select one memory location. Similarly, 8 bit IO port address with IO/M’ = 1 is used
to select one IO.

• T2 Clock cycle: µP will remove 8 LSBs of Address from AD7 to AD0 pins and
then µP gives RD’=0, so 8 bit data is transferred from selected memory location/ IO
port to µP data pins AD7 to AD0.

• T3 Clock Cycle: µP will transfer 8 bit data from data pins AD7 to AD0 to
corresponding internal 8 bit register
Memory Write/ IO Write Machine Cycle
Of 8085
• The memory write machine cycle is executed by
the processor to write a data byte in memory. The
processor takes 3T states to execute this cycle.

• The instructions which have more than one byte

word size will use the machine cycle after the
opcode fetch machine cycle.
• The total time required by µP to store 8 bit data into one selected memory
location is called as MWMC. (3 Clock Cycles).

• The total time required by µP to store 8 bit data of accumulator into one
selected IO port is called as IOWMC. (3 Clock Cycles).
– T1 Clock Cycle: µP will transfer 16 bit memory location address or 8 bit IO port address on address
pins A15 to A8 and AD7 to AD0. To latch 8 LSBs of address of AD7 to ADO pins, µP gives ALE=1.
To indicate that the address on address bus is of IO port/memory, µP gives IO/M’=1/0 respectively. At
the same time, µP will output status S1S0=10. 16 bit memory location address with IO/M’=0 is used
to select one memory location. Similarly, 8 bit IO port address with IO/M’ = 1 is used to select one
IO.

– T2 Clock Cycle: µP will remove 8 LSBs of address from AD7 to AD0 pins at the same time µP will
transfer 8 bit data from internal register to AD7 to AD0 pins. Then µP gives writing signal WR’=0.
So, writing operation starts.

– T3 Clock Cycle: The 8 bit data transferred by µP will get stored into selected memory location/ IO
poet i.e data writing operation is completed.
I/O Read Machine Cycle Of 8085
• The I/O Read machine cycle is executed by the
processor to Read a data byte from the I/O port
or from a peripheral, which is I/O, mapped in
the system.
• The processor takes 3T states to execute this
machine cycle.
I/O Write Machine Cycle Of 8085
• The I/O write machine cycle is executed by the
processor to write a data byte in the I/O port or
to a peripheral, which is I/O, mapped in the
system.
• The processor takes 3T states to execute this
machine cycle.
 Notes for Timing Diagram
• OFMC = 4 c/c and rest of the m/c = 3 c/c

• A15 to A8 : It will change in T1 and T4

• AD7 to AD0:

– Read Cycle: Address (T1)- Float- data(before T3)-float.

– Write Cycle: Address (T1)-data (T2T3)

• ALE : Logic 1 pulse in T1

• IO/M’ and S1S0: It will change only in T1

• RD’: In read cycle RD’=0 from T2 (20%) to centre of T3

• WR’: In write cycle WR’ = 0 from T2 (20%) to centre of T3

• Ready : For wait state, READY=0 during T2.

Timing Diagram of 8085 Instructions

EXAMPLES
 Timing Diagram For MVI B, 43H
• Fetching the opcode 06H from the memory 2000H. (Opcode
fetch machine cycle)

• Read (move) the data 43H from memory 2001H. (memory

read).
 Timing Diagram For STA 526AH
• STA means Store Accumulator -The contents of the accumulator are stored in the specified address (526A).

• The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see fig). – OF
machine cycle.

• Then the lower order memory address is read(6A). – Memory Read Machine Cycle

• Read the higher order memory address (52) – Memory Read Machine Cycle.

• The combinations of both the addresses are considered and the content from accumulator is written in
526A. – Memory Write Machine Cycle

• Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from
accumulator is now stored in 526A.