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  • BCD双向计数逻辑自动生成

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    陈陈兆卿
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    The document describes a 4-bit synchronous sequential circuit with one input signal (Mode) and outputs the next state. It provides the current state, input, next state and the equivalent minimum logic expressions for the circuit in terms of the S3, S2, S1, S0 bits and Mode input. The final summary logic expression for the next state bits N3, N2, N1, N0 is provided in terms of the current state bits and Mode.

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    The document describes a 4-bit synchronous sequential circuit with one input signal (Mode) and outputs the next state. It provides the current state, input, next state and the equivalent minimum logic expressions for the circuit in terms of the S3, S2, S1, S0 bits and Mode input. The final summary logic expression for the next state bits N3, N2, N1, N0 is provided in terms of the current state bits and Mode.

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    © All Rights Reserved
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    3 views5 pages

    BCD双向计数逻辑自动生成

    Uploaded by

    陈陈兆卿
    The document describes a 4-bit synchronous sequential circuit with one input signal (Mode) and outputs the next state. It provides the current state, input, next state and the equivalent minimum logic expressions for the circuit in terms of the S3, S2, S1, S0 bits and Mode input. The final summary logic expression for the next state bits N3, N2, N1, N0 is provided in terms of the current state bits and Mode.

    Copyright:

    © All Rights Reserved
    Download as XLSX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as xlsx, pdf, or txt
    of 5

    当前状态(现态) 输入信号 下一状态（次态）

    现态 次态
    S3 S2 S1 S0 Mode N3 N2 N1
    10进制 10进制
    0 0 0 0 0 0 1 0 0 0
    0 0 0 1 1 0 2 0 0 1
    0 0 1 0 2 0 3 0 0 1
    0 0 1 1 3 0 4 0 1 0
    0 1 0 0 4 0 5 0 1 0
    0 1 0 1 5 0 6 0 1 1
    0 1 1 0 6 0 7 0 1 1
    0 1 1 1 7 0 8 1 0 0
    1 0 0 0 8 0 9 1 0 0
    1 0 0 1 9 0 0 0 0 0
    0 0 0 0 0 1 9 1 0 0
    0 0 0 1 1 1 0 0 0 0
    0 0 1 0 2 1 1 0 0 0
    0 0 1 1 3 1 2 0 0 1
    0 1 0 0 4 1 3 0 0 1
    0 1 0 1 5 1 4 0 1 0
    0 1 1 0 6 1 5 0 1 0
    0 1 1 1 7 1 6 0 1 1
    1 0 0 0 8 1 7 0 1 1
    1 0 0 1 9 1 8 1 0 0

    只填0或1，无关项不填
    态（次态）

    N0

    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0
    1
    0 1
    S3 S2 S1 S0 Mode 0 0 0 0 0 0 最小项表达式 N3 N2
    ~S3& ~S2& ~S1& ~S0& ~Mode& ~S3&~S2&~S1&~S0&~Mode
    ~S3& ~S2& ~S1& S0& ~Mode& ~S3&~S2&~S1&S0&~Mode
    ~S3& ~S2& S1& ~S0& ~Mode& ~S3&~S2&S1&~S0&~Mode
    ~S3& ~S2& S1& S0& ~Mode& ~S3&~S2&S1&S0&~Mode ~S3&~S2&S1&S0&~Mode+

    ~S3& S2& ~S1& ~S0& ~Mode& ~S3&S2&~S1&~S0&~Mode ~S3&S2&~S1&~S0&~Mode+

    ~S3& S2& ~S1& S0& ~Mode& ~S3&S2&~S1&S0&~Mode ~S3&S2&~S1&S0&~Mode+

    ~S3& S2& S1& ~S0& ~Mode& ~S3&S2&S1&~S0&~Mode ~S3&S2&S1&~S0&~Mode+

    ~S3& S2& S1& S0& ~Mode& ~S3&S2&S1&S0&~Mode ~S3&S2&S1&S0&~Mode+


    S3& ~S2& ~S1& ~S0& ~Mode& S3&~S2&~S1&~S0&~Mode S3&~S2&~S1&~S0&~Mode+

    S3& ~S2& ~S1& S0& ~Mode& S3&~S2&~S1&S0&~Mode


    ~S3& ~S2& ~S1& ~S0& Mode& ~S3&~S2&~S1&~S0&Mode ~S3&~S2&~S1&~S0&Mode+

    ~S3& ~S2& ~S1& S0& Mode& ~S3&~S2&~S1&S0&Mode


    ~S3& ~S2& S1& ~S0& Mode& ~S3&~S2&S1&~S0&Mode
    ~S3& ~S2& S1& S0& Mode& ~S3&~S2&S1&S0&Mode
    ~S3& S2& ~S1& ~S0& Mode& ~S3&S2&~S1&~S0&Mode
    ~S3& S2& ~S1& S0& Mode& ~S3&S2&~S1&S0&Mode ~S3&S2&~S1&S0&Mode+

    ~S3& S2& S1& ~S0& Mode& ~S3&S2&S1&~S0&Mode ~S3&S2&S1&~S0&Mode+

    ~S3& S2& S1& S0& Mode& ~S3&S2&S1&S0&Mode ~S3&S2&S1&S0&Mode+

    S3& ~S2& ~S1& ~S0& Mode& S3&~S2&~S1&~S0&Mode S3&~S2&~S1&~S0&Mode+

    S3& ~S2& ~S1& S0& Mode& S3&~S2&~S1&S0&Mode S3&~S2&~S1&S0&Mode+

    逻辑表达式->>> ~S3&S2&S1&S0&~Mode+S3&~S2&~S1&~S0&~Mode+~S3&~S2&~S1&~S0&Mode+S3&~S2&~S1&S0&Mode ~S3&~S2&S1&S0&~Mode+~S3&S2&~S1&~S0&~Mode+~S3&S2&~S1&S0&~Mode+~S3&S2&S1&~S0&~Mode+~S3&S2&~S1&S0&Mode+~S3&S2&S1&~S0&Mode+~S3&S2&S1&S0&Mode+S3&~S2&~S1&~S0&Mode

    此表一般不需要修改，如需修改，在审阅中撤销工作表保护
    默认4位状态，如只需3位，将s3列的公式删除，注意不是删除列，只是将公式删掉
    这里是最终的表达式，
    N1 N0
    ~S3&~S2&~S1&~S0&~Mode+

    ~S3&~S2&~S1&S0&~Mode+

    ~S3&~S2&S1&~S0&~Mode+ ~S3&~S2&S1&~S0&~Mode+

    ~S3&S2&~S1&~S0&~Mode+

    ~S3&S2&~S1&S0&~Mode+

    ~S3&S2&S1&~S0&~Mode+ ~S3&S2&S1&~S0&~Mode+

    S3&~S2&~S1&~S0&~Mode+

    ~S3&~S2&~S1&~S0&Mode+

    ~S3&~S2&S1&~S0&Mode+

    ~S3&~S2&S1&S0&Mode+

    ~S3&S2&~S1&~S0&Mode+ ~S3&S2&~S1&~S0&Mode+

    ~S3&S2&S1&~S0&Mode+

    ~S3&S2&S1&S0&Mode+

    S3&~S2&~S1&~S0&Mode+ S3&~S2&~S1&~S0&Mode+

    ~S3&~S2&~S1&S0&~Mode+~S3&~S2&S1&~S0&~Mode+~S3&S2&~S1&S0&~Mode+~S3&S2&S1&~S0&~Mode+~S3&~S2&S1&S0&Mode+~S3&S2&~S1&~S0&Mode+~S3&S2&S1&S0&Mode+S3&~S2&~S1&~S0&Mode ~S3&~S2&~S1&~S0&~Mode+~S3&~S2&S1&~S0&~Mode+~S3&S2&~S1&~S0&~Mode+~S3&S2&S1&~S0&~Mode+S3&~S2&~S1&~S0&~Mode+~S3&~S2&~S1&~S0&Mode+~S3&~S2&S1&~S0&Mode+~S3&S2&~S1&~S0&Mode+~S3&S2&S1&~S0&Mode+S3&~S2&~S1&~S0&Mode

    这里是最终的表达式，复制到Logisim中即可

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