ARM7 LPC2148

Prepared By
HARISH
 Inter Integrated Circuit
 It is unique for its ability to maximize hardware efficiency & circuit simplicity.
 The I2C bus uses only 2-bidirectional data lines for communicating with the
microcontroller.
 All I2C-bus compatible devices incorporate an on-chip interface which allows
them to communicate directly with each other via I2C-bus.
 I2C protocol specification can support up to 128 devices attached to the same
bus.
 Today many I2C IC devices available in the market such as Serial EEPROM, I/O
Expander, RAM, LCDs, RTC, ADC, DAC, Sensors etc…
 The I2C protocol uses master and slave method, the master which is in most
cases a microcontroller while the slave can be any I2C device such as Serial
EEPROM, RTC etc.
 The I2C protocol uses only two signals: clock and data.
 The Clock referred as SCL (Serial Clock) while data is referred as SDA
(Serial Data).

Pullup Resistors

Serial Data

Serial Clock
 In I2C protocol we have to use just two conditions START and STOP.
 A START condition is generated by master followed by 7-bit of address, then a
Read/Write (R/W) bit.
 If a slave device detects an address match then it sends ACK by driving SDA
low during the next clock cycle;
 if no slave recognizes the address then the SDA line will left alone and pulled
up high.
 Once ACK received, data will be either sent to the slave device or read from the
slave device (depending on the status of R/W bit).
 Therefore, each byte is 9-bits in which 7-bits in which 7-bits for address and one
R/W plus one ACK/NAK, or 8-bit data plus one ACK/NAK.
 The last data byte of a transaction should generally be followed by NAK, to
indicate that it is intended to be the final byte.
 After this, either a STOP or a ReSTART should be issued by the master.
 Features of I2C
 LPC2148 supports two fast I2C-buses :I2C0 & I2C1
 I2C bus interface that may be configured as Master, Slave or Master/Slave.
 Supports programmable clock to allow adjustment of multiple data speed:
1. Standard: 100 kbps
2. Fast: 400 kbps
3. High speed 3.4 Mbps
 Supports bi-directional data transfer between master and slave.
 This helps to reduce the cost and complexity of circuit as more devices allowed
to communicate through same bus.
Differences
 I2C operating modes
Each of the two I2C interfaces on the LPC214x is byte oriented and has four
operating modes:
1. Master transmitter mode
2. Master receiver mode
3. Slave transmitter mode
4. Slave receiver mode
 Master Transmitter mode
1. The first byte transmitted contains the slave address of the receiving device (7 bits) and the
data direction bit(1 bit). In this mode the data direction bit (R/W) should be 0 which means
Write.
2. Data is transmitted 8 bits at a time.
3. After each byte is transmitted, an acknowledge bit is received.
4. START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
 Master Receiver mode
In the master receiver mode, data is received from a slave transmitter.
1. When the START condition has been transmitted, the interrupt service routine must load the
slave address and the data direction bit to the I2C Data Register (I2DAT).
2. In this case, the data direction bit (R/W) should be 1 to indicate a read.
3. When the slave address and data direction bit have been transmitted and an acknowledge bit
has been received, and the Status Register will show the status code.
4. For master mode, the possible status codes are 0x40(ACK has been received), 0x48(NOT
ACK has been received), or 0x38(Arbitration lost in NOT ACK bit). For slave mode, the
possible status codes are 0x68(ACK returned), 0x78, or 0xB0
After a repeated START condition, I2C may switch to the master transmitter mode.
 Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter.
1. To initialize the slave receiver mode, user write the Slave Address Register (I2ADR) and
write the I2C Control Set Register.
2. I2C interface waits until it is addressed by its own address or general address followed by
the data direction bit.
3. If the direction bit is 0 (W), it enters slave receiver mode.
4. After the address and direction bit have been received, the SI bit is set and a valid status
code can be read from the Status Register (I2STAT).
 Slave Transmitter mode
1. In the slave mode, the I2C hardware looks for its own slave address and the general call
address. If one of these addresses is detected, an interrupt is requested.
2. When the microcontrollers wishes to become the bus master, the hardware waits until the
bus is free before the master mode is entered so that a possible slave action is not
interrupted.
3. If bus arbitration is lost in the master mode, the I2C interface switches to the slave mode
immediately and can detect its own slave address in the same serial transfer.
 I2C registers
I2CONSET (I2C Control Set Register): When a one is written to a bit of this register, the
corresponding bit in the I2C control register is set. Writing a zero has no effect.

I2CONCLR (I2C Control Clear Register): When a one is written to a bit of this register, the
corresponding bit in the I2C control register is cleared. Writing a zero has no effect.

I2STAT (I2C Status Register): During I2C operation, this register provides detailed status
codes that allow software to determine the next action needed.

I2DAT (I2C Data Register): Using for all read and write data operations.

I2ADR (I2C Slave Address Register): Contains the 7 bit slave address for operation of the I2C
interface in slave mode, and is not used in master mode.
I2SCLH (SCH Duty Cycle Register High Half Word): Determines the high time of the I2C
clock.

I2SCL (SCL Duty Cycle Register Low Half Word): Determines the low time of the I2C clock.
 I2C Control Set Register
The I2CONSET registers control setting of bits in the I2CON register that controls operation of
the I2C interface.

7 6 5 4 3 2 1:0
Reserved I2EN STA STO SI AA Reserved
I2EN (I2C Interface Enable): When I2EN is 1, the I2C interface is enabled. I2EN can be cleared by writing 1 to the
I2ENC bit in the I2CONCLR register. When I2EN is 0, the I2C interface is disabled.
STA (START flag): Setting this bit causes the I2C interface to enter master mode and transmit a START condition
or transmit a repeated START condition if it is already in master mode.
STO (STOP flag): Setting this bit causes the I2C interface to transmit a STOP condition in master mode. When
STO is 1 in master mode, a STOP condition is transmitted on the I2C bus. When the bus detects the STOP condition,
STO is cleared automatically.
SI (I2C Interrupt Flag): This bit is set when the I2C state changes.
AA (Assert Acknowledge Flag): When set to 1, an acknowledge (low level to SDA) will be returned during the
acknowledge clock pulse on the SCL line.
 I2C Control Clear Register
The I2CONCLR registers control clearing of bits in the I2CON register that controls operation of
the I2C interface.
7 6 5 4 3 2 1:0
Reserved I2ENC STAC Reserved SIC AAC Reserved
AAC (Assert Acknowledge Clear bit): Writing a 1 to this bit clears the AA bit in the I2CONSET register. Writing
0 has no effect.
SIC (I2C Interrupt Clear bit): Writing a 1 to this bit clears the SI bit in the I2CONSET register. Writing 0 has no
effect.
STAC (Start flag Clear bit): Writing a 1 to this bit clears the STA bit in the I2CONSET register. Writing 0 has no

effect.
I2ENC (I2C Interface Disable bit): Writing a 1 to this bit clears the I2EN bit in the I2CONSET register. Writing 0
has no effect.
 I2C Status Register
 Each I2C Status register reflects the condition of the corresponding Status register is Read-
Only.
 There are 26 possible status codes.
Ex: A START condition has been transmitted, A repeated START condition has been
Transmitted, Data byte in I2DAT has been transmitted, ACK has been Received…etc.

7:3 2:0
Status Reserved
 I2C Data Register
 This register contains the data to be transmitted or the data just received.

7:0
Data

I2C Slave Address Register

 These registers are readable and writable, and is only used when an I2C interface is set to
slave mode.
 In master mode, this register has no effect. The LSB of I2ADR is the general call bit. When
this bit is set, the general call address (0x00) is recognized.
7:1 0
Address GC
(I2C device address for slave mode) (General Call enable bit)
 I2C SCL High Duty Cycle Register
 Count for SCL HIGH time period selection

15:0
SCLH

I2C SCL Low Duty Cycle Register

 Count for SCL LOW time period selection

15:0
SCLL
 Selecting the I2C data rate and duty cycle
 Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data
rate and duty cycle.
 I2SCLH defines the number of PCLK cycles for the SCL high time, I2SCLL defines the
number of PCLK cycles for the SCL low time.

PCLK = 15MHz, I2C Frequency = 100KHz

Formula:
I2C Frequency = PCLK/((I2CSCLH + I2CSCLL)
(I2CSCLH + I2CSCLL) = 15000/100 = 150
So, I2CSCLH = 75, I2CSCLL=75
I2C Functions:
void i2c0_init(void);
void i2c0_start(void);
void i2c0_stop(void);
void I2C0_Write(unsigned char data, unsigned char status);
unsigned char I2C0_Read(void);
void I2C0_Init(void) 7 6 5 4 3 2 1:0
Reserved I2ENC STAC Reserved SIC AAC Reserved
{
PINSEL0 |= 0x50; /*Initialize Pin Connect Block P0.2 as SCL0 P0.3 as SDA0*/
I2C0CONCLR = 0x2C; /*Clear AA, I2C Interrupt Flag, Start Bit*/
I2C0CONSET = 0x44; /*Enable I2C0*/
7 6 5 4 3 2 1:0
I2C0SCLH = 75; RESERVED I2EN STA STO SI AA RESERVED

I2C0SCLL = 75; /*Bit Rate 100Khz*/

}

void I2C0_Start(void) 7 6 5 4 3 2 1:0

{ RESERVED I2EN STA STO SI AA RESERVED

I2C0CONSET |= 0x20; /*Set the Start Bit*/

while(I2C0STAT!=0x08); /*Wait for the Status (A START condition has been transmitted)Set*/
}
void I2C0_Stop(void) 7 6 5 4 3 2 1:0
RESERVED I2EN STA STO SI AA RESERVED
{
I2C0CONSET |= 0x14; /*Stop I2C*/
I2C0CONCLR = 0x08; /*I2C Interrupt Clear bit*/
7 6 5 4 3 2 1:0
}
Reserved I2ENC STAC Reserved SIC AAC Reserved

void I2C0_Write(unsigned char data, unsigned char status)

{
7 6 5 4 3 2 1:0
I2C0DAT = data; RESERVED I2EN STA STO SI AA RESERVED

I2C0CONSET = 0X04; /*Assert Acknowledge Flag*/

7 6 5 4 3 2 1:0
I2C0CONCLR = 0X28; Reserved I2ENC STAC Reserved SIC AAC Reserved

while(I2C0STAT!=status); /* Wait for Status Set */

}
unsigned char I2C0_Read(void) 7 6 5 4 3 2 1:0
{ RESERVED I2EN STA STO SI AA RESERVED

I2C0CONSET = 0X04; 7 6 5 4 3 2 1:0

I2C0CONCLR = 0X28; Reserved I2ENC STAC Reserved SIC AAC Reserved

while (I2C0STAT!=0x050); /* Wait for Status Set - 0x50 Data byte has been received; ACK has
been returned. */
return(I2C0DAT);
}
void EEPROM24C_Write(unsigned char data, unsigned char address);
unsigned char EEPROM24C_Read(unsigned char address);
int main()
{
unsigned char read_eeprom;
lcdinit();
lcd_str("Writing... A");
delay();
delay();
delay();
EEPROM24C_Write('A',0x00);
cmdlcd(0xC0);
read_eeprom = EEPROM24C_Read(0x00);
lcd_str("Reading... ");
datalcd(read_eeprom);
while(1); }
void EEPROM24C_Write(unsigned char data, unsigned char address)
{
I2C0_Init();
I2C0_Start();
I2C0_Write(0xA0,0x18); //Slave Address =0xA0, status: SLA+W has been transmitted; ACK has
been received.
I2C0_Write(address,0x28); //address = 0x00 for EEPROM internal Address to store data
I2C0_Write(data,0x28); //data=‘A’, status: Data byte in I2DAT has been transmitted; ACK has been received.
I2C0_Stop();
}
unsigned char EEPROM24C_Read(unsigned char address)
{
unsigned char read;
I2C0_Init();
I2C0_Start();
I2C0_Write(0xA0,0x18); //Slave Address =0xA0, status: SLA+W has been transmitted; ACK has been
received.
I2C0_Write(address,0x28); //EEPROM Address=0x00, status: Data byte in I2DAT has been transmitted; ACK has
been received.
I2C0_Stop();
I2C0_Start();
I2C0_Write(0xA1,0x40); //data=0xA1, status: SLA+R has been transmitted; ACK has been received.
read = I2C0_Read();
I2C0_Stop();
return (read);
}