37th International Conference on VLSI Design

&
23rd International Conference on Embedded Systems
VLSI meets AI & Quantum for Cyber Physical Systems
6-10 January, 2024 | Kolkata, India

Steering
ng Co
Committee
mitt Chair
hai CALL FOR PAPERS
Vishwani Agarwal,
Agarw Au Auburn University
nivers
Satya Gupta, VSI
Saty The world of Cyber Physical Systems (CPS) is transforming our industry and lives by
connecting the physical world with the cyber components in an unprecedented manner.
Gen ra Chairs
General
Rapid proliferation of CPS has led to the emergence of Industry 4.0 - the fourth industrial
Hafizur
afizzur Raham
Rahaman,
man, IIEST
EST Shibpurp
revolution that promises a new era in intelligent autonomy. The convergence of these
Abhijit
it Dutt
D
Dutta, Cyi
Cyie
Cyient, K
Kolkataa
systems with artificial intelligence technologies is fuelling powerful edge and cloud comput-
Advisoryy Committee
C mmi
m
mmit eCChair ing solutions. Similarly, quantum science and technologies are bringing new communica-
Sumit Goswa
Goswami,
osw mi Q Qualcomm
alcom
alco
lco tion, sensing and secure data processing capabilities to CPS. It may be emphasized that our
Veeresh Shetty, Siemens
mens semiconductor industry remains a pivot to enable these key technologies, offering both
Technical
al Pr
Program Chair opportunities and challenges, which when circumvented can solve global problems in the
Debdeep M
Mukhopadhyay,
ukhop IIT KGP field of agriculture, energy, climate, transportation, education, and healthcare. The confer-
Swarup Bhunia,
u ia University
nive y of F Florida
Florida,USA
USA ence aims at unearthing these issues for researchers and practitioners to see how VLSI and
Amlan Chakrabarti,
hak
krab i, Ca
Calcutta U
Univ. embedded systems can play a key role in enabling these ushering technologies.
Tutorial
ria
al C
Chair VLSID 2024 provides a platform for industry and academia alike to discuss, deliberate and
Sudeb
Sude
deb Dasgupta,, IIT
TRRoorkee delve into the frontiers in semiconductors that could eventually enable disruptive technolo-
Ujjwal Guin, Au
U
Ujj Auburn
uburn University
U gies for the next generation. Original contributions are solicited on topics covered under
Shreyas Sen,
en, Purdue
Pu due University
board broad areas such as (but not limited to):
O
Organizing
iz n Chair
C
Topics:
Tridibesh
T dibes N Nag,
ag, NSE
NSEC, Kolkata
kata
Arghajit
rghajit B
Basu,
u, Jun
Juniper Net
Net, Kolkata
ta • Hardware for AI and ML • Analog & Mixed Signal circuits
Anupam
p mD Dutta,
tta, Gl
Global Fo
Foundries • RF Circuits and Wireless systems • Sensors interfacing circuits and systems
Finance
an e C
Chaair: • Wireline and Optical Communication • Neuromorphic Circuits and Systems
Arindam
d mMMukherjee,
ukherje Alum
Alumnus,
u Kolkata
ka Circuits and Systems • Test and Reliability
Publication
ublica
a o Chair
Chair: • Embedded Systems, Internet of • Low power Digital Systems
Rajat
at S
Subhra
ubh a Chak
Chakraborty, IIT-KGP Things (IoT), and Cyber-Physical • Advances in CAD for VLSI
Jimson
Jimson Mathew, II
IIT-Patna
T-Pat System (CPS) Design • Latest trends in device design and modelling
Pr gram Man
Program Management
nage Chair • Beyond 2D in Packaging and • Hardware and Systems Security
Souvik
ouvik Basu,
Bas , Q
Qua
Qualcomm interconnects • Advanced process and Material
Sponsorship
pons rsh Chairr • Photonic Integrated Circuits • Power & Energy Management
Soumya Dey, Keys
Keysight
sight Tec
Technologies
chnologies • Emerging Computing & Post-CMOS Technologies
Sivaram Allam
Allamraju,Rambus
llam
amraju,Rambu
j
Biswajit Patra,
atra Intel
Full Paper Submission Deadline : 30th July 2023
Deesign Contest Chair
Design Chai
Notification for Acceptance: : On or Before 05th October, 2023
Maryam Shojaei Baghini,
Baghi IIT-Bombay
Subhra
S ubhra K Das, Thales
ales India
Submission & Enquiries: www.vlsid.org
Industry
dustry
try Forum
Foru
F Chair
Cha
Sudipto
dipto o Da
Das, Que
Quest
Q Global
ba Paper Submission: Authors are invited to submit full-length (6 pages maximum), original,
Navin
in Bishnoi,
Bishno M Marvell
arvel unpublished papers along with an abstract of at most 200 words. To enable blind review, the
Vishwajeet
hwajeet Betai,
Be CadCadence Design Systems author list should be omitted from the main document. Previously published papers or
Prositt Mukherjee,
Mu Qualcomm papers currently under review for other conferences/journals should NOT be submitted and
will not be considered. Electronic submission in PDF format to the http://www.vlsid.org
VSI Liaison
Li i
Chitra
hi Hariharan,
haran, IIntel
nte
website is required. Author and contact information (name, affiliation, mailing address,
telephone, fax, e-mail) must be entered during the submission process. Paper Format:
IEEE LiLiaison
Liaii n Submissions should be in camera-ready two-column format, following the IEEE
Preet Yadav
Pre Yadav, NXP Semiconductors
emic
emi
i d t proceedings specifications.
ACM
ACMM Liaison
Li i Paper Publication and Presenter Registration: Papers will be accepted for regular or
Nagi
agi Naganathan, Microsoft
poster presentations at the conference. Every accepted paper MUST have at least one author
MeitY
Y LiLiaison registered to the conference by the time the camera-ready paper is submitted; at least one of
Nishitt G
Gupta,
Gupt
pta, M
Meity
ty the authors is also expected to attend the symposium and present the paper.
 37th International Conference on VLSI Design
23rd International Conference on Embedded Systems
VLSI meets AI & Quantum for Cyber Physical Systems
6-10 January, 2024 | Kolkata, India
CALL FOR PAPERS
Hardware for AI and ML: Chips demonstrating system, architecture
and circuit innovations for machine learning and artificial intelligence,
AI accelerator design, AI boosted circuits and systems for Brain Machine
Interface, Intelligent storage, Memory Centric Accelerator Design, Low
power autonomous systems, Trusted Architectures for AI
Analog & Mixed Signal circuits: Amplifiers, comparators, oscillators,
filters, references; nonlinear analog circuits; digitally-assisted analog
circuits; Analog design at lower technology nodes, Analog Circuits for
Various Applications, Data Converters, High Speed Interfaces.
Photonic Integrated Circuits: Silicon and III-V Photonic Integrated
Circuits, Waveguides/interconnects, On-chip lasers, Optical
Multiplexers/Demultiplexers, Photo detectors and sensors, Quantum
photonics, RF Photonics, Mid-IR/THz Photonics, Heterogeneous
integration, Packaging of Photonic devices, Quantum photonics, RF
Photonics, Mid-IR and THz Photonics.
RF Circuits and Wireless systems: RF, mm-Wave and THz
transceivers, SoCs, and SiPs. frequency synthesizers, system architecture
for 5G and 6G wireless, next generation systems for radar, sensing, and
imaging. Reliability aspects in RFICs.
Wireline and Optical Communication Circuits and Systems:
Receivers/transmitters/transceivers for wireline systems, exploratory I/O
circuits for advancing data rates, bandwidth density, power efficiency,
equalization, robustness, adaptation capability, and design methodology;
building blocks for wireline transceivers (such as AGCs, analog and
ADC/DAC-based front ends, equalizers, clock generation and
distribution circuits including PLLs, line drivers, and hybrids).
Sensors interfacing circuits and systems: Sensor Interfacing,
Instrumentation, Biomedical Circuits and Healthcare Systems, Low
Noise Circuits, EMI Immune Design, Auto Calibration Techniques,
Wearable Electronics, flexible electronics, ultra-low power circuit
techniques, circuits and systems for IoT.
Neuromorphic Circuits and Systems: Device, circuit, architecture
design, analysis and optimization for neuromorphic computing systems,
Complexity and scalability of neuromorphic computing, Emerging
technologies for brain-inspired nano-computing and communication,
Applications of neuromorphic computing in embedded and IoT devices,
unmanned vehicles and drones, and cyber-physical systems.
Embedded Systems, Internet of Things (IoT), and Cyber-Physical
System (CPS) Design: ESL, System-level design methodology,
Processor and memory design, Concurrent interconnect,
Networks-on-chip, Defect Tolerant Architectures, Hardware/Software
Co-Design & Verification, Reconfigurable Computing, Embedded
Multicores SOC and Systems, Embedded Software Including Operating
Systems, Firmware, Middleware, Communication, Virtualization,
Encryption, Compression, Security, Reliability; Hybrid systems-on-chip,
Embedded for automotive and Electric Vehicles, Artificial Intelligence of
Things (AIoT), Edge Intelligence, Reconfigurable computing for IoT
and CPS, Design automation for IoT/CPS.
&
Low power Digital Systems: Next generation digital circuits, building
blocks, and complete systems (monolithic, 2.5D, and 3D) for reduced
power and form factor, near- and sub-threshold systems, emerging
applications, Energy-efficient storage systems, Digital circuits for
intra-chip communication, clock distribution, variation-tolerant design,
digital regulators and digital sensors.
Advances in CAD for VLSI: Logic and behavioural synthesis, logic
mapping, simulation and formal verification, physical design techniques,
post route optimizations, simulation Tools for Design Verification, Static
Timing and Timing Exceptions, Mixed Signal Simulations in sub 10 nm
nodes, Application of Machine Learning in CAD for VLSI, CAD for
Secured Chips.
Latest trends in device design and modelling: Deep nanoscale CMOS
devices, device modeling and simulation, multi-domain simulation,
device/circuit-level reliability and variability, Devices for beyond
CMOS, compact modeling and novel TCAD solutions.
Beyond 2D in Packaging and interconnects: Methodologies and tools
for Wafer-level packaging, embedded chip packaging, 2.5D/3D
integration, Silicon, SiC & Glass interposer, Thermal characterization
and simulation, component, system and product level thermal
management and characterization, Au/Ag/Cu/Al Wire-bond / Wedge
bond technology, Flip-chip & Cu pillar, Solder alternatives, Cu to Cu,
wafer-level bonding & die attachment (Pb-free), Fan-out, panel-level,
chiplets, SiP, micro-bump, high I/O thermocompression/hybrid bonding,
fine-pitch/multi-layer RDL, printable interconnects.
Power and Energy Management: Power management and control
circuits, regulators; power converter ICs, energy harvesting circuits and
systems; wide-bandgap topologies and gate-drivers; power and signal
isolators, Power management for automotive systems, battery
management circuits and systems.
Test and Reliability: Simulation, formal verification, validation at
different abstraction levels, DFT, fault modelling and simulation, ATPG,
BIST, fault tolerance, post-silicon validation and debug, delay test,
memory test, reliability testing, 2.5D/3D IC testing, Analog and Mixed
Signal Testing.
Emerging Computing & Post-CMOS Technologies: Quantum
Information processing systems, Quantum logic circuits, Quantum
algorithms, spin-based computing, reversible computing, approximate
and stochastic computing.
Hardware and Systems Security: Secure and trustworthy hardware,
Side-channel Attack (SCA), Fault Attacks, and mitigation, Hardware IP
Protection, Hardware Trojan attacks and mitigation, Security of
IoT/CPS, Firmware and software security, Secure crypto, Automotive
security, Physically Unclonable Functions, Hardware Design for Fully
Homomorphic Encryptions, Security of Trusted Architectures,
Micro-architectural Security.
Advanced process and Material: Advanced CMOS process,
low-dimensional materials and devices, 2D and nanowire devices,
Nano-patterning, directed self-Assembly, EUV, ALE and selective
deposition, strain/channel engineering, Advanced manufacturing
technology, metrology and yield.