TEPZZ 54_¥6¥B_T

(19)

(11) EP 2 541 363 B1

(12) EUROPEAN PATENT SPECIFICATION

(45) Date of publication and mention (51) Int Cl.:

of the grant of the patent: G05F 1/575 (2006.01) G05F 3/26 (2006.01)
14.05.2014 Bulletin 2014/20 G05F 1/59 (2006.01)

(21) Application number: 11368014.4

(22) Date of filing: 13.04.2011

(54) LDO with improved stability

Regler mit geringer Abfallspannung mit verbesserter Stabilität
Régulateur de tension à faible chute de tension avec stabilité améliorée

(84) Designated Contracting States: (72) Inventor: Childs, Mark

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB Lydiard Millicent, Wilts SN5 3L2 (GB)
GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO
PL PT RO RS SE SI SK SM TR (74) Representative: Schuffenecker, Thierry
120 Chemin de la Maure
(43) Date of publication of application: 06800 Cagnes sur Mer (FR)
02.01.2013 Bulletin 2013/01
(56) References cited:
(73) Proprietor: Dialog Semiconductor GmbH WO-A1-2007/009484 US-A- 5 600 234
73230 Kirchheim/Teck-Nabern (DE) US-A- 5 672 959 US-B2- 6 856 124
US-B2- 7 872 454
EP 2 541 363 B1

Note: Within nine months of the publication of the mention of the grant of the European patent in the European Patent
Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been
paid. (Art. 99(1) European Patent Convention).

Printed by Jouve, 75001 PARIS (FR)

 1 EP 2 541 363 B1
Description
Technical field
[0001] The invention relates to a low drop-out (LDO)
voltage regulator, and more particularly to eliminating
stability problems for LDOs with very low bond wire re-
sistance or no bond wires at all.
Background Art
[0002] Currently, low drop-out (LDO) voltage regula-
tors which use advanced techniques usually require that
the bond wire impedance is within a reasonably tightly
controlled range in order that the LDO is stable. However,
the move to advanced package types will mean that no
bond wires are used where these LDOs easily become
unstable. Many solutions to the above problems associ-
ated with unstable LDOs have been proposed in the re-
lated art, many with complex and thus costly schemes.
Reference is made to U.S. Patent No.6,856,124, entitled
"LDO Regulator With Wide Output Load Range And Fast
Internal Loop" issued Feb. 15, 2005 and assigned to the
assignee of this application. That patent shows a method
and a circuit to achieve a low drop-out voltage regulator
with a wide output load range. A fast loop is introduced
in the circuit. The circuit is internally compensated and
uses a capacitor to ensure that the internal pole is more
dominant than the output pole as in standard Miller com-
pensation. The quiescent current is set being proportion-
al to the output load current. No explicit low power drive
stage is required. The whole output range is covered by
one output drive stage. This technique however does not
address the above mentioned problem with the very low
resistances that are associated with the absence of bond
wires.
[0003] What is needed is an easy-to-implement and
cost effective solution which will insure that the LDO re-
mains stable with a minimal amount of degradation in
performance or current consumption. These needs are
met by the present invention, which assures a stable cir-
cuit between equivalent series resistance (ESR) ranges
of 100mΩ and 1mΩ.
[0004] U.S. Patents which relate to the subject of the
present invention are: U. S. Patent Application 7,710,091
B2 (Huang) discloses an LDO voltage regulator which
utilizes nested Miller compensation and pole-splitting to
move the dominant pole to the output of a first-stage am-
plifier. An active resistor is arranged in the feedback path
of a Miller capacitor to increase the controllability of the
damping factor.
[0005] U. S. Patent Application 7,679,437 B2 (Tade-
parthy et al.) describes a split feedback technique and a
scheme for improving the degradation of load regulation
caused by additional metal resistance in an amplifier (an
LDO) of the type wherein a feedback loop for the amplifier
is deployed and where the feedback loop might be viewed
as including a feedback resistance and a capacitance
2
connected in parallel.
[0006] U. S. Patent 7,656,139 B2 (van Ettinger) shows
a negative feedback amplifier system in which part of the
supplied output current is diverted through a first "zero"
5 resistor before adding it to the output voltage, and also
using a second "boost zero" compensating resistor be-
tween the amplifier and the first current control element.
[0007] U. S. Patent 7,589,507 B2 (Mandal) teaches a
stability compensation circuit for an LDO driving a load
10 capacitor in a range of few nano-Farads to few hundreds
of nano-Farads with a good phase margin over a no load
to full load current range, and maintains minimum power
area product for an LDO suitable for a SoC integration.
[0008] U. S. Patent 7,323,853 B2 (Tang et al.) presents
15 an LDO voltage regulator which comprises an error am-
plifier with a common-mode feedback unit, a pass device,
a feedback circuit, and a compensation circuit to provide
a stable output voltage with a high slew rate and simple
configuration when the load capacitance has a large
20 range.
[0009] It should be noted that none of the above-cited
examples of the related art provide the advantages of
the below described invention.
[0010] US 6856124 discloses a LDO regulator with
25 wide output load range and fast internal loop.
[0011] US 7 872454 discloses a low dropout (LDO)
regulator including a switch module to generate the out-
put voltage, which switch module includes at least two
parallel connected switches responsive to corresponding
30 switch control signals to regulate a flow of energy from
the input source to the output.
Summary of the invention
35 [0012] It is an object of at least one embodiment of the
present invention to provide a low drop-out voltage reg-
ulator and a method to mimic the external equivalent se-
ries resistance of the bond wire.
[0013] It is another object of the present invention to
40 allow very quick and easy porting of one design of a low
drop-out voltage regulator to different packages.
[0014] It is yet another object of the present invention
to improve the phase margin of the low drop-out voltage
regulator to be well within the positive range.
45 [0015] It is still another object of the present invention
to provide a low drop-out voltage regulator which is stable
with very little degradation in performance or current con-
sumption.
[0016] It is a further object of the present invention is
50 to provide a low drop-out voltage regulator which is suit-
able for applications where no bond wires are used.
[0017] These and many other objects have been
achieved by splitting the main pass device into two une-
qual parts, by placing a controlled impedance in series
55 with the smaller part of the pass device, and to take the
fast feedback loop from the node between the pass de-
vice and the impedance and couple it back to the Miller
capacitor. The channel width of the smaller part of the
2
 3 EP 2 541 363 B1
pass device is dimensioned to be about one twentieth
the width of the larger pass device. The impedance cou-
pled to the smaller part of the pass device has a resist-
ance of typically 2Ω but which can vary in size depending
on specific requirements.
[0018] These and many other objects and advantages
of the present invention will be readily apparent to one
skilled in the art to which the invention pertains from a
perusal of the claims, the appended drawings, and the
following detailed description of the preferred embodi-
ments.
Description of the drawings
[0019]
FIG. 1 is a block diagram of a conventional LDO cir-
cuit.
FIG. 2 is a circuit diagram of the preferred embodi-
ment of the present invention.
FIGS. 3a and 3b are graphs of the conventional LDO
of Fig. 1, showing magnitude and phase response
versus frequency for an ESR of 100mΩ and 1mΩ,
respectively.
FiGs. 3c and 3d are graphs of the LDO of Fig. 2,
showing magnitude and phase response versus fre-
quency at the output of the LDO for an ESR of 100mΩ
and 1mΩ, respectively.
FIG. 4 is a block diagram of the method of the present
invention.
[0020] Use of the same reference number in different
figures indicates similar or like elements.
Description of the preferred embodiments
[0021] Fig. 1 shows in more detail the low drop-out
voltage regulator (LDO) 100 of the above referenced U.S.
Patent No.6,856,124. A differential amplifier 110 couples
via node 160 to a buffer 112 which drives nmos transistor
114 with output node 161. A current mirror stage 116 is
coupled to output node 161 and drives the current mirror
output pmos transistor118, the main pass device. The
current mirror input is pmos transistor 117. The output
162, the drain of pmos transistor 118, couples to wire
bond (Rbond) 120. The other side of wire bond 120 cou-
ples to node (Vout) 164 of LDO 100. Also shown but not
strictly part of the circuit are: capacitor (Cout) 130 with
its intrinsic equivalent series resistance (ESR) 132 and
current source (lout) 140 coupled between node 164 and
Vss (typically Ground).
[0022] A main feedback loop 180 couples from node
(Vout) 164 via resistors 150 and 152 to Vss. The junction
of resistors 150 and 152 is node 154 which is one of the
4
two inputs to differential amplifier 110. The other input is
a reference voltage Vref. A fast feedback loop 182, cou-
ples from node 162 via capacitor (Cmiller) 115 to node
160, the input to buffer 112.
5 [0023] In the current design practice, per Fig. 1, an
internally compensated design with a ’smart-mirror’ drive
scheme is used and comprises buffer 112 plus the two
transistors 114 and 117. This smart-mirror controls the
output of transistor 118, the buffer 112 can be low power
10 while transistors 114 and 117 pass current in proportion
to the output power of the LDO, meaning that when the
pass device is lightly loaded, the drive current is reduced.
Conversely, large voltage swings on the pass device gate
are driven by similar large bias currents through the driv-
15 er. The current design practice takes this further by using
the mirrored currents as a large fraction of the bias cur-
rents in the preceding amplifier stage 110 and buffer 112
of the LDO.
[0024] To regulate the output (Vout) the main feedback
20 loop 180 is included. This feedback loop divides down
the output voltage of the LDO with a resistive chain (150
and 152), and then amplifies this result with respect to a
1.2V reference Vref. This amplifies the error in the output
voltage Vout and so regulates the output. This feedback
25 loop is held stable by a low voltage pole added by the
internal-compensation Miller-capacitor. This means the
LDO has high gain at DC but the gain of this main feed-
back loop is low at high frequencies.
[0025] In order to improve the performance of the LDO
30 at higher frequencies a fast feedback loop (182) is in-
cluded. This feedback loop is formed by the existing Miller
capacitor and provides a means of feedback for high-
frequency disturbances at the output 162 directly to the
input of the smart-mirror stage. This feedback loop can
35 be visualized as such: any high-frequency current signal
should be supplied directly from the load capacitor (Cout)
130, which will look like a short to ground (Vss). However,
the series impedance of the capacitor 130 will mean that
a small voltage will be developed across the capacitor
40 component. This voltage can be passed back to the input
of buffer 112 and used to correct the output current with-
out seeing any low-frequency poles. Since the Miller ca-
pacitor is connected before the output bond i.e. wire bond
(Rbond) 120, the impedance of these bonds is also in-
45 cluded with the capacitor (Cout) 130 ESR.
[0026] Recently the ESR of the wire bonds and of the
capacitors have fallen to the extent that this fast feedback
loop 182 high-frequency zero node has moved out of the
bandwidth of the LDO, and the fast feedback loop has
50 become unstable. As the move to copper bond wires or
CSP (Chip Scale Packaging) packages will further re-
duce the ESR. The present invention addresses this
problem and provides a solution as described below.
55 Proposal
[0027] Case 1: One solution is to place a series resistor
between the pass device and the output Vout, artificially
3
 5 EP 2 541 363 B1
increasing the equivalent ESR. However, this fix will im-
pact the drop-out voltage of the LDO and the load-tran-
sient behavior. For output load models we have assumed
an equivalent ESR of 100mΩ. With this ESR, a simulation
run shows that the LDO has a phase-margin of about 40°
at 100mA output current, Vout = 2.4V and Vdd = 3V. If
this ESR is reduced to the unlikely case of 1mΩ, then
this phase margin falls to about -5°.
[0028] Referring to Fig. 3a, we show a graph of a com-
puter simulation of Case 1 and an ESR of 100mΩ with
Vout = 2.4V and Vdd = 3V, for an output current of 100mA
as described above. The horizontal axis displays fre-
quency in Hz ranging from 10-1 to 107. The vertical axis
displays Y0 in db for output and Y1 in degrees for the
phase. Curve 1 shows the magnitude of the output signal
Vout, Curve 2 shows the phase. At Vout=0 the phase
margin is 31.47° i.e. the circuit is stable.
[0029] Referring to Fig. 3b, we show a graph of a com-
puter simulation of Case 1 and an ESR of 1mΩ with Vout,
Vdd = 3V and output current as described above. Curve
3 shows the magnitude of the output signal Vout, Curve
4 shows the phase. At Vout=0 the phase margin is -23.18°
i.e. the circuit is unstable.
[0030] Case 2: In the preferred embodiment of the
present invention, and referring to Fig. 2, we propose to
add another pass device in parallel with the main pass
device. A more detailed description of this new circuit
follows below. This pass device 218 would be typically
about 5% of the existing 100% channel width of the main
pass118 device, but pass device 218 may range from
between about 1 to 10% but preferably ranges from be-
tween about 0.5 to 15% of the existing channel width of
the main pass device. The new pass device will share
the power connection and the gate connection. However,
between the drain and the output of the LDO is placed a
resistor of typically about 2Ω but which may range from
between about 1 to 5Ω but preferably ranges from be-
tween about 0.5 to 10Ω. The Miller capacitor is now con-
nected to the drain of this new pass device. This means
the Miller capacitor sees a much greater ESR, and so it
amplifies the fast feedback loop gain, moving the zero
node back within the bandwidth. The major pass device
still has low ESR, and so the drop-out performance re-
mains unchanged. In this case the phase-margin now
exceeds the previous 100mΩ ESR environment.
[0031] Again referring to Fig. 2, we now describe the
low drop-out voltage regulator (LDO) 200 of the preferred
embodiment of the present invention: The present inven-
tion is different in several main aspects from the conven-
tional circuit of Figure 1.
[0032] Current mirror stage 116 is replaced by current
mirror stage 216 which uses a third and smaller current
mirror pmos transistor as pass device 218, as discusses
above. Another difference is that the drain of pass device
218 is coupled via node 262 to a small resistor 220 which
in turn is coupled to output node 162. The main feedback
loop 180 is unchanged but a new fast feedback loop 282
is coupled from node 262 via capacitor (Cmiller) 115 to
6
node 160, the input to buffer 112.
[0033] Referring now to Fig. 3c we show a graph of a
computer simulation of Case 2, the preferred embodi-
ment of the present invention, with the same conditions
5 as for Case 1, that is with and an ESR of 100mΩ and
Vout = 2.4V and Vdd = 3V, for an output current of 100mA.
The horizontal axis displays frequency in Hz ranging from
10-1 to 107. The vertical axis displays Y0 in db for output
and Y1 in degrees for the phase. Curve 5 shows the
10 magnitude, Curve 6 shows the phase of the output signal
Vout. It can be seen that at Vout=0 the phase margin has
improved to 44.97°.
[0034] Referring to Fig. 3d, we show a graph of a com-
puter simulation of Case 2 and an ESR of 1mΩ with Vout,
15 Vdd = 3V and output current as described above. Curve
7 shows the magnitude of the output signal Vout, Curve
8 shows the phase. It can be seen that at Vout=0 the
phase margin has improved to 28.27° i.e. the circuit is
now stable.
20 [0035] Referring again to the low drop-out voltage reg-
ulator 200 of Fig. 2, we provide a second description of
the preferred embodiment of the present invention:
Shown is an amplifier 110 which amplifies input sig-
25 nals, having as inputs an input node 154 and a ref-
erence node Vref and an output node 160;
a buffer 112, followed by an nmos transistor 114,
having its buffer input node coupled to the amplifier
output node and further having an output node 161;
30 a pass device 216 of a current mirror, the pass device
having its input node coupled to the buffer output
node, and having an output node 162, where the
pass device further comprises;
a first pmos transistor 118, representing a first output
35 side 162 of the current mirror, where the drain of the
first pmos transistor is coupled to the pass device
output node;
a second pmos transistor 218 representing a second
output side of the current mirror, where the second
40 pmos transistor, in series with resistor 220, is in par-
allel with the first pmos transistor and where the junc-
tion of the second pmos transistor and resistor pro-
vides a feedback node 262;
a bond wire 120 coupled at one end to the pass de-
45 vice output node and coupled at its other end to a
low drop-out voltage regulator output node 164;
a main feedback loop 180 which regulates the output
voltage Vout at the low drop-out voltage regulator
output node, where one end is coupled to the low
50 drop-out voltage regulator output node and the other
end is coupled to the amplifier input node; and
a fast feedback loop 282 which feeds back high-fre-
quency disturbances from the low drop-out voltage
regulator output node, the fast feedback loop com-
55 prising a Miller feedback capacitor 115, where one
end of the fast feedback loop is coupled to the feed-
back node and where the other end is coupled to the
buffer input node.
4
 7 EP 2 541 363 B1
[0036] The differential amplifier 110 and buffer 112
mentioned above and in subsequent descriptions below
may be some other type of amplifier and implies a device
which amplifies a signal, and may be a transistor or a
transistor circuit, either of these in discrete form or in
integrated circuits (IC) depending on the particular im-
plementation of the LDO voltage regulator. These devic-
es are cited by way of illustration and not of limitation, as
applied to amplifiers.
[0037] The pmos transistors mentioned above and in
subsequent descriptions below may be substituted with
nmos transistors, or a mix of MOS transistors or other
transistor types, and imply devices such a transistor cir-
cuit, either of these in discrete form or in integrated cir-
cuits (IC), depending on the particular implementation of
the LDO voltage regulator. These devices are cited by
way of illustration and not of limitation, as applied to tran-
sistors.
[0038] Capacitors mentioned above and in subse-
quent descriptions below may be implemented as a tran-
sistor, transistors or a transistor circuit, either of these in
discrete form or in integrated circuits (IC). These devices
are cited by way of illustration and not of limitation, as
applied to capacitors .
[0039] We now describe with reference to Fig. 4 a pre-
ferred method of the present invention to move a fast
loop high-frequency zero node back into the bandwidth
of the LDO:
Block 1 provides a feedback input to an amplifier;
Block 2 couples a buffer to the output of the amplifier;
Block 3 couples a first pass device between the out-
put of the buffer and a wire bond;
Block 4 parallels a second pass device, in series with
a resistor, with the first pass device thereby creating
an extra equivalent series resistance to move a zero
of the low drop-out voltage regulator within its band-
width;
Block 5 couples the wire bond to the output of the
low drop-out voltage regulator;
Block 6 creates a main feedback loop from the output
of the low drop-out voltage regulator to the feedback
input of the amplifier; and
Block 7 creates a fast feedback loop from a junction
of the second pass device in series with a resistor
to an input of the buffer via a Miller capacitor.
Claims
1. A modified low drop-out voltage regulator (200),
comprising:
An amplifier stage comprising:
- an amplifier (110) having an input (154)
and an output (160); where the input is the
output of a low drop-out voltage regulator
8
output node (164);
- a buffer (112) having an input(160) and an
output (161), its input coupled to said output
of said amplifier (110), to buffer the output
5 signal of said amplifier, said buffer (112)
providing an output signal ;
- a first pass device (118) of an output stage
(216) in communication with said buffer out-
put (161) to provide a first current at a first
10 output node (162) of said output stage;
- a bond wire (120) coupled at one end to
said first output node (162) and at its other
end to said low drop-out voltage regulator
output node (164);
15 - a main feedback loop (180) to regulate an
output voltage Vout at said low drop-out
voltage regulator output node, where one
end is coupled to said low drop-out voltage
regulator output node (164) and the other
20 end is in communication with said amplifier
input (154); and
- a fast feedback loop (282) to feed back
high-frequency disturbances, where one
end of said fast feedback loop is coupled to
25 said second output node (262) and where
the other end is coupled to said buffer input
node (160), said fast feedback loop (282)
comprising a Miller feedback capacitor
(115);
30
Characterized by :
- a second pass device (218) of said output stage
in communication with said buffer output (161)
35 to provide a second current at a second output
node (262) of said output stage (216); and
- a resistive means (220) coupled between said
first (162) and second (262) output node.
40 2. The modified low drop-out voltage regulator of claim
1, wherein said output voltage Vout is generated by
a voltage divider comprising the resistance of said
bond wire and an equivalent series resistance (ESR)
of a load capacitor.
45
3. The modified low drop-out voltage regulator of claim
1, wherein each control gate of said first and second
pass device of said output stage is in communication
with said buffer output.
50
4. The modified low drop-out voltage regulator of claim
1, wherein said first and second pass device - e.g.
MOS transistors - of said output stage are coupled
to a power supply.
55
5. The modified low drop-out voltage regulator of claim
1, wherein said second pass device ranges in chan-
nel width from between about 2 % to 15 % of the
5
 9 EP 2 541 363 B1
width of said first pass device.
6. The modified low drop-out voltage regulator of claim
1, wherein said main feedback loop comprises a volt-
age divider having a center node and where further
said center node is coupled to said amplifier input.
7. The modified low drop-out voltage regulator of claim
2, wherein said main feedback loop receives said
output voltage Vout, generated by a voltage divider
comprising the resistance of said bond wire and said
equivalent series resistance (ESR) of a load capac-
itor.
8. The modified low drop-out voltage regulator of claim
1 where a reference node of said amplifier receives
a reference voltage.
9. A method of moving a high-frequency zero back into
the bandwidth of a low drop-out voltage regulator
(200), comprising the steps of:
a) providing a feedback input (154) to an ampli-
fier (110);
b) coupling a buffer (112) to the output of said
amplifier (110);
c) coupling a first pass device (118) between the
output (161) of said buffer (112) and a wire bond
(120);
d) paralleling a second pass device (218), in se-
ries with a resistor (220), with said first pass de-
vice (118) thereby creating an extra equivalent
series resistance to move a zero of said low
drop-out voltage regulator (200) within its band-
width;
e) coupling said wire bond (120) to the output
(164) of said low drop-out voltage regulator
(200);
f) creating a main feedback loop (180) from said
output (164) of said low drop-out voltage regu-
lator (200) to said feedback input (154) of said
amplifier (110); and
g) creating a fast feedback loop (282) from a
junction (262) of said second pass device (218)
in series with said resistor (220) to an input (160)
of said buffer (116) via a Miller capacitor (115).
10. The method of moving a high-frequency zero back
into the bandwidth of said low drop-out voltage reg-
ulator of claim 9, wherein a reference input node of
said amplifier receives a reference voltage, and/or
wherein said second pass device ranges in channel
width from between about 2 % to 15 % of the width
of said first pass device ; and/or
wherein said resistor ranges from between about 0.2
ohm to 5 ohm.
10
Patentansprüche
1. Modifizierter Regler (200) mit geringer Abfallspan-
nung, aufweisend:
5
eine Verstärkerstufe, aufweisend:
- einen Verstärker (110) mit einem Eingang
(154) und einem Ausgang (160), wobei der
10 Eingang der Ausgang eines Ausgangskno-
tens (164) mit geringer Abfallspannung ist,
- einen Speicher (112) mit einem Eingang
(160) und einem Ausgang (161), dessen
Eingang mit dem Ausgang des Verstärkers
15 (110) gekoppelt ist, um das Ausgangssignal
des Verstärkers zu speichern, wobei besag-
ter Speicher (112) ein Ausgangssignal zur
Verfügung stellt,
- eine erste Pass-Vorrichtung (118) einer
20 Ausgangsstufe (216), die in Verbindung mit
dem Speicherausgang (161) steht, um ei-
nen ersten Strom am ersten Ausgangskno-
ten (162) der Ausgangsstufe zur Verfügung
zu stellen,
25 - einen Verbindungsdraht (120), der mit ei-
nem Ende mit dem ersten Ausgangsknoten
(162) und mit seinem anderen Ende mit
dem Ausgangsknoten (164) des Reglers
mit geringer Abfallspannung verbunden ist,
30 - eine Hauptrückkopplungsschleife (180),
um eine Ausgangsspannung Vout am Aus-
gangsknoten (164) des Reglers mit gerin-
ger Abfallspannung zu regeln, wobei ein
Ende mit dem Ausgangsknoten (164) des
35 Reglers mit geringer Abfallspannung ver-
bunden ist, und das andere Ende in Verbin-
dung mit dem Eingang (154) des Verstär-
kers ist; und
- einer schnellen Rückkopplungsschleife
40 (282), um hochfrequente Störungen zu-
rückzuführen, wobei ein Ende der schnellen
Rückkopplungsschleife mit dem zweiten
Ausgangsknoten (262) verbunden ist, und
wobei das andere Ende mit dem Speicher-
45 eingangsknoten (160) verbunden ist, wobei
die schnelle Rückkopplungsschleife (282)
einen Miller-Rückkopplungskondensator
(115) aufweist,
50 gekennzeichnet durch:
- eine zweite Pass-Vorrichtung (218) der Aus-
gangsstufe, die in Verbindung mit dem Spei-
cherausgang (161) steht, um einen zweiten
55 Strom in einem zweiten Ausgangsknoten (262)
der Ausgangsstufe (216) zu erzeugen; und
- ein Widerstandsmittel (220), das zwischen
dem ersten (162) und zweiten (262) Ausgangs-
6
 11 EP 2 541 363 B1
knoten eingebunden ist.
2. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei die Ausgangsspannung
Vout durch einen Spannungsteiler erzeugt wird, der
den Widerstand des Verbindungsdrahts und eines
Ersatz-Serien-Widerstandes (ESR) eines Lastkon-
densators aufweist.
3. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei jedes Steuergate der ersten
und zweiten Pass-Vorrichtung der Ausgangsstufe in
Verbindung mit dem Speicherausgang steht.
4. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei die erste und zweite Pass-
Vorrichtung - z.B. MOS Transistoren - der Ausgangs-
stufe mit einer Energieversorgung gekoppelt sind.
5. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei die Kanalbreite der zweiten
Pass-Vorrichtung im Bereich von etwa 2% bis 15%
der Breite der ersten Pass-Vorrichtung liegt.
6. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei die Hauptrückkopplungs-
schleife einen Spannungsteiler aufweist mit einem
Mittelknoten, und wobei der Mittelknoten mit dem
Verstärkereingang verbunden ist.
7. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 2, wobei die Hauptrückkopplungs-
schleife die Ausgangsspannung Vout empfängt, die
durch einen Stromteiler, aufweisend den Widerstand
des Verbindungsdrahts und des Ersatz-Serien-Wi-
derstandes (ESR) eines Lastkondensators, erzeugt
wird.
8. Modifizierter Regler mit geringer Abfallspannung
nach Anspruch 1, wobei ein Referenzknoten des
Verstärkers eine Referenzspannung empfängt.
9. Verfahren zum Zurückschieben einer hochfrequen-
ten Nullstelle in die Bandbreite eines Reglers (200)
mit geringer Abfallspannung, aufweisend die Schrit-
te:
a) Vorsehen eines Rückkopplungseingangs
(154) eines Verstärkers (110),
b) Verbinden eines Speichers (112) mit dem
Ausgang des Verstärkers (110),
c) Verbinden einer ersten Pass-Vorrichtung
(118) mit dem Ausgang (161) des Speichers
(112) und einem Verbindungsdraht (120),
d) Parallelschalten einer zweiten Pass-Vorrich-
tung (218), die in Reihe mit einem Widerstand
(220) ist, mit der ersten Pass-Vorrichtung (118),
wodurch eine zusätzlicher äquivalenter Reihen-
12
widerstand erzeugt wird, um eine Null des Reg-
lers (200) mit geringer Abfallspannung innerhalb
dessen Bandbreite zu verschieben,
e) Verbinden des Verbindungsdrahts (120) mit
5 dem Ausgang (164) des Reglers (200) mit ge-
ringer Abfallspannung,
f) Erzeugen einer Hauptrückkopplungsschleife
(180) von dem Ausgang (164) des Reglers (200)
mit geringer Abfallspannung zu dem Rückkopp-
10 lungseingang (154) des Verstärkers (110), und
g) Erzeugen einer schnellen Rückkopplungs-
schleife (282) von einer Verbindung (262) der
zweiten Pass-Vorrichtung (218) in Reihe mit
dem Widerstand (220) zu einem Eingang (160)
15 des Speichers (116) über einen Miller-Konden-
sator (115).
10. Verfahren zum Zurückschieben einer hochfrequen-
ten Nullstelle in die Bandbreite eines Reglers (200)
20 mit geringer Abfallspannung nach Anspruch 9, wo-
bei ein Referenzeingangsknoten des Verstärkers ei-
ne Referenzspannung empfängt, und/oder
wobei die zweite Pass-Vorrichtung im Bereich von
etwa 2% bis 15% der Breite der ersten Pass-Vor-
25 richtung liegt, und/oder
wobei der Widerstand in einem Bereich von zwi-
schen etwa 0,2 Ohm und 5 Ohm liegt.
30 Revendications
1. Un régulateur de tension a faible chute de tension
modifié (200), comprenant :
35 un étage amplificateur comportant :
- un amplificateur (110) ayant une entrée
(154) et une sortie (160), dans lequel l’en-
trée est la sortie d’un noeud de sortie (164)
40 du régulateur de tension à faible chute de
tension ;
- un tampon (112) ayant une entrée (160)
et une sortie (161), son entrée étant couplée
à ladite sortie dudit amplificateur (110), pour
45 la mise en tampon du signal de sortie dudit
amplificateur, ledit tampon (112) générant
un signal de sortie :
- un premier dispositif de transfert (118) d’un
étage de sortie (216) en connexion avec la-
50 dite sortie du tampon (161) pour fournir un
premier courant à un premier noeud de sor-
tie (162) dudit étage de sortie ;
- un fil de connexion (120) couplé à une ex-
trémité dudit premier noeud de sortie (162)
55 et à son autre extrémité audit noeud de sor-
tie du régulateur de tension à faible chute
de tension (164) ;
- une boucle de contre-réaction principale
7
 13 EP 2 541 363 B1
(180) pour la régulation d’un potentiel de
sortie Vout audit noeud de sortie du régu-
lateur de tension à faible chute de tension,
dans lequel une extrémité est couplée audit
noeud de sortie (164) du régulateur de ten-
sion à faible chute de tension et l’autre ex-
trémité est en connexion avec ladite entrée
d’amplificateur (154) ; et
- une boucle de contre-réaction rapide (282)
pour le retour des perturbations haute-fré-
quences, dans laquelle une extrémité de la-
dite boucle de contre-réaction rapide est
couplée audit second noeud de sortie (262)
et dans lequel l’autre extrémité est couplée
audit noeud d’entrée du tampon (160), la-
dite boucle de contre-réaction (282) com-
portant une capacité de retour de Miller
(115) ;
caractérisé par :
- un second dispositif de transfert (218) dudit
étage de sortie en connexion avec ladite sortie
de tampon (161) pour générer un second cou-
rant à un second noeud de sortie (262) dudit
étage de sortie (216) ; et
- des moyens résistifs (220) couplés entre les-
dits premier (162) et second (262) noeuds de
sortie.
2. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel ledit po-
tentiel de sortie Vout est généré par un diviseur de
tension comportant la résistance dudit fil de con-
nexion et une résistance série équivalente (ESR)
d’une capacité de charge.
3. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel chaque
grille de commande dudit premier et second dispo-
sitif de transfert dudit étage de sortie est en con-
nexion avec ladite sortie de tampon.
4. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel lesdits pre-
mier et second dispositifs de transfert - par exemple
des transistors MOS - dudit étage de sortie sont cou-
plée à une alimentation de courant.
5. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel ledit se-
cond dispositif de transfert varie au niveau de la lar-
geur de canal entre environ 2% et 15% de la largeur
dudit premier dispositif de transfert.
6. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel ladite bou-
cle de contre-réaction principale comporte un divi-
14
seur de tension ayant un noeud central et dans lequel
ledit noeud central est couplé à ladite entrée d’am-
plificateur.
5 7. Le régulateur de tension à faible chute de tension
modifié de la revendication 2, dans lequel ladite bou-
cle de contre-réaction principale reçoit ledit potentiel
de sortie Vout, généré par un diviseur de tension
comprenant la résistance dudit fil de connexion et
10 ladite résistance série équivalente (ESR) d’une ca-
pacité de charge.
8. Le régulateur de tension à faible chute de tension
modifié de la revendication 1, dans lequel un noeud
15 de référence dudit amplificateur reçoit un potentiel
de référence.
9. Une méthode pour ramener un zéro haute-fréquen-
ce dans la largeur de bande d’un régulateur de ten-
20 sion à faible chute de tension (200), comportant les
étapes :
a) la mise à disposition d’une entrée de contre-
réaction (154) d’un amplificateur (110) ;
25 b) le couplage d’un tampon (112) à la sortie dudit
amplificateur (110) ;
c) le couplage d’un premier dispositif de transfert
(118) entre la sortie (161) dudit tampon (112) et
un fil de connexion (120) ;
30 d) la mise en parallèle d’un second dispositif de
transfert (218), en série avec une résistance
(220), avec ledit premier dispositif de transfert
(118), créant ainsi une résistance série équiva-
lente supplémentaire pour déplacer un zéro du-
35 dit régulateur de tension à faible chute de ten-
sion vers sa bande ;
e) le couplage dudit fil de connexion (120) à la
sortie (164) dudit régulateur de tension à faible
chute de tension (200) ;
40 f) la création d’une boucle de contre-réaction
principale (180) depuis ladite sortie (164) dudit
régulateur de tension à faible chute de tension
(200) vers une entrée de contre-réaction (154)
dudit amplificateur (110) ; et
45 g) la création d’une boucle de contre-réaction
rapide (282) depuis une jonction (262) dudit se-
cond dispositif de transfert (218) en série avec
ladite résistance (220) vers une entrée (160) du-
dit tampon (116) via une capacité Miller (115).
50
10. La méthode pour ramener un zéro haute-fréquence
dans la largeur de bande d’un régulateur de tension
à faible chute de tension de la figure 9, dans laquelle
un noeud d’entrée de référence dudit amplificateur
55 reçoit un potentiel de référence, et/ou
dans laquelle ledit second dispositif de transfert varie
au niveau de la largeur du canal entre environ 2%
jusqu’à 15% de la largeur dudit premier dispositif de
8
 15 EP 2 541 363 B1 16

transfert ; et/ou
dans laquelle ladite résistance varie entre environ
0.2 ohm et 5 ohm.

10

15

20

25

30

35

40

45

50

55

9
EP 2 541 363 B1

10
EP 2 541 363 B1

11
EP 2 541 363 B1

12
EP 2 541 363 B1

13
EP 2 541 363 B1

14
EP 2 541 363 B1

15
EP 2 541 363 B1

16
 EP 2 541 363 B1

REFERENCES CITED IN THE DESCRIPTION

This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description

• US 6856124 B [0002] [0010] [0021] • US 7589507 B2, Mandal [0007]

• US 7710091 B2, Huang [0004] • US 7323853 B2, Tang [0008]
• US 7679437 B2, Tadeparthy [0005] • US 7872454 B [0011]
• US 7656139 B2, van Ettinger [0006]

17