COURSE 111 Introduction to Digital Design

Assignment #: 4 Lab5

Section #: 16

Submitted by:
1. Ahmed Hafez El-Sayed, V23010322
2. Ahmed Gaber Mohamed, V23010611
3. Ahmed Mohamed Qorany, V23010564
4. Mostafa Khaled Fouad, V23010279

Submitted to TA: Mohamed Elshafey

Date: 28/10/2023
Simple Moore FSM

Below is the state transi�on diagram that we created a�er applying all needed
parameters.

And below is the auto generated code from the diagram:

Assignment:

Below is our main code:

First, we make parameters for width and

depth of our register and define our
input and outputs.
Then iden�fy the register.

Here we make all values of the register

equal 0.

The code here make the register

respond it receive a clock or reset signal
as reset is asynchronous signal and
resets all values to 0.

If statement here check whether the R/W pin is

LOW Register Writes from input
if HIGH Register Reads and send to output.
Second our testbench code:

first se�ng our �me scale

then iden�fy our parameters

then atach our code with testbench

here the clock signal

changes every 5 ns.

We test wri�ng data in 2 different

loca�ons in the register,
Then we read and send them out from
our 2 outputs.
in full write test we write in all registers
the binary value of the range from 300
to 315.

And in full read mode we should get

from each output all the values in the
registers.
 Simula�on:

If we give an order to read from register and it was empty the output will be 0 as we made an
ini�aliza�on condi�on to set all values to 0 at start.

First, we set the value of address 0001 with value of (100)D or (1100100)B
then we set the value of address 0010 with value of (200)D or (11001000)B
then the value of read pin changes so the 2 values saved get out through our 2 outputs
and then start the full write mode �ll we reach the address of 1111 with value of (315)D or
(100111011)B

next we made a condi�on if address3 reaches 1111 the read pin changes so we read the values
in register with address 0001 and 0010 with values of 300 => 100101100 and 301 => 100101100
respec�vely.
We made this condi�on as we have a problem with for loop doesn’t end, I’ll be glad to learn the
solu�on for this problem.
 DataOut1[11]$latch

DATAIN
LATCH_ENABLE OUT0 DataOut1[15..0]
1'h0
ACLR

LATCH
Mux4
DataOut1[10]$latch
SEL[3..0]
Addr1[3..0] OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
Mux5 ACLR

SEL[3..0]
OUT LATCH
DATA[15..0]
DataOut2[11]$latch

Mux20 DATAIN

SEL[3..0] LATCH_ENABLE OUT0 DataOut2[15..0]

Addr2[3..0] OUT 1'h0
DATA[15..0] ACLR

LATCH
Mux21
DataOut2[10]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux15
DataOut1[0]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux31
DataOut2[0]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux1
DataOut1[14]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux17
DataOut2[14]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux2
DataOut1[13]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN
LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux18
DataOut2[13]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux3
DataOut1[12]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux19
DataOut2[12]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
DataOut1[3]$latch

DATAIN
LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
DataOut1[4]$latch

DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux10
DataOut1[5]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
Mux11 ACLR

SEL[3..0]
OUT LATCH
DATA[15..0]
DataOut1[15]$latch

Mux0 DATAIN

SEL[3..0] LATCH_ENABLE OUT0

OUT 1'h0
DATA[15..0] ACLR

LATCH
Mux12
DataOut2[15]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
Mux16 ACLR

SEL[3..0]
OUT LATCH
DATA[15..0]
DataOut1[8]$latch

Mux7 DATAIN

SEL[3..0] LATCH_ENABLE OUT0

OUT 1'h0
DATA[15..0] ACLR

LATCH
Mux23
DataOut2[8]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux8
DataOut1[7]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux24
DataOut2[7]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux13
DataOut1[2]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux29
DataOut2[2]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN
LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux14
DataOut1[1]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN
LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux30
DataOut2[1]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux26
DataOut2[5]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux27
DataOut2[4]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux28
DataOut2[3]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux9
DataOut1[6]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN
LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux25
DataOut2[6]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux6
DataOut1[9]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
Mux22
DataOut2[9]$latch
SEL[3..0]
OUT
DATA[15..0] DATAIN

LATCH_ENABLE OUT0
1'h0
ACLR

LATCH
@OUT0_304,OUT0_286,OUT0_268
[1-3]
@OUT0_316,OUT0_298,OUT0_280
registers[0][0] [1-3]

0
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[0][10]
10
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][0]
0
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[0][12]
12
DATAIN

LATCH_ENABLE OUT0 @OUT0_318,OUT0_300,OUT0_282

ACLR [1-3]

@OUT0_317,OUT0_299,OUT0_281
LATCH [1-3]

registers[1][12]
12
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[0][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][11]
11
DATAIN

LATCH_ENABLE OUT0
DataOut1[15] ACLR
Rst_n
R_W LATCH
@OUT0_319,OUT0_301,OUT0_283
registers[0][13] [1-3]

13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][13]
13
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
@OUT0_320,OUT0_302,OUT0_284
[1-3]
registers[0][0]~0 registers[1][14] OUT[15..0]
[1-3]
0 14
DATAIN

1
registers[1][0]~0 LATCH_ENABLE OUT0

ACLR

LATCH
Decoder0

IN[3..0] OUT[15..0]
Addr3[3..0]

@OUT0_307,OUT0_289,OUT0_271
[1-3]

registers[0][14] @OUT0_308,OUT0_290,OUT0_272
[1-3]
14
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[0][1]
1
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][1]
1
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[0][2]
2
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][2]
2
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
@OUT0_309,OUT0_291,OUT0_273
registers[0][3] [1-3]

3
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
@OUT0_310,OUT0_292,OUT0_274
[1-3]

registers[1][3] @OUT0_311,OUT0_293,OUT0_275
[1-3]
3
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[0][4]
4
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[0][5]
5
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][5]
5
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
@OUT0_312,OUT0_294,OUT0_276
registers[0][6] [1-3]

6
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH

registers[1][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][15]
15
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
OUT0
registers[0][15] [1-3]

15 @OUT0_321,OUT0_303,OUT0_285
DATAIN
[1-3]
LATCH_ENABLE OUT0
ACLR

LATCH
@OUT0_314,OUT0_296,OUT0_278
registers[0][8] [1-3]

8
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[1][8]
8
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
@OUT0_315,OUT0_297,OUT0_279
DataIn[15..0] registers[0][9] [1-3]

9 @OUT0_313,OUT0_295,OUT0_277
DATAIN
[1-3]
LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][9]
9
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[1][7]
7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH OUT0
[1-3]
OUT0
registers[0][7] [1-3]

7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
 registers[2][0]
0
DATAIN

LATCH_ENABLE OUT0 @OUT0_304,OUT0_286,OUT0_268

ACLR [1-3]

LATCH
registers[3][0]
0
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][1]
1
DATAIN

LATCH_ENABLE OUT0 @OUT0_307,OUT0_289,OUT0_271

ACLR [1-3]

LATCH
registers[3][1]
1
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][0]
0
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][1]
1
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][0]
0
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][1]
1
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][0]
0
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][1]
1
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][1]
1
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
OUT0
registers[9][0] [2-3]

0
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][0]
0
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[2][12]
12
DATAIN
LATCH_ENABLE OUT0 @OUT0_318,OUT0_300,OUT0_282
ACLR [1-3]

LATCH
registers[3][12]
12
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][12]
12
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][12]
12
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][12]
12
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][12]
12
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][12]
12
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[2][13]
13
DATAIN
LATCH_ENABLE OUT0 @OUT0_319,OUT0_301,OUT0_283
ACLR [1-3]

LATCH
registers[3][13]
13
DATAIN

LATCH_ENABLE OUT0
2
registers[2][0]~0
OUT[15..0] ACLR
[1-3]
LATCH
OUT0 3
registers[3][0]~0
[1-3] registers[4][13]
13
DATAIN
4
registers[4][0]~0
LATCH_ENABLE OUT0

ACLR

15
registers[15][0]~0
LATCH
registers[6][13]
6
registers[6][0]~0 13
DATAIN

LATCH_ENABLE OUT0

7
registers[7][0]~0 ACLR

LATCH
8
registers[8][0]~0 registers[7][13]
13
DATAIN

9
registers[9][0]~0 LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][13]
13
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][13]
13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][2]
2
DATAIN

LATCH_ENABLE OUT0 @OUT0_308,OUT0_290,OUT0_272

ACLR [1-3]

LATCH
registers[3][2]
2
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][2]
2
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][2]
2
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][2]
2
DATAIN

OUT0 LATCH_ENABLE OUT0

[2-3] ACLR

OUT0
[1-3] LATCH
registers[2][10]
OUT0
[1-3] 10
DATAIN
LATCH_ENABLE OUT0 @OUT0_316,OUT0_298,OUT0_280
ACLR [1-3]

LATCH
registers[3][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][10]
10
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][11]
11
DATAIN

LATCH_ENABLE OUT0 @OUT0_317,OUT0_299,OUT0_281

ACLR [1-3]

LATCH
registers[3][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][11]
11
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][11]
11
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][11]
11
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][14]
14
DATAIN

LATCH_ENABLE OUT0 @OUT0_320,OUT0_302,OUT0_284

ACLR [1-3]

LATCH
registers[3][14]
14
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][14]
14
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][14]
14
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][14]
14
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][14]
14
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][14]
14
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][14]
14
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][14]
14
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][4]
4
DATAIN

LATCH_ENABLE OUT0 @OUT0_310,OUT0_292,OUT0_274

ACLR [1-3]

LATCH
registers[3][4]
4
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][4]
4
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][4]
4
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][4]
4
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][5]
5
DATAIN

LATCH_ENABLE OUT0 @OUT0_311,OUT0_293,OUT0_275

ACLR [1-3]

LATCH
registers[3][5]
5
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][5]
5
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][5]
5
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][5]
5
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][5]
5
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][5]
5
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][3]
3
DATAIN

LATCH_ENABLE OUT0 @OUT0_309,OUT0_291,OUT0_273

ACLR [1-3]

LATCH
registers[14][3]
3
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[3][3]
3
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][6]
6
DATAIN

LATCH_ENABLE OUT0 @OUT0_312,OUT0_294,OUT0_276

ACLR [1-3]

LATCH
registers[3][6]
6
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][7]
7
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[3][7]
7
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][8]
8
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[3][8]
8
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[3][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[2][9]
9
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[2][15]
15
DATAIN

LATCH_ENABLE OUT0 @OUT0_321,OUT0_303,OUT0_285

ACLR [1-3]
@OUT0_313,OUT0_295,OUT0_277
LATCH [1-3]
registers[3][15]
@OUT0_314,OUT0_296,OUT0_278
15 [1-3]
DATAIN
LATCH_ENABLE OUT0 @OUT0_315,OUT0_297,OUT0_279
ACLR [1-3]

LATCH
registers[14][6]
6
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][7]
7
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[14][8]
8
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[14][9]
9
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][3]
3
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][6]
6
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][7]
7
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][3]
3
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][3]
3
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][3]
3
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][3]
3
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][3]
3
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][8]
8
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][9]
9
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][7]
7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][8]
8
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][15]
15
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[4][6]
6
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[4][9]
9
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][6]
6
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][7]
7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][6]
6
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][6]
6
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][8]
8
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[7][9]
9
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[7][15]
15
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[6][15]
15
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][15]
15
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[6][7]
7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][7]
7
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[8][8]
8
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[8][9]
9
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][7]
7
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[6][8]
8
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[9][8]
8
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[9][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[6][9]
9
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
OUT0
[2-3]
 registers[10][2]
clk
2
DATAIN
LATCH_ENABLE OUT0 @OUT0_308,OUT0_290,OUT0_272
ACLR [1-3]

LATCH
registers[11][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[10][3]
3
DATAIN

LATCH_ENABLE OUT0 @OUT0_309,OUT0_291,OUT0_273

ACLR [1-3]

LATCH
registers[11][3]
3
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][2]
2
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[12][3]
3
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][2]
2
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][2]
2
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][3]
3
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][3]
3
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[5][10]
10
DATAIN
LATCH_ENABLE OUT0 @OUT0_316,OUT0_298,OUT0_280
ACLR [1-3]

LATCH
registers[10][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][10]
10
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][11]
11
DATAIN

LATCH_ENABLE OUT0 @OUT0_317,OUT0_299,OUT0_281

ACLR [1-3]

LATCH
registers[10][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[11][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[12][11]
11
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[13][11]
11
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[5][14]
14
DATAIN
LATCH_ENABLE OUT0 @OUT0_320,OUT0_302,OUT0_284
ACLR [1-3]

LATCH
registers[10][14]
14
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[11][14]
14
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][14]
14
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][14]
14
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][12]
12
DATAIN

LATCH_ENABLE OUT0 @OUT0_318,OUT0_300,OUT0_282

ACLR [1-3]

LATCH
registers[10][12]
12
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[11][12]
12
DATAIN

LATCH_ENABLE OUT0

ACLR

LATCH
registers[12][12]
12
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[13][12]
12
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][12]
12
DATAIN

OUT0 LATCH_ENABLE OUT0

[2-3] ACLR

LATCH
registers[14][12]
12
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][0]
0
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][0]
0
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
OUT0
registers[11][0] [2-3]

0 @OUT0_304,OUT0_286,OUT0_268
DATAIN
[1-3]
LATCH_ENABLE OUT0

ACLR

LATCH
registers[13][0]
0
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
10
registers[10][0]~0
OUT[15..0] registers[5][0]
[1-3]
0
DATAIN
OUT0 11
registers[11][0]~0
LATCH_ENABLE OUT0
[1-3]
ACLR

12
registers[12][0]~0
LATCH
registers[14][0]
13
registers[13][0]~0 0
DATAIN
LATCH_ENABLE OUT0

14
registers[14][0]~0 ACLR

LATCH
5
registers[5][0]~0 registers[6][0]
0
DATAIN

OUT0 LATCH_ENABLE OUT0

[2-3] ACLR

OUT0
[1-3] LATCH
registers[6][1]
OUT0
[1-3] 1
DATAIN

LATCH_ENABLE OUT0 @OUT0_307,OUT0_289,OUT0_271

ACLR [1-3]

LATCH
registers[5][1]
1
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][1]
1
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][1]
1
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][1]
1
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][1]
1
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[14][1]
1
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][1]
1
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][13]
13
DATAIN
LATCH_ENABLE OUT0 @OUT0_319,OUT0_301,OUT0_283
ACLR [1-3]

LATCH
registers[10][13]
13
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][13]
13
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][13]
13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[13][13]
13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[14][13]
13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][13]
13
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[5][4]
4
DATAIN
LATCH_ENABLE OUT0 @OUT0_310,OUT0_292,OUT0_274
ACLR [1-3]

LATCH
registers[10][4]
4
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[11][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[14][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][4]
4
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[14][5]
5
DATAIN

LATCH_ENABLE OUT0 @OUT0_311,OUT0_293,OUT0_275

ACLR [1-3]

LATCH
registers[14][15]
15
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH
registers[15][5]
5
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[15][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][5]
5
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][5]
5
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][5]
5
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][5]
5
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][5]
5
DATAIN

LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][6]
6
DATAIN

LATCH_ENABLE OUT0 @OUT0_312,OUT0_294,OUT0_276

ACLR [1-3]

LATCH
registers[10][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][6]
6
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][7]
7
DATAIN
LATCH_ENABLE OUT0 @OUT0_313,OUT0_295,OUT0_277
ACLR [1-3]

LATCH
registers[11][7]
7
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[10][8]
8
DATAIN
LATCH_ENABLE OUT0 @OUT0_314,OUT0_296,OUT0_278
ACLR [1-3]

LATCH
registers[10][9]
9
DATAIN
LATCH_ENABLE OUT0 @OUT0_315,OUT0_297,OUT0_279
ACLR [1-3]

@OUT0_321,OUT0_303,OUT0_285
LATCH [1-3]
registers[11][8]
8
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[11][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][7]
7
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][7]
7
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][7]
7
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][8]
8
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[12][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][8]
8
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][8]
8
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[13][15]
15
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][9]
9
DATAIN
LATCH_ENABLE OUT0
ACLR

LATCH
registers[5][15]
15
DATAIN
LATCH_ENABLE OUT0

ACLR

LATCH