COURSE 111 Introduction to Digital Design

Assignment #: 5 Lab6

Section #: 16

Submitted by:
1. Ahmed Hafez El-Sayed, V23010322
2. Ahmed Gaber Mohamed, V23010611
3. Ahmed Mohamed Qorany, V23010564
4. Mostafa Khaled Fouad, V23010279

Submitted to TA: Mohamed Elshafey

Date: 3/11/2023
sequence detector for the non-overlapping bit
stream of “1011”

Our code:
We separated our code into
individual blocks to make it easier to
read.

This is our top-level code and we call

all blocks in it.
Here we define our 16*32
ROM with 16bit word adders
Then we load data in it with
external file.

File des�na�on

And now we define the parallel

input serial output module.
It receives data from ROM with
start signal.
And begin to convert data a�er
start signal is removed and with
posi�ve edge of clock signal.
 This is the finite state machine
that we used to check if the serial
data matches the sequence of
1011.

If this sequence appears FSM

output will send signal at output
that sequence is detected.

This counter counts how many

�mes the FSM detected the
sequence of 1011 in the data of
desired address.

Then a simple checker checks if counted number is

odd or even if odd the output is high.
RTL of our design:

The Code of our Test Bench:

the idea of our testbench we call address of 00000

and 00001, and we know that the data in address
00000 has the sequence of 1011 in it 3 �mes so the
odd checker value should be 1, and address 00001
has the sequence of 1011 in it 2 �mes so the odd
checker value should be 0.
The Simula�on:

First, we reset the whole module

Then a start signal is sent to load data at address of 00000 from ROM to PISO.
At the end of the opera�on the odd checker = 1, as we expected

then we reset the module and load data of address 00001 to PISO
At the end of the opera�on the odd checker = 0, as we expected too.