Namal University Mianwali

Department of Electrical Engineering

Digital Logic Design

EE-251L

Lab # 5 Manual

Binary Adders
Name

Roll No

Marks Obtained

Date Performed

Instructor: Ms. Naureen Shaukat

Lab Engineer: Engr. Maria Rehman

Version 1.0-Prepared by Dr. Syed Asad Alam

Version 2.0-Dr. Majid Ali
Version 3.0-Engr Maria Rehman
Fall 2023 DLD Lab 05 Version 3.0

1. Objectives
The objective of this lab is to construct a basic n-bit binary adder using logic gates.
.
2. Learning Outcomes
This lab satisfies the following learning outcomes of the course:
• CLO1: Build digital circuits for open ended, complex and real- world applications.
• CLO3: Writing technical and comprehensive lab report

3. Equipment & Components

• Trainer board
• Various gate ICs

4. Instructions
• There will be no concept of make-up labs. If missed, the lab may be performed later for practice and
knowledge required for the coming labs on your own and will be graded for partial marks unless there
is any valid reason.
• Plagiarism cases would be sent to the student disciplinary committee (SDC) without any prior
warnings.

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Fall 2023 DLD Lab 05 Version 3.0

5. Introduction
To build a binary adder of any size it is sufficient to build a unit, which can add two single bits. Such a
circuit is not very complex as there are only three calculations that needs to be performed, i.e.

0+0=0
0+1=1
1 + 1 = 10

In the third case we encounter a slight complication: A single bit of output does not suffice to represent the
sum of 1 and 1, and we must “carry” a 1 to the next place. A 1-bit adder, therefore, must accept two single-
bits of input (the bits to be added) and generate two bits of output. These two bits can be designated the
SUM bit and the CARRY bit.

5.1. Half-Adder
Half Adder is a combinational logic circuit that generates the sum of two single-bit binary numbers. The
logic circuit has two inputs A and B and two outputs i.e., SUM and CARRY abbreviated as S and C
respectively.

5.2. Full-Adder
Half-adder only has only two inputs. However, even the addition of two single-bit numbers may generate
a carry. This implies that the circuit, which is going to perform addition on the next higher bits, must take
into account the carry from the previous stage. Thus, in order to build n-bit adder, we require a modification
in the half-adder circuit that can accept three inputs rather than two, i.e., two bits to be added and the carry
from the previous stage. Such a circuit is called a full-Adder.

5.3. N-Bit Adder

With the ability to design a full-adder, one can construct adder circuits for adding two numbers of any sizes,
e.g., 4-bit adder (which adds two 4-bit numbers), 8-bit adder and so on. Figure 1 shows the block diagram
of a 3-bit adder. The first full adder for bit 0 can be replaced by a half-adder (Think about the reason).
Specifically, the figure shows first two stages of the design, i.e., a half-adder to add the least significant
bits, cascaded to a full-adder for the addition of next significant bits. Thus, by cascading required number
of full-adders with a half-adder for the least significant bit, it is quite straightforward to construct adder for
any number of bits.

Figure 1: Three-bit adder using three full-adders.

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Fall 2023 DLD Lab 05 Version 3.0

6. Procedure
6.1. Task 1: Half-Adder
1. Create the truth table for the SUM (S) and the CARRY (Cout) bit. The inputs are A and B.

Inputs Outputs
A B S Cout

2. Read the Boolean equations from the truth table.

3. Simplify the Boolean equations for S and Cout using K-map.

4. Draw the logic diagrams for the simplified Boolean equations S and Cout using basic gates.

5. Convert the logic diagrams for S to a XOR logic and draw the circuit diagram.

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Fall 2023 DLD Lab 05 Version 3.0

6. Build the circuits and test.

Inputs Outputs
A B S Cout

7. Convert the logic diagrams for S and Cout to a NAND logic.

8. Build the circuits and test.

Inputs Outputs
A B S Cout

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Fall 2023 DLD Lab 05 Version 3.0

6.2. Task 2: Full-Adder

1. Create the truth table for the SUM (S) and the CARRY (Cout) bit. The inputs are A, B and Cin.

Inputs Output
Cin A B S Cout

2. Read the Boolean equations from the truth table. It should be in SOP form.

3. Simplify the Boolean equations for S and Cout using K-map.

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Fall 2023 DLD Lab 05 Version 3.0

4. Draw the logic diagrams for the simplified Boolean equations S and Cout using basic gates.

5. Convert the logic diagrams to a XOR logic and draw the circuit diagram.

6. Build the circuits and test.

Inputs Output
Cin A B S Cout

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Fall 2023 DLD Lab 05 Version 3.0

6.3. Task 3: 3–bit Adder

Using a full-adder construct a 3–bit adder on the trainer board, similar to the one shown in Fig. 1
and verify the output.

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Fall 2023 DLD Lab 05 Version 3.0

7. Observations and Conclusion

8. Submissions
You need to submit the hard copy of the manual.
References
[1]. Digital Design: With an Introduction to the Verilog HDL, by M. Morris Mano and Michael D.
Ciletti, 5th Edition, Pearson, 2013.

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 Marking Rubric

Excellent Good Average Poor

Performance Marks
9-10 7-8 5-6 4-0

Successfully completed in Successfully performed Had difficulty in

Not completed about
Circuit Implementation time with complete but not with a clear completing the
half of the tasks
understanding understanding tasks

More than half of

Most correct answers,
Complete, clear, and the answers are Less than half of the
Understanding/ viva and confident
correct answers correct but not answers are incorrect
confident

Not very clear and

Not very clear and
Clean and clear without Clean and clear but clean, and most of
clean and partial
Report any match with fellow slight overlap with other the content
overlap with fellow
students students overlapping with
students
fellow students

• CLO1: Build digital circuits for open ended, complex and real- world applications.
• CLO3: Writing technical and comprehensive lab report