Roll No. :-..............................

2021013

B. E. II Examination Nov-Dec 2021

Information Technology
ITR3G1: Computer Organization and Architecture

Duration: 3 Hrs Max. Marks: 60

Total No. of questions: 05

Note: All questions are compulsory. Attempt any two parts from each question. Make
suitable assumptions if necessary. Answer should be to the point.

Q1. A. Give historical perspective of computers in terms of generations and evolution of 06

performance.

B. Define the following: 06

1. Desktop Computer 2. Server 3. Data Center
4. Super Computer 5. Embedded Computer 6. Petabyte

C. Write the following rules for arithmetic operations on floating-point numbers: 06

1. Add/Subtract Rule 2. Multiply Rule 3. Divide Rule

Q2. A. Explain caches on the processor chip. 06

B. How flash memory is different from EEPROM and flash drives are different 06
from hard disk drives?

C. Consider a computer that has a cache holds 8-word blocks and a typical DRAM 06
main memory. 17 cycles are needed to load a block into the cache. Assume that
30 percent of the instruction in a typical program performs a read or a write
operation. Assume that hit rate in the cache are 0.95 for instructions and 0.9 for
data. 1 clock cycle is needed to access information in the cache. Let us further
assume that the miss penalty is the same for both read and write accesses.
How effective this cache is compared to an ideal cache?

Q3. A. For a given CPU, the first machine cycle M1 always consist of 4-states, and the 06
remaining machine cycles consist either of 3 or 4 states. An instruction cycle
consists of a minimum of 2 and a maximum of 5 machine cycles. If the CPU’s
clock rate is 50 MHz and every memory access introduces one wait state. Then
calculate:

A).The shortest instruction execution time,

B).The longest instruction execution time,

B. Design a firmware architecture for a digital component that have four states, 06
three inputs (J, K and Clock) and two outputs (ZERO and ONE).

C. Draw and explain single-bus organization of the datapath inside a processor. 06

1
Q4 A. List three broad classifications of external, or peripheral, devices. 06
B. When a device interrupt occurs, how does the processor determine which device 06
issued the interrupt?

C. What is the difference between programmed-driven I/O and interrupt-driven 06

I/O? Give one advantage and one disadvantage of each.

Q5. A. Describe the classification of pipeline processor. 06

B. Give the principle of linear pipelining with the basic structure of a linear pipeline 06
processor and the space time diagram.

C. The diagram shown below is a reservation table for a unifunctional pipeline 06

system. Identify a collision vector and draw a state diagram for this pipeline
system. Also find out minimum average latency for the given pipeline system.

t0 t1 t2 t3 t4 t5 t6 t7 t8
1 X X
2 X X X
3 X
4 X X
5 X X

2
 Mid Semester Test-III, November-2021
BE III Semester, Information Technology (Section: A and B)
ITR3G1: Computer Organization and Architecture

Max. Marks: 20
Total No. of questions: 05

Note: All questions are compulsory. Make suitable assumptions if necessary. Answer should
be to the point.

Q.1 When a device interrupt occurs, How does the processor determine which device 05
issued the interrupt?

Q.2 What is the difference between programmed-driven I/O and interrupt-driven 05

I/O? Give one advantage and one disadvantage of each.

Q.3 Give the principle of linear pipelining with the basic structure of a linear pipeline 05
processor and the space time diagram.

Q.4 Derive the Speedup, Efficiency and Throughput for a k-stage linear pipeline 05
processor.
 Mid Semester Test – II (Oct-2021)
B. E. II Year (IT-A, IT-B)
Subject – Computer Organization and Architecture (ITR3G1)

Duration: 70 Min Max Marks: 20

Note: Attempt all questions and answer should be to the point.

Q.1 How many total bits are required for a direct-mapped cache with 16 KB of data and 4- 5
word blocks, assuming a 32-bit address?

Q.2 Design a memory hierarchy for the system. Show the typical size and latency at 5
various levels of the hierarchy. What’s the relationship between cache size and its
access latency?

Q.3 Show how to build a datapath for the operational portion of the memory-reference and 5
arithmetic-logical instructions that uses a single register file and a single ALU to
handle both types of instructions, adding any necessary multiplexors.

Q.4 Explain the following: State element, Asserted, Deasserted, Clocking Methodology, 5
and Edge-triggered clocking.
 Mid Semester Test – I (Sep-2021)
B. E. II Year (IT-A, IT-B)
Subject – Computer Organization and Architecture (ITR3G1)

Duration: 70 Min Max Marks: 20

Note: Attempt all questions and answer should be to the point.

Q.1 Explain the processor clock. Also derive the basic performance equation for the 5
processor time T.

Q.2 List the steps needed to execute the machine instruction: 5

Add LOCA, R0;

Q.3 Criticize the following statement: “Using a faster processor chip results in a 5
corresponding increase in performance of a computer even if the main memory speed
remains the same.”

Q.4 Give a short sequence of machine instructions for the task: “Add the contents of 5
memory A to those of location B, and place the answer in location C”.
Instructions: Load LOC, Ri and Store Ri, LOC
Are the only instructions available to transfer data between the memory and general
purpose register Ri. Do not destroy the contents of either location A or B.