Unit 1 Basics of Microcontroller & Intel 51 family architecture [08]

External Memory Interface.

a) External RAM interface to 8051
b) External ROM interface to 8051
c) External RAM as well as external ROM interface to 8051

Reference Books:
Recommended books: • 8051 microcontroller and Embedded system using assembly and C
: Mazidi, Mazidi and McKinley, Pearson publications

• The 8051 microcontroller – Architecture, programming and applications: K.Uma Rao and
Andhe Pallavi, Pearson publications. 1
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Interfacing External Memory with 8051
We have seen that a typical 8051 Microcontroller
has 4KB of ROM and 128 Bytes of RAM
The designer of an 8051 Microcontroller based
system is not limited to the internal RAM and ROM
present in the 8051 Microcontroller. There is a
provision of connecting both external RAM and
ROM i.e. Data Memory and Program memory.

A maximum of 64KB of Program Memory (ROM) and Data

Memory (RAM) each can be interface with the 8051
Microcontroller.
Now we will see block diagram of interfacing External RAM
and External ROM with the 8051 Microcontroller.

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 8051 Memory

/EA: PIN 31
1./EA is the External Access pin of 8051 microcontrollers.
2.The /EA pin is connected to GND to indicate that the code is stored completely in the external
program memory (64kB).
3.To use both on-chip ROM (4kB) and external ROM (60kB) together, the /EA pin is connected to
the +5V VCC supply.
4.It turns ON when a low pulse/signalS.Y.B.Sc(CS)
is provided.Electronics paper1
5./EA pin must be disable when 8051Microcontroller
is interfaced
Unit1with external RAM, so it is connected to3+5Vcc
by Gambhire
Madhavi
External Access Pin (/EA Pin) must be pulled HIGH i.e. when
the /EA Pin is connected to +Vcc, the CPU first fetches
instructions from the Internal Program Memory (4KB)in the
address range of 000H to 0FFFH .
and if the memory addresses exceed the limit, then the
instructions are fetched from the external ROM(60KB) in
the address range of 1000H to FFFFH.

S.Y.B.Sc(CS) Electronics paper1

Microcontroller Unit1 by Gambhire 4
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There is another way to fetch the instructions: ignore the
Internal ROM and fetch all the instructions only from the
External Program Memory (External ROM). For this
scenario, the /EA Pin must be connected to GND. In this
case, the memory addresses of the external ROM will be
from 0000H to FFFFH.

S.Y.B.Sc(CS) Electronics paper1

Microcontroller Unit1 by Gambhire 5
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 Significance of /PSEN in external memory interface : PIN 29
1.This is an output pin.
2./PSEN stands for “program store enable.”
3.Connect this /PSEN pin to the /OE pin of the ROM to enable access to data.
4.It is an active low output signal.
5.It is used to enable/read external program memory (ROM).
1. When [/PSEN] = 0, then external program memory becomes enabled, and
microcontroller reads the content of external memory location.
2. When [/PSEN] = 1, then the data cannot be read from any external program
memory, then the microcontroller has to depend on the on-chip ROM to store the
program code.

Significance of Port 0 and Port 2 in external memory interface :

1.These ports provide a 16-bit address to access External Memory.
2.P0: Multiplexed lower order address/data bus: AD0-AD7.
3.P2: Higher-order address bus: A8-A15.
4.When ALE = 0, P0 facilitates data path
5.When ALE = 1, P0 facilitates address path
6.We can address 2^16 = 64Kb memory (i.e. 64Kb code memory and 64Kb data memory) by
these 16 address lines from A0 to A15.
7.To extract the address from the P0 pins, we connect P0 to a 74LS373 and use the ALE pin
to latch the address.
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 Significance of ALE in
external memory interface
• Port 0 acts as a multiplexed address/data bus. Sending the
low byte of the program counter (PCL) as an address.
• Port 2 sends the high byte of program counter (PCH) directly
to the external memory.
• ALE is used to demultiplexing address/data on Port 0.
• The signal ALE (ALE=1) operates as in the 8051 to allow an
external latch to store address from PCL byte from Port 0
• When ALE = 0, Port 0 switches function and becomes the data
bus receiving the data byte from memory.

Status at ALE (active high) P0 carries

1 = logic high A0-A7 = Lower byte of address bus
0 = logic low D0-D7 = 8-bit bidirectional data
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bus
 External ROM External RAM
/EA GND=> External ROM +Vcc
+Vcc=> internal ROM
+External ROM
Read strobe /PSEN /RD
Write Strobe --------- /WR
Data Bus carries from Instructions Data

From Size of memory find out no. of locations and no. of data bits

From no. of locations , find out no. of address bits

For addressing find out of requirement of P0 bits and P2 bits

ALE to +level triggered CLK of Octal D-Latch

Connect P0 to D input of external octal latch to latch lower byte of

address on it and 8-bit data bits to data bus of external memory

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IC 74LS373 Octal D Latch
Where to connect
CLK =?
Inputs=?
Outputs=?

Truth table:
/OC G (CLK) D (input) Output comment
L H H H Output=input
L L
L L x Q Previous Output
=No Change
H x x Z High impedance
R=∞

• 74LS373 comprises eight D flip flops.

• Whenever a clock pulse is applied, the input is passed on to the output as
it is if the ALE pin is high.
• When the ALE pin is low, then the output is latched in the IC.
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 Access External Program Memory
/EA=>GND => To access only external ROM
/PSEN => /OE(Output Enable) selecting ROM when /PSEN goes low
ALE=1 => Port 0 gives lower byte of address which is stored in external latch.
Port 2 gives higher byte of address
All 16 bit of address is received by address pins of 64KB external ROM.
ALE=0 => Port 0 is ready to receive data/instruction from external ROM

D0-D7

PCL
743
73 A0-A7
clk

A8-A15

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Access External Program Memory

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Access External Program Memory

Circuit diagram to interface external program ROM with 8051

Size of external ROM is 8K x 8 =>213 locations ,
8 bits/location=> address bus= 13 =A0 to A12
1.Step 1: Connect /EA pin to ground to access only external ROM.
2.Step 2: Connect the /PSEN to the /CE and/ OE = => Active low chip select and active low output
Enable.
3.Step 3: Then, Port 2 (P2.0 – P2.7) to A8 – A12 pins of ext. ROM.
4.Step 4: Connect ALE to G of 74LS373 latch to enable it.
5.Step 5: Next, connect the /OC of 74LS373 to GND.
6.Step 6: Connect Port 0 (P0.0 – P0.7), which consists of both address and data multiplexed into Port 0 to
1D – 8D pins of 74LS373 latch to demultiplex it and 1Q – 8Q of the latch to A0 – A7 of ext. ROM.
7.Step 7: Connect Port 0 (P0.0 – P0.7) to D0 – D7 of the ext. ROM.
8.Step 8: VPP of ext. ROM to VCC. 12
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Code to interface external program ROM with 8051

ORG 0000H
MOV DPTR, #4000H ; Load DPTR with the location address of ext.ROM where data is stored
MOV R0, #40H ; Load R0 with the int RAM address where you want to save the data
rep: MOV A, #00H ; Clear accumulator
MOVC A, @A+DPTR ; Syntax to move data from ext. ROM to accumulator
MOV @R0, A ; Copy the value of accumulator in location pointed by R0
INC R0 ; Inc R0 to point to next int RAM location
INC DPTR ; Inc DPTR to point to next ext. ROM location
CJNE A, #00H, rep ; Repeat this process until 0 is received from the DPTR
stay:SJMP stay ; Stay here
END

; Let’s say that the data present at 4000H is

ORG 4000H
DB 1H, 2H, 0AH, 0F2H, 30H, 5CH, 2AH, 01H, 00H, FFH, 0
; Here 0 is the stop bit that we’re assuming

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 Access External Data Memory
/EA =+Vcc => Internal ROM is enabled.
No use of /PSEN for accessing external data memory.

D0-D7

A0-A7

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+Vcc

/EA

P2.5

1.Step 1: Connect /RD to /OE of ext. RAM. Access External Data Memory
2.Step 2: Connect /WR to /WE of ext. RAM.
3.Step 3: Connect output of NAND gate to /CE of external RAM, where the input to NAND
gate are address lines A15, A14, . We’ve given A15=1,A14=0 to these lines to select the
external RAM chip.
Size No. of Locations Address Data
8KB=8Kx8 𝟐𝟏𝟑 13=A0 to A12 8 = D0 to D7
A0-A7=>P0
A8-A12=>P2.0-P2.5
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 Code to interface external RAM with 8051 : write operation

ORG 0000H
RAMLOC EQU 6000H ; External RAM location = 6000H
COUNT EQU 150 ; Variable count = 150d
MOV DPTR, #RAMLOC ; Mov DPTR to point to ext. RAM location
MOV R3, #COUNT ; Number of bytes of data
rep: MOV A, P1 ; Copy status of P2 into acc
MOVX @DPTR, A ; Copy the content of acc to the ext. RAM
ACALL DELAY ; call a delay before repeating the process
INC DPTR ; Inc DPTR to point to next location
DJNZ R3, rep ; Repeat this until all the bytes of data are sent
stay: SJMP stay ; Stay here forever
END

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Size No. of Address Data
Locations
1KB=1Kx8 210 10 =A0 to A9 8 = D0 to D7
A0-A7=>P0
A8-A9=>P2.0,P2.1
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Accessing External Memory

ROM RAM
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Access External Program Memory (ROM) and
External Data Memory(RAM)

Size No. of Address Data

Locations
64KB=64Kx8 216 16 =A0 to A15 8 = D0 to D7
A0-A7=>P0
A8-A15=>P2
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 Accessing External Memory

WE

Size No. of Locations Address Data

8KB=64Kx8 213 13 =A0 to A12 8 = D0 to D7
Ao-A7=>P0
A8-A12=>P2.0-P2.4

RAM is selected when A13=A14=A15=0, as /CE= /(1.1.1.) = 0

RAM delivers data when /RD=0 => /OE=0
ROM is selected when /PSEN=0 which makes /CE and /OE=0 and delivers instruction on D0-D720
S.Y.B.Sc(CS) ELC2301 Microcontroller Unit1 :Gambhire Madhavi
 Interfacing external program ROM, data ROM and external RAM with the 8051

Step 1: Calculate the number of address lines required to access 16KB of data, that is 214
= 16KB. Here, we require 14 address lines A0 – A13.
Step 2: Connect /EA pin to ground . Connect the /PSEN to the /CE and/ OE of ext. ROM
==> Active low chip select and active low output Enable.
Step 3: Then, Port 2 (P2.0 – P2.7) to A8 – A12 pins of ext. ROM and ext. RAM.
Step 4: Connect ALE to G of 74LS373 latch to enable it.
Step 5: Next, connect the /OC of 74LS373 to GND.
Step 6: Connect Port 0 (P0.0 – P0.7), which consists of both address and data
multiplexed into Port 0 to 1D – 8D pins of 74LS373 latch to demultiplex it and 1Q – 8Q
of the latch to A0 – A7 of ext. ROM and ext. RAM.
Step 7: Connect Port 0 (P0.0 – P0.7) to D0 – D7 of the ext. ROM and ext. RAM.
Step 8: VPP of ext. ROM to VCC.
Step 9: We connect external RAM program and Ext. ROM, for that we can use an NAND
gate to output logic zero to /CE of external ROM and external RAM when A13,A14,A15
are made low. 0output of NAND=/(/A13./A14./A15)=/CE= /(1.1.1) =0
Step 10: To interface the external RAM, we connect both /RD and /WR to /OE and /WE
respectively of external RAM.

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Questions:
1. For external Program memory access, give the significance
of /EA pin of 8051.
2. For external Program memory access, give the significance
of /PSEN pin of 8051.
3. To interface 1KBbyte external RAM memory , how many
address lines are required and which port pins are required
for addressing it?
4. Calculate number of address lines to interface 256bytes
external ROM to 8051. Which port pins are required as
address pins ?
5. Draw the block diagram to interface 64KB ROM to 8051.
6. Draw the block diagram to interface 4KB RAM to 8051.
7. Draw the block diagram to interface 64KB ROM and 4KB
RAM to 8051.
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Test your Knowledge:
/EA= Active__________ pin
ALE=Active____________ pin
ALE=1 then P0= ______________
ALE =0 then P0=______________
/EA= ___________ for interfacing only external ROM
/EA=+Vcc for _____________ and ______________
IC 74373 has ________ number of _____ flip-flops.

Size No.Of No. of address P0 and P2 pins

Locations Lines
8KB
16KB
32 KB
64KB

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https://technobyte.org/8051-external-
memory-interfacing-ram-rom/

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