15-09-2023

CS 207 Computer Organization and Architecture (COA)

Sequential Circuits
• Counters
• Problems and Discussion

Counters
• A counter is a register capable of incrementing and/or decrementing its
contents.
Q(t+1) ← Q(t) plus n
Q(t+1) ← Q(t) minus n
• Counter with 3 FFs will have a maximum count of 23 = 8
counting states and would be called a MOD-8 counter. The maximum
binary number that can be counted by the counter is 2n–1 giving a
maximum count of (111)2 = 23–1 = 710.
• There are two types of counters based on the flip-flops that are connected
in synchronous or not.
• Asynchronous counters
• Synchronous counters

1
 15-09-2023

Example: 3-bit binary counter

Example: 3-bit binary up/down counter

2
 15-09-2023

Example: Binary Mod 6 counter

Counters
• If the flip-flops do not receive the same clock signal, then that
counter is called as Asynchronous counter (Ripple counter).
The output of system clock is applied as clock signal only to
first flip-flop. The remaining flip-flops receive the clock signal
from output of its previous stage flip-flop. Hence, the outputs
of all flip-flops do not change at the same time.
• If all the flip-flops receive the same clock signal, then that
counter is called as Synchronous counter. Hence, the outputs
of all flip-flops change at the same time.

3
 15-09-2023

ASYNCHRONOUS (RIPPLE) COUNTER

• It has 16 distinctly different states
• (0000 through 1111).
• Thus, it is a MOD-16 ripple counter.
• MOD number is equal to the number of
states that the counter goes through in
each complete cycle before it recycles
back to its starting state.
• The MOD number can be increased
simply by adding more FFs to the
counter.
• MOD number = 2N
where N is the number of FFs
connected in the arrangement.

ASYNCHRONOUS (RIPPLE)
COUNTER Using T Flip Flops

4
 15-09-2023

BCD Ripple Counter

Also termed as Decade Counter or MOD-10 Counter.

BCD Ripple Counter

5
 15-09-2023

Synchronous Counters
• Synchronous 3 bit binary up counter.
• Qi toggles on every clock cycle where Qj = 1, for i > j ≥ 0.

Synchronous Counter
Q1Q0 00 01 11 10
Design of a 3-bit Binary Up Counter Q2
0 1 T2 = Q1Q0
Present State Next State FF Inputs 1 1
Q2 Q1 Q0 Q2+ Q1+ Q0+ T2 T1 T0
Q1Q0
0 0 0 0 0 1 0 0 1 Q2 00 01 11 10
0 0 1 0 1 0 0 1 1 0 1 1
T1= Q0
0 1 0 0 1 1 0 0 1 1 1 1
0 1 1 1 0 0 1 1 1
Q1Q0
1 0 0 1 0 1 0 0 1 Q2 00 01 11 10
1 0 1 1 1 0 0 1 1 0 1 1 1 1 T0 = 1
1 1 0 1 1 1 0 0 1 1 1 1 1 1
1 1 1 0 0 0 1 1 1

6
 15-09-2023

Design of a Binary Up Counter

• The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops change
synchronously. The T inputs of first, second and third flip-flops are 1, Q0 & Q1Q0
respectively.
• The output of first T flip-flop toggles for every negative edge of clock signal. The output of
second T flip-flop toggles for every negative edge of clock signal if Q0 is 1. The output of
third T flip-flop toggles for every negative edge of clock signal if both Q0 & Q1 are 1.

3-bit Synchronous Binary Up-Counter using T-FFs

Design of a Binary Down-Counter

3-bit Synchronous Down Counter

Present State Next State FF Inputs 1

Q2 Q1 Q0 Q2+ Q1+ Q0+ T2 T1 T0 T2 = Q1’Q0’
1
0 0 0 1 1 1 1 1 1
1 1 1 1 1 0 0 0 1
1 1 0 1 0 1 0 1 1 1 1
1 0 1 1 0 0 0 0 1 T1 = Q0’
1 1
1 0 0 0 1 1 1 1 1
0 1 1 0 1 0 0 0 1
0 1 0 0 0 1 0 1 1 1 1 1 1
T0 = 1
0 0 1 0 0 0 0 0 1 1 1 1 1

7
 15-09-2023

Design of a Binary Down Counter

• The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-
input AND gate. All these flip-flops are negative edge triggered and the outputs of
flip-flops change synchronously. The T inputs of first, second and third flip-flops
are 1, Q0′ & Q1′Q0′ respectively.
• The output of first T flip-flop toggles for every negative edge of clock signal. The
output of second T flip-flop toggles for every negative edge of clock signal if Q0′ is
1. The output of third T flip-flop toggles for every negative edge of clock signal if
both Q1′ & Q0′ are 1.

3-bit Synchronous
Down Counter

Design of a Binary Up-Down Counter

A single sequential circuit, which works for both up and down counter.

8
 15-09-2023

Design of a Binary Up-Down Counter

QBQA
MQC
Present Next FF Input
1
M QC QB QA QC+ QB+ QA+ TC TB TA
0 0 0 0 0 0 1 0 0 1 1
0 0 0 1 0 1 0 0 1 1

0 0 1 0 0 1 1 0 0 1
1
0 0 1 1 1 0 0 1 1 1 1
0 1 0 0 1 0 1 0 0 1

0 1 0 1 1 1 0 0 1 1 QBQA TC = M’QBQA+MQB’QA’
0 1 1 0 1 1 1 0 0 1
M QC
0 1 1 1 0 0 0 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1
1 1 1 1 1 1 0 0 0 1
1 1
1 1 1 0 1 0 1 0 1 1 1 1
1 1 0 1 1 0 0 0 0 1
1 1 0 0 0 1 1 1 1 1 1 1
1 0 1 1 0 1 0 0 0 1

1 0 1 0 0 0 1 0 1 1 TB = M’QA+MQA’
1 0 0 1 0 0 0 0 0 1

Design of a Binary Up-Down Counter

9
 15-09-2023

Ring Counter

Johnson Counter (Twisted-ring counter)

10