IC fabrication&design

process (EE3113)
Part 1: FAB
HOANG Trang
hoangtrang@hcmut.edu.vn
Main reference:
Jaeger R C –Introduction to Microelectronic Fabrication (Pearson Higher
Education, 2001) ISBN 0201444941
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 1
Motivation, Introduction
Video:
Microelectronic fabrication !!!???? WHY
from sand to chip

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 2

Historical Trends
Silicon Wafer Size
• Early Wafers - 1, 1.5, 2
Inch Diameters
• Wafer Size has
Increased Steadily
• 200 mm (8”) Wafers in
Production
• 300 mm (12”) (>
3B$/Fab. Intel: 6B$)
• 450 mm Planned and
coming on line now

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 3

 Larger Wafers
Lower Die Cost

• Cost to Process a Wafer is

Relatively Fixed for a Given
Process
• Larger Wafer →Lower Cost/Die

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 4

Historical Trends
Memory Density (Bits/Chip)

• Moore’s Law - Exponential

Increase in Chip Complexity

• ISSCC Research Benchmarks

•1967 - 64 bit Memory
•1984 - 1Mb Memory
•1995 - First 1 Gb Memory

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 5

Historical Trends
Microprocessor Complexity (Trans./Chip)

• ISSCC Benchmarks
•1971 - 2000 Transistors
•1988 - 1M Transistors
•1998 - 100M Transistors

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 6

Historical Trends
Memory Feature Size (mm)
• Feature Size Decreases by 2X
approximately every 5 years
• Each New Process Generation
Doubles Density - Reduction
of Feature Size by 0.707
• The Original Nanotechnology!
• Feature size now 22-28 nm
• Transistors Operate Normally
to at Least 6 nm

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 7

Semiconductor Industry
Roadmap - ITRS

Each new process generation doubles chip density by scaling feature size by 0.7.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 8

 NMOS Transistor
Top View and Cross-Section
• N-Channel Metal-Oxide
Semiconductor
Transistor
Conducting Channel
• n- and p-type
Region semiconductor regions
• Thick and thin oxides
• Etching Openings
• Polysilicon gate
• Metal (Al)
Interconnections

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 9

Basic NMOS Process
Key Steps

•Oxidation
•Photolithography
•Implantation
•Diffusion
•Etching
•Film Deposition

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 10

CMOS Technology
N-Well Technology Cross-Section
• Complementary Metal-
Oxidation Oxide Semiconductor
Technology
Photolithography
• Dominant Technology
Implantation in Integrated Circuits
Today!
Diffusion
• Requires both NMOS
Etching and PMOS Transistors

Film Deposition

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 11

 Bipolar Transistor
Top View and Cross-Section
• Bipolar Junction Transistor
(BJT)
• Standard Buried Collector
Process (SBC)
Active • n- and p-type
Transistor semiconductor regions
Region
• Thick and thin oxides
• Etching Openings
• Metal (Al) Interconnections

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 12

SBC Process
Key Steps

•Oxidation
•Photolithography
•Implantation
•Diffusion
•Etching
•Film Deposition

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 13

 Photolithographic
Process

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 14

 quang khắc

Photolithographic Process
(a) Substrate covered with silicon
dioxide barrier layer
(b) Positive photoresist (light-
sensitive material) applied to
wafer surface (machine:
Spinner)
(c) Mask in close proximity to
surface
(d) Substrate following resist
exposure and development
(e) Substrate after etching of oxide
layer (etch => remove)
(f) Oxide barrier on surface after
resist removal (resist #
photoresist)
(g) View of substrate with silicon
dioxide pattern on the surface

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 15

Photolithographic Process
Si02 qtrong và phổ biến vì nó là lớp bảo vệ

mask alignment: căn chỉnh mask

• Each mask step requires

many individual process
steps (=> gds file)

• Number of masks is a
common measure of overall
process complexity

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 16

Photolithographic Process
• Soft-Baking
Soft-baking is the step during which almost all of the solvents
are removed from the photoresist coating.
Soft-baking plays a very critical role in photo-imaging. The
photoresist coatings become photosensitive, or imageable,
only after softbaking.
Oversoft-baking will degrade the photosensitivity of resists
by either reducing the developer solubility or actually
destroying a portion of the sensitizer.
Undersoft-baking will prevent light from reaching the
sensitizer. Positive resists are incompletely exposed if
considerable solvent remains in the coating. This undersoft-
baked positive resists is then readily attacked by the
developer in both exposed and unexposed areas, causing
less etching resistance.
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 17
Photolithographic Process
• Hard-Baking

Hard-baking is the final step in the

photolithographic process. This step is
necessary in order to harden the
photoresist and improve adhesion of the
photoresist to the wafer surface.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 18

Photolithographic Process
• Development
At low-exposure energies, the negative resist remains
completely soluble in the developer solution. As the
exposure is increased above a threshold energy Et, more of
the resist film remains after development. At exposures two
or three times the threshold energy, very little of the resist
film is dissolved. For positive resists, the resist solubility in
its developer is finite even at zero-exposure energy. The
solubility gradually increases until, at some threshold, it
becomes completely soluble. These curves are affected by
all the resist processing variables: initial resist thickness,
prebake conditions, developer chemistry, developing time,
and others.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 19

Photomasks
CAD Layout

• Composite drawing of the

masks for a simple integrated
circuit using a four-mask
process

• Drawn with computer layout

system

• Complex state-of-the-art
CMOS processes may use 25
masks or more

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 20

Photo Masks
10X Reticle

• Example of 10X reticle for the

metal mask - this particular mask
is ten times final size (10 mm
minimum feature size - huge!)

• Used in step-and-repeat
operation

• One mask for each lithography

level in process

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 21

Photomasks
Final Mask

• Mask after reduction and

“step-and-repeat”
operation

• Final size emulsion mask

with 400 copies of the
metal level for the
integrated circuit

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 22

ITRS Lithography Projections

Table 2.5 -- ITRS Lithography Projections

Year 2001 2003 2005 2008 2011 2014

Dense Line Half-Pitch (nm) 150 120 100 70 50 35

Worst Case Alignment Tolerance 52 42 35 25 20 15

Mean + 3  (nm)

Minimum Feature Size F (nm) 100 80 65 45 30 20

Microprocessor Gate Width

Critical Dimension Control (nm) 9 8 6 4 3 2

Mean + 3  - Post Etching

Equivalent Oxide Thickness (nm) 1.5 - 1.9 1.5 - 1.9 1.0 - 1.5 0.8 - 1.2 0.6 - 0.8 0.5 - 0.6

Lithography Technology Options 248 nm DUV 248 nm + PSM 193 nm + PSM 157 nm +PSM EUV EUV
193 nm DUV 157 nm E-beam projection E-beam projection E-beam projection
E-beam projection E-beam direct write E-beam direct write E-beam direct write
Proximity x-ray EUV Ion Projection Ion Projection
Ion Projection Ion Projection Innovation
Proximity x-ray
DUV - deep ultraviolet; EUV - extreme ultraviolet; PSM - phase shift mask;

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 23

Contamination

• Human hair at the

same scale as the
integrated circuit with
10 mm feature size
• Today’s feature size
100 nm - 100 times
smaller!

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 24

Clean Room Specifications

Table 2.1 Clean Room Ratings by Class of Filtration

Class Number of 0.5-mm Number of 5-mm

particles per ft3 (m3) particles per ft3 (m3)

10,000 10000 (350,000) 65 (23,000)

1,000 1000 (35,000) 6.5 (2,300)
100 100 (3,500) 0.65 (230)
10 10 (350) 0.065 (23)
1 1 (35)* 0.0065 (2.3)

3
*It is very difficult to measure particulate counts below 10/ft

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 25

Common Wafer
Surface Orientations 111,100: crystal orientations (định hướng tinh thể)

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 26

Wafer Cleaning

• Wafers must be cleaned of chemical and particulate

contamination before photo processing
• Example of “RCA” cleaning procedure in table below

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 27

Photoresist Deposition
Automated Production Systems

• Rite Track 88e wafer processing system (Courtesy of Rite Track Services,
Inc.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 28

Mask Alignment

• Each mask must be

carefully aligned to
the previous levels
• Some form of
alignment marks are
used
• Automated alignment
and exposure in
production lines

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 29

Resists for Lithography

• Resists
– Positive gặp ánh sáng sẽ remove
– Negative

• Exposure Sources
– Light
– Electron beams
– Xray sensitive

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 30

 đẳng hướng

Oxide (Metal) Etching Profiles

(a) Isotropic etching - wet chemistry - mask undercutting
(b) Anisotropic etching - dry etching in plasma or reactive
ion etching system
đẳng hướng 0 đẳng hướng

Mask Undercut

process variaty

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 31

Dry Plasma Systems

(a) Conceptual drawing

for a parallel plate
plasma etching
system
(b) Asymmetrical
reactive ion etching
(RIE) system

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 32

Plasma Etching
Characteristics

• Anisotropic etching

• Minimizes chemical
waste 1 atm = 760 mm Hg = 760 torr = 1.013 x 10 5 Pa 1 Pa = 1 N/m2 = 0.0075 torr

• Etching

• Cleaning

• Resist removal
“ashing”

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 33

Mask Fabrication (gds, layout engineer)

• Masking processes
– Direct step on wafer
– Contact printing
– Proximity printing
– Projection printing

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 34

Printing Techniques
• Contact printing damages the
reticle and limits the number of
times the reticle can be used

• Proximity printing eliminates

damage

• Projection printing can operate

in reduction mode with direct
step-on-wafer, eliminating the
need for the reduction step
presented earlier

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 35

 Wafer Steppers

• Wafer stepping systems

widely used
• Must be completely
isolated from sources of
vibration
• High degree of
environmental control
needed
• Often in their own clean
Figure 2.13 The true complexity of a wafer stepper
is apparent in this system drawing. (Courtesy of
room
ASM Lithography, Inc.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 36

 Wafer Steppers
(cont.)
i-line

g-line

Figure 2.15
Lens System Spectral Content of Xe-Hg lamp (Courtesy of SVG)
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 37
Minimum Feature Size
and Depth of Field

Minimum Feature Size F = 0.5
NA


Depth of Field DF = 0.6
(NA)
2

Numerical Aperture NA = sin 

 = wavelength of exposure source

 38
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication
Phase Shifting Masks

Pattern transfer of two

closely spaced lines
(a) Conventional mask
technology - lines not
resolved
(b) Lines can be resolved
with phase-shift
technology

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 39

 ITRS Lithography Projections
Table 2.5 -- ITRS Lithography Projections

Year 2001 2003 2005 2008 2011 2014

Dense Line Half-Pitch (nm) 150 120 100 70 50 35

Worst Case Alignment Tolerance 52 42 35 25 20 15

Mean + 3  (nm)

Minimum Feature Size F (nm) 100 80 65 45 30 20

Microprocessor Gate Width

Critical Dimension Control (nm) 9 8 6 4 3 2

Mean + 3  - Post Etching

Equivalent Oxide Thickness (nm) 1.5 - 1.9 1.5 - 1.9 1.0 - 1.5 0.8 - 1.2 0.6 - 0.8 0.5 - 0.6

Lithography Technology Options 248 nm DUV 248 nm + PSM 193 nm + PSM 157 nm +PSM EUV EUV
193 nm DUV 157 nm E-beam projection E-beam projection E-beam projection
E-beam projection E-beam direct write E-beam direct write E-beam direct write
Proximity x-ray EUV Ion Projection Ion Projection
Ion Projection Ion Projection Innovation
Proximity x-ray
DUV - deep ultraviolet; EUV - extreme ultraviolet; PSM - phase shift mask;

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 40

 Inspection
SEM, TEM, STM

“A picture is worth a
thousand words”
– Optical microscopy
– Scanning electron
microscopy (SEM)
– Transmission electron
microscopy (TEM)
– Scanning tunneling
microscopy (STM)

SEM images of a three-dimensional micro-electro-mechanical system

(MEMS) structure (Courtesy of Sandia National Laboratories).
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 41
Inspection
TEM

Figure 2.18
Cross-sectional high-resolution TEM images for MOS structures with (a) 27-Å and (b) 24-Å Image.
Polysilicon grains are easily noticeable in (a); the Si/SiO2 and poly-Si/SiO2 interfaces are shown in part
(b). On a local atomic scale, thickness variations of 2-3 Å are found which are a direct result of atomic
steps at both interfaces. Copyright 1969 by International Business Machines Corporation; reprinted with
permission from Ref. [9].
HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 42
Layout of a Class Chip

Basic 4-Mask Process

PMOS Metal-Gate Process

1. p-diffusion
2. Thin oxide
3. Contacts
4. Metal

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 43

 Four Mask Class Process

p-diffusion Thin oxide

Contacts Metal

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 44

Layout of Class Chip
G F H
J I
A D
B C
G
HOANG Trang. Ref: Pearson Education, Inc.
Metal Gate PMOS Process
G A. Thick oxide capacitor
B. Thin Oxide Capacitor
C. Van der Pauw structure
D. Resistor 1
G E. Resistor 2
F. Diode
G. PMOS transistors
H. PMOS logic inverter
E G I. Lateral pnp transistor
J. Kelvin contact structure
Microelectronic Fabrication 45
Our Class Process
Diode & Resistor Fabrication

Top view of an integrated pn diode.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 46

Our Class Process
Diode Fabrication (cont.)

(a) First mask exposure (b) Post-exposure and development of photoresist

(c) After SiO2 etch (d) After implantation/diffusion of acceptor dopant.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 47

Our Class Process
Diode Fabrication (cont.)

(e) Exposure of contact opening mask, (f) after resist development and etching of contact
openings, (g) exposure of metal mask, and (h) After etching of aluminum and resist removal.

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 48

Layout of Class Chip
G F H
J I
A D
B C
G
HOANG Trang. Ref: Pearson Education, Inc.
Metal Gate PMOS Process
G A. Thick oxide capacitor
B. Thin Oxide Capacitor
C. Van der Pauw structure
G D. Resistor 1
E. Resistor 2
F. Diode
G. PMOS transistors
E G H. PMOS logic inverter
I. Lateral pnp transistor
J. Kelvin contact structure
Microelectronic Fabrication 49
Quiz

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 50

Quiz: ans

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 51

 End of Chapter

FAB Overview and

Photolithography

HOANG Trang. Ref: Pearson Education, Inc. Microelectronic Fabrication 52