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UNIT-1 : LECTURE-6

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General Register Organization

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 https://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

Prerequisites

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▪ Registers

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Register Transfer and Memory Transfer

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▪

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Multiplexer https://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

Multiplexer is a combinational circuit that has maximum of

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2n data inputs, ‘n’ selection lines and single output line.

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Example: 8x1 Multiplexer

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▪ 2x1 Multiplexer 4x1 Multiplexer 8x1 Multiplexer Input: 8 -> pow(2,3)

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Selection lines: 3

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16x1 Multiplexer ……. Output: 1

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Inputs

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8x1 Outputs

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.y B Mux
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D
Select
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Block Diagram Truth Table lines

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Decoder https://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

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▪ Decoder is a combinational circuit that has ‘n’ input lines and 2n data outputs out of which

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only ONE output is activated based on ‘n’ inputs. Example: 3*8 Decoder

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▪ 2x4 Decoder 3x8 Decoder Input: 3

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4x16 Decoder

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Output: 8 -> pow(2,3)

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Block Diagram Truth Table

GENERAL REGISTER ORGANIZATION
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Input
Clock

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A bus organization

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for seven CPU

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R1

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R2
registers.

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R3
R1 R2+R3

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1. MUX A selector (SELA): R5

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R6
to place the content of R2

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R7
into bus A .

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2 . MUX B selector Load

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(7 lines)
(SELB): to place the { }

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SELA MUX MUX SELB

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content o f R 3 into bus B

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3 . ALU operation selector 3x8
A bus B bus

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(OPR): to provide the decoder w
arithmetic addition
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A + B. SELD
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OPR ALU
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4. Decoder destination
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selector (SELD): to https://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

transfer the content of
the output bus into R1 Result -> Register Output
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Control Word https://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

There are 14 binary selection inputs in the unit, and their combined value specifies a control

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word.

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SEL A SEL B SEL D OPR

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3 3 3 5

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EXAMPLE

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R1  R2 - R3

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Field: SELA SELB SELD OPR .y
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Symbol: R2 R3
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R1 SUB
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Control word: 010 011 001 00101

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Encoding of Register Selection Fields
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Binary Codes SEL A SEL B SEL D

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000 Input Input None

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001 R1 R1 R1

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010 R2 R2 R2

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011 R3 R3 R3

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100 R4 R4 R4

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101 R5 R5 R5

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110 R6 R6 R6
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111 R7 R7 R7
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NOTE: When SELA or SELB is 000, the corresponding multiplexer selects the external input data.
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When SELD = 000, nohttps://www.youtube.com/playlist?list=PLqisrLSFbMDKZRViIED3mwBVHl5c4LG-L

destination register is selected but the contents of the output bus are available in
the external output.
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Encoding of ALU OPERATION
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Opr Select Operation Symbol

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00000 Transfer A TSFA

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00001 Increment A INCA

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00010 ADD A + B ADD

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00101 Subtract A - B SUB

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00110 Decrement A DECA

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01000 AND A and B AND

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01010 OR A and B OR
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01100 XOR A and B XOR
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01110 Complement A COMA

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10000 Shift right A SHRA

11000 Shift left A SHLA 8

Examples of Microoperations
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Symbolic Designation

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Microoperation SEL A SEL B SEL D OPR Control Word

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R1  R2 - R3 R2 R3 R1 SUB 010 011 001 00101

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R4  R4  R5 R4 R5 R4 OR 100 101 100 01010

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R6  R6 + 1

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R6 - R6 INCA 110 000 110 00001

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R7  R1

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R1 - R7 TSFA 001 000 111 00000

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Output  R2
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R2 - NONE w TSFA 010 000 000 00000
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Output  Input
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INPUT - NONE TSFA 000 000 000 00000

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R4  shl R4 R4 - R4 SHLA 100 000 100 11000

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R5  0 R5 R5 R5 XOR 101 101 101 01100 9

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Thank

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