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Design of low power preamplifier IC for cochlear implant using split folded
cascode technique

Article in Microsystem Technologies · September 2021

DOI: 10.1007/s00542-020-05158-0

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TECHNICAL PAPER

Design of low power preamplifier IC for cochlear implant using split

folded cascode technique
Sourav Nath1 • N. M. Laskar1 • Swagata Devi1 • Koushik Guha1 • K. L. Baishnab1 • Jacopo Iannacci2

Received: 23 November 2020 / Accepted: 27 November 2020

Ó The Author(s), under exclusive licence to Springer-Verlag GmbH, DE part of Springer Nature 2021

Abstract
According to the WHO (World Health Organization) report, out of 360 million people, i.e. over 5% of world population,
have a disabling hearing loss. Designing a low-cost cochlear implant for hearing aid device is therefore of great impor-
tance. The overall cochlear system consists of several blocks, namely, the microphone for sensing the sound waves, the
preamplifier for boosting the signal level and the signal processing unit to generate electrical pulses for the electrode to
stimulate the auditory nerve. In this paper, we address the design of the High-gain Low Power Preamplifier block for
cochlear implants, as it plays a crucial role for the incoming signal to be further processed. In particular, a new technique
named Split Folded Cascode (SFC) for designing the Operational Transconductance Amplifier (OTA) is proposed. This
arrangement enhances the performance of normal cascode solutions. This technique splits the current in two different
branches and increases the overall transconductance by 1.414 times. Simulations and post layout analysis have been carried
out for the proposed preamplifier in Cadence Virtuoso using Semi-Conductor Laboratory (SCL) 180 nm technology
parameters. In this proposed design a mid-band gain of 43.7 dB, bandwidth of 18–20 kHz and noise 473.47 nV/HHz at
4 kHz are obtained.

1 Introduction tests and other applications. Among various biomedical

systems, cochlear implants design has attracted various
With growing advancement in technology, the design of researchers. A cochlear implant is a device that stimulates
portable electronics systems in biomedical applications has the cochlear nerve. The implant has external and internal
become a challenge for the developers. The designed sys- parts. The external part picks up sounds with a microphone.
tem must meet some critical specification requirements, so It then processes the sound and transmits it to the internal
that it can give accurate and precise reading for biomedical part of the implant. The incoming signals from the
microphone are first boosted up by using a preamplifier,
and then feed the Analog to Digital Converter (ADC) to
& Jacopo Iannacci
iannacci@fbk.eu convert the signal in digital form to process further. These
small components collectively form an Analog Front End
Sourav Nath
nathsourav945@gmail.com (AFE). For better understanding, a complete overall block
diagram of a cochlear system is shown in Fig. 1. An AFE is
N. M. Laskar
naushad.0015@gmail.com a set of analogue signal conditioning circuitry that uses
sensitive analogue amplifiers, filters and other circuits to
Swagata Devi
swagatadevi90@gmail.com provide a reconfigurable and flexible electronics functional
block, to interface a variety of sensors to ADC or micro-
Koushik Guha
koushikguha2009@gmail.com controller. Low-power AFEs are enabling many emerging
applications, particularly in the healthcare field, ranging
K. L. Baishnab
klbaishnab@gmail.com from speech processing systems to biomedical wearable
devices. Additionally, AFE power consumption has
1
National Institute of Technology Silchar, Assam 788010, become a significant part of the systems power budget. So,
India designing a power efficient AFE is of utmost importance
2
Center for Materials and Microsystems, Fondazione Bruno and to design an optimised preamplifier for AFE is also
Kessler (FBK), Via Sommarive, 18, 38123 Trento, Italy

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 Microsystem Technologies

preamplifiers. In this paper, the design of the preamplifier

block for cochlear implants has been targeted. A high
swing folded cascode with current scaling technology is
used rather than standard folded cascode solutions. Con-
ventional folded cascode has low output swing as well as
high power consumption. In order to get better perfor-
mance in terms of gain, output swing as well as low noise
and relatively low power, a modified structure starting from
a conventional folded cascode is used. Here the input
transistors are used as PMOS transistors, as it is more
immune to noise (Razavi 2002). The folded cascode pairs
Fig. 1 Overall block diagram of a cochlear system
are split in the proposed design with equal aspect ratio, and
as such, the effective transconductance (gm) of the input
important. The main challenge is to overcome the noise-
pair is increased by 1.414 times. Current scaling resistor is
power trade off in designing the preamplifier. Many works
used to get low noise. A diode-connected cascode MOS
have been reported in literature for what concerns design-
current mirror is used to provide high output swing. Instead
ing an optimised preamplifier block. A relevant contribu-
of a normal current mirror load, a cascode current mirror
tion is that by Ryoo et al. (2016), which involves designing
one is used to get high Rout at the output, as well as to get
a charge amplifier and a programmable gain amplifier with
high gain.
feedback from the ADC to adjust the gain. However, large
The proposed preamplifier simulations have been per-
array of capacitors is present in the design, which con-
formed in Cadence Virtuoso using SCL 180 nm technology
sumes a large area. The SNR (Signal to Noise Ration)
parameters. The post-layout analysis for the proposed
achieved is lower and the circuit consumes high power.
design has also been performed, which indicates a close
(Ryoo et al. 2016). Bandwidth adaptive technique is also
agreement with pre-layout simulations. Finally, the tape-
used to optimise the power consumption. Depending upon
out of the Amplifier has been designed. Simulation results
the input signal, certain bandwidth is selected by band-
reveal that the proposed amplifier yielded a high mid-band
width extraction block attached with the preamplifier.
gain of 43.5 dB with a -3 dB bandwidth of 20 kHz, which
Nonetheless, the circuit complexity is high and as a
is suitable for cochlear implant device. The amplifier input-
result, it consumes large chip area (Du and odame 2013). In
referred noise has been found to be 368 nV while con-
some works, chopper-based techniques are introduced to
suming 4.47 lW of power from a 1.8 V supply.
reduce the flicker noise modulation and demodulation cir-
cuitry is used, which is termed as chopper circuit. PMOS
1.1 Preamplifier design
input based folded cascode amplifier is used for amplifi-
cation. The circuit complexity is mainly due to 4th order
In this section, the proposed amplifier is discussed in detail.
filter. The two 2nd order filters along with the Common
The overall schematic of the closed loop preamplifier is
Mode Feedback (CMFB) circuit make it bulky and the
shown below in Fig. 2. The topology is the same as pro-
power consumption is also relevant (Uma et al. 2018). In
posed in Ryoo et al. (2016), which exploits the capacitive
some works, Micro-Electro-Mechanical Systems (MEMS)
varactors are used as off chip capacitors to reduce the chip
area as well as the flicker noise (Iannacci 2018, 2017;
Tazzoli et al. 2009; Persano et al. 2016). The gain of the
preamplifier is slightly enhanced as compared to other
reported works (Oh et al. 2017). In some other literature
items, a combined gain-controlled circuit is proposed. The
design employs a MOS-Resistive Feedback structure and a
gain control unit to achieve high accuracy and dynamic
range. However, noise performance is low and it has also
low output swing (Kim et al. 2014). In most of the works it
is observed that they use the capacitive feedback topology
rather than the open loop one, although open loop tech-
nique offers lower area and power consumption. This is
because open loop topology results in a higher input
referred noise, which is an important design criterion for
Fig. 2 Overall schematic of closed loop preamplifier

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Microsystem Technologies
feedback and Cin, Cf are used to control the gain. The
topology is slightly modified here. Instead of passive single
resistor, Mf1 and Mf2 are used as pseudo-resistors, realised
in diode connected mode that aids to get better flexibility in
controlling the cut-off frequency. The series capacitance
along with the input source are used to realise the Micro-
phone (Ryoo et al. 2016). Vref is used as biasing voltage.
The mid band gain is controlled by the ratio of Cin/Cf,
which is approximately found to be 43.5 dB with input
capacitance Cin= 20 pF and Cf = 120 fF. The Cin is actually
used as AC coupling capacitor to cancel the DC offset and
Cf is the feedback capacitance. The block diagram of the
proposed system is shown in Fig. 2. Within the schematic
in Fig. 3, Cp models the parasitic gate capacitances at the
input, while Gm and Ro are used to model the OTA
transconductance and output impedance. Moreover, Rp is
used to realize the overall resistance offered by the series
pseudo-resistors and CL is the load capacitance, the com-
bination of which controls the cut-off frequency of the
overall amplifier. From the block diagram, the overall
transfer function is given by Eq. (1).
vout ðsÞ C in sRP CL
H ðsÞ ¼ ¼  ð1Þ
vin ðsÞ C f 1 þ sRP CL
The mid-band gain of the amplifier is given by Eq. (2)
Cin
Av ¼  ð2Þ
Cf
The input-referred noise of the gain stage of the OTA
can be related to the input-referred noise of the overall
amplifier, as it is shown in Eq. (3)
 
C in þ Cf þ C p;in 2 
 ¼  ð3Þ
vn,amp2 C in vn2
where, vn;amp 2 is the input-referred noise of the amplifier
and vn 2 is the input referred noise of the OTA.
Fig. 3 Block diagram of the
proposed system (Laskar et al.
2018)
1.2 Split folded cascode (SFC) OTA design
For designing the 1st stage of the proposed preamplifier,
Folded Cascode OTA topology has been used as it allows
reduced supply margins and is a self-compensating one
(Razavi 2002). The design uses a normal folded cascode
structure with split input transistor and the folded transistor
set to the same aspect ratio. The idea of doing this is to split
the current in two different branches and to increase the
overall transconductance of the amplifier. This arrange-
ment helps to use low bias current to get sufficient gain,
which results in low power consumption. In Fig. 4 the split
folded cascode is shown. The arrangement and mathe-
matical proof are stated below. The proposed schematic
circuit diagram is shown in Fig. 5. Here the input transistor
M1a, M1b, M2a, M2b are split, i.e. instead of one, a pair of
transistors are connected, similarly to complement the
splitting, a pair of folded transistors is also connected as
M5a, M5b, M6a, and M6b. As a result of splitting with
lower aspect ratio, the same performance is achieved,
which in turn helps in reducing the area as well as the
parasitic resistance and capacitance in the backend design.
As it can be seen, source degenerated current sources are
employed as in Laskar et al. (2018), rather than normal
current sources, which provides a significant improvement
in noise performance as compared to a conventional Folded
Cascode OTA. Resistance R2, R3, R4, R5 are connected to
scale the current. They are configured to draw less current
through, therefore leading to lower noise (Laskar et al.
2018).
Here the cascode current mirror load is used instead of
normal current mirror to enhance the gain. One extra
transistor is being used, i.e. M13, to give high swing out-
put, as we know folded cascode has low output swing
(Laskar et al. 2018). In Table 1 all the design parameters
are listed after calculation.
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 Microsystem Technologies

Fig. 4 a Normal folded cascode

b Split folded cascode (SFC)

Fig. 5 Circuit diagram of

proposed OTA

Table 1 Parameter values used

Parameter Value
in design
VDD 1.8 V
Ibias 490 nA
Cf 120fF
Cin 20pF
(W/L)1a = (W/L)1b = (W/L)2a = (W/L)2b 20 lm /2 lm
(W/L)3a = (W/L)3b = (W/L)4a = (W/L)4b (W/L)15 0.42 lm /8 lm
(W/L)5a = (W/L)5b = (W/L)6a = (W/L)6b 0.42 lm /0.18 lm
(W/L)7 = (W/L)8 10 lm /5 lm
(W/L)9 = (W/L)10 5 lm /5 lm
(W/L)13 2 lm /0.18 lm
(W/L)11 = (W/L)12=(W/L)14 14 lm / 10 lm

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Fig. 6 Small signal model

1.3 Small signal modelling 1.4 Small signal output resistance

Under the assumption of neglecting the body effect, the The output resistance is the parallel combination of the
complete small signal analysis is performed. This is done current mirror load with parallel combination of input
because the body terminal of the PMOS is connected transistor and the source degeneration resistor. Equa-
directly to the positive terminal of the power supply and the tion (12) shown below is the total output resistance
body of the NMOS is connected directly to the ground. The   
Rout ¼ ðgm8 r o8 r o10 Þ k ð gm6a r o6a r o1a k ðr o3b k R4 Þ
small signal diagram of the proposed circuit is shown  
k ð gm6b r o6b r o1b k ðr o4b k R5 ÞÞÞ ð12Þ
below in Fig. 6 considering the half circuit method.
Small signal transconductance.
The small signal transconductance is an important 1.5 Small signal gain
parameter to be determined. The overall transconductance
is calculated from the Fig. 6 shown below. The small signal gain of the proposed preamplifier is given
Referring to the schematic in Fig. 6, by the product of the obtained transconductance and the
R8 ¼ ðððgm3b r 03b Þ k R4 Þ k r 01a Þ ð4Þ output resistance calculated. Equation (13) shown below
gives the gain of the amplifier:
R9 ¼ gm6a r 06a ð5Þ
Av ¼ Gm  Rout
R6 ¼ ðððgm4b r 04b Þ k R5 Þ k r 01b Þ ð6Þ
2gm1a
R7 ¼ gm6b r 06b ð7Þ Av ¼ ðgm8 r o8 r o10 Þ
1 þ ðððg gr03b
m6a r 06a
ÞkR Þkr Þ
 m3b 4 01a   
I out ¼ I out1 þ I out2 ð8Þ k ð gm6a r o6a r o1a k ðr o3b k R4 Þ k ð gm6b r o6b r o1b
k ðr o4b k R5 ÞÞÞ
Moreover, I out1 ¼ I out2 , R6 ¼ R8 andR9 ¼ R7 : Since all
the aspect ratios of the transistor are the same, the resis- ð13Þ
tance value of R4 and R5 are the same, as well. Hence from
Eq. (8)
1.6 Noise analysis
I out ¼ 2I out1 ¼ 2I out2 ð9Þ
The main source of noise, as shown in Fig. 2, is given by
After solving the small signal model, the overall
the contribution by all non-cascode transistors, as the
transconductance Gm can be written as:
cascode transistors do not contribute to noise (Razavi
2gm1a gm1a gm1b 2002). The total noise analysis is done by considering half
Gm ¼ ¼ ð10Þ
1 þ RR98 1 þ RR98 1 þ RR76 circuit, as the circuit is symmetric. Then the final expres-
sion of noise is obtained by multiplying the half circuit
Replacing the values of R9, and R8 in Eq. (10)
noise by two. Therefore, the main contributing component
2gm1a for noise is the differential pair input transistors M1a, M1b,
Gm ¼ ð11Þ
1 þ ðððg rg03b
m6a r 06a
ÞkR4 Þkr01a Þ the resistors R4 and R5, the current mirror transistors M9
m3b
and M10, and the high swing active resistor M13. The
overall noise of the amplifier would then be the integration
of the OTA noise over the amplifier noise bandwidth. The
total noise for any circuit is given by the contribution of
thermal noise, which is due to random motion of charge

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 Microsystem Technologies

carriers (Razavi 2002), and flicker noise due to trapping of 2 Results and discussions
charge carriers at the gate. The flicker noise is the dominant
noise in case of low frequencies. The thermal noise is For validating the performance of the proposed preampli-
shown in Eq. (14) and the flicker noise is shown in fier, simulations have been carried out in Cadence Virtuoso
Eq. (13). The overall input referred noise for the proposed using SCL 180 nm technology parameters, and setting the
OTA is shown in Eq. (17). design parameters as previously shown in Table 1. The
In the equations below, post-layout analysis of the design was performed and
gm1 ¼ gm1a¼ gm1b ; 2gm1 ¼ gm1a þ gm1b results indicate very low deviation as compared to pre-
Similarly, gm2 ¼ gm2a¼ gm2b ; 2gm2 ¼ gm2a þ gm2b ; layout, which further validates the consistency of the per-
gm3 ¼ gm3a¼ gm3b ; 2gm3 ¼ gm3a þ gm3b formance of the proposed preamplifier for the said appli-
gm4 ¼ gm4a¼ gm4b ; 2gm4 ¼ gm4a þ gm4b cation. It can be observed that the proposed preamplifier
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi shows a very good mid-band gain of around 43.7 dB at the
Moreover, as known: gm ¼ 2ln C ox WL I D -3 dB cut-off frequencies of 18 Hz (lower) and 20 kHz
Bearing this in mind, the mentioned equations are for- (upper) (see Fig. 7). It can be inferred that at low fre-
mulated as follows: quencies the flicker noise significantly dominates the noise,

2 4gm1 4gm2 4gm3 4gm4 2gm13 which decreases with the increase in frequency. After the
I n;Thermal ¼ 4KT þ þ þ þ
3 3 3 3 3 corner frequency, there is a flat frequency response indi-
4gm9 1 1 1 1 cating that the noise is dominated by thermal noise (see
þ þ þ þ þ Þð14Þ Fig. 8). Finally, the power dissipation plot in Fig. 9 shows
3 R2 R3 R 4 R5
ð14Þ a very low deviation in power dissipation from 4.6 lW to
  4.63 lW after the post-layout analysis has been performed,
K p 2gm1 2 2gm2 2 2K N gm3 2 gm13 2 2gm9 2 thereby indicating the negligible impact of parasitic
I 2n;Flicker ¼ þ þ þ þ ð15Þ
Cox f W 1 L1 W 2 L2 K p W 3 L3 W 13 L13 W 9 L9
capacitances on the overall load of the amplifier. The
ð15Þ results are listed in Table 2 showing some deviation,
however limited to less than 2% and the results are in close
V 2n;Total ¼ ðI 2n;Thermal þ I 2n;Flicker Þ  Rout 2
ð16Þ
agreement, thereby validating the consistency in the per-
formance of the proposed amplifier. The comparative

 
1 4gm1 4gm2 4gm3 4gm4 2gm13 4gm9 1 1 1 1
V 2n;TotalInputRefered ¼ ½4KT þ þ þ þ þ þ þ þ þ
Gm 2  3 3 3 3 3 3 R2 R3 R4 R 5
K p 2gm1 2 2gm2 2 2K N gm3 2 gm13 2 2gm9 2
þ þ þ þ þ  ð17Þ
Cox f W 1 L1 W 2 L2 K p W 3 L3 W 13 L13 W 9 L9

Fig. 7 Post layout simulation of

gain

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Microsystem Technologies

Fig. 8 Post layout simulation of

noise

Table 3 Comparison with existing work

Year Work Parameters
Gain BW (Hz) Noise Power
(dB) (V/HHz) (W)

2016 Ryoo et al. 33 400-8 k 331n 167.7u

2016
2016 Croce et al. 18 20-20 k NA 230u
(2016)
2013 Du and odame 20 4k 3uV 65u
(2013)
2018 Uma et al. 17.49 NA 100n NA
Fig. 9 Post layout simulation of dynamic power (2018)
2017 Oh et al. (2017) 9.6 20-20 k 7.3u NA
Table 2 Performance analysis of the preamplifier 2005 Kim et al. NA 8k 3.8u 60u
(2014)
Parameter Pre-layout Post layout Deviation % This Work 43.7 18.7–20.6 k 473.47nV 4.6u
Gain (dB) 43.8 43.7 0.22
BW (kHz) 20.8 20.6 0.96 gain with respect to process variations, and the corre-
Power (lW) 4.6 4.63 0.65 sponding output is shown in Fig. 10. From the analysis it is
Noise (nV/HHz) 478.17 473.47 0.98 found that the proposed design has mid band gain as
43.7 dB throughout the distribution. Furthermore, the
analysis of the proposed amplifier with some other state of complete chip tape-out is shown in Fig. 11.
art designs (Ryoo et al. 2016; Croce et al. 2016; Du and
odame 2013; Uma et al. 2018; Oh et al. 2017; Kim et al.
2014) is shown in Table 3. The power dissipation of the 3 Conclusion
proposed preamplifier has also been found to be very low,
maintaining the audio bandwidth having a value around The main focus of this paper is to report a power efficient
4.7 lW. Thus, the proposed amplifier gives better perfor- preamplifier for cochlear implants. The design was chosen
mance in terms of an improved mid-band gain, higher after extensive literature survey and evaluation of the
bandwidth and a comparable noise and power dissipation current state of the art available design solutions. The
as compared to the present state of the art design. Monte topology used for the preamplifier is folded cascode with
Carlo analysis is also done to check the mean value of the cascode current mirror load to obtain high gain. The

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 Microsystem Technologies

Fig. 10 Post layout monte carlo analysis of gain

Fig. 11 Tape-out of
preamplifier

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Microsystem Technologies
proposed design is based on the split folded cascode
technique, where the folded cascode transistors are split
with the same aspect ratio transistors to get sufficiently
high gain with low bias current. The small signal
transconductance along with gain and output resistance are
calculated and it is found that there is an improvement in
the overall transconductance and output resistance in
comparison to conventional folded cascode techniques.
However, there is a slight increment in the noise due to the
extra transistors used. We know that there is a noise power
trade-off. Therefore, for low power design, there must be
additive noise to compensate the trade-off. The overall
power consumption can be reduced by designing efficient
bias circuit. Post layout simulations of the proposed
preamplifier are performed using SCL 180 nm technology
and the tape-out of the preamplifier chip is done. The
simulation result of both the pre and post layout are shows
very low deviation.
Acknowledgement The authors are deeply grateful to the Ministry of
Information Technology, (MeitY) Govt. of India and SCL Mohali for
supporting this work by necessary grants-in-aid, EDA Tools and
technology files under the SMDP-C2SD Project.
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