PCS-9611S - Electrified Railway - Technical Manual - EN - Overseas General - X - R1.00 - 1127

his
Copyright © 2021 NR. All rights reserved.
NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR
trademarks may be used without written permission. NR products appearing in this document may
be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and benefits
afforded under P.R. China and international copyright and patent laws in its products, including but
not limited to software, firmware and documentation. NR Engineering Co., Ltd. is licensed to use
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including but not limited to copyright, rights in inventions, patents, know-how, trade secrets,
trademarks and trade names, service marks, design rights, database rights and rights in data, utility
models, domain names and all similar rights.
The information in this document is provided for informational use only and does not constitute a
legal contract between NR and any person or entity unless otherwise specified. Information in this
document is subject to change without prior notice.
To the extent required the products described herein meet applicable IEC and IEEE standards, but
no such assurance is given with respect to local codes and ordinances because they vary greatly.
Although every reasonable effort is made to present current and accurate information, this
document does not purport to cover all details or variations in equipment nor provide for every
possible contingency to be met in connection with installation, operation, or maintenance. Should
further information be desired or should particular problems arise which are not covered sufficiently
for your purposes, please do not hesitate to contact us.
Preface
Preface
About This Manual

The technical manual describes the protection, automation, control, and supervision functions of
PCS-9611S feeder relay, and contains operation principle descriptions, and lists function blocks,
logic diagrams, input and output signals, setting parameters and technical data, sorted per function,
as well as the hardware of the device. The manual can be used as a technical reference during the
engineering phase and during normal service. In addition, the manual also includes a glossary that
lists and defines technical terms used throughout the manual.
Safety Information
This manual is not a complete index of all safety measures required for operation of the equipment
(module or device). However, it comprises important information that must be followed for personal
safety, as well as to avoid material damage. Information is highlighted and illustrated as follows
according to the degree of danger:
Indicates an imminently hazardous situation that, if not avoided, will
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, could
result in death or serious injury.
Indicates a potentially hazardous situation that, if not avoided, may result
in minor or moderate injury or equipment damage.
Indicates that property damage can result if the measures specified are
not taken.
Important information about the device, product handling or a certain

section of the documentation which must be given particular attention.
Instructions and Warnings

The following hazard statements apply to this device.
Disconnect or de-energize all external connections BEFORE opening this

device. Contact with hazardous voltages and currents inside this device can
PCS-9611S Feeder Relay I

Date: 2021-04-20
Preface
cause electrical shock resulting in injury or death.
Contact with instrument terminals can cause electrical shock that can result
in injury or death.
Use of this equipment in a manner other than specified in this manual can
impair operator safety safeguards provided by this equipment.
Have only qualified personnel service this equipment. If you are not qualified
to service this equipment, you can injure yourself or others, or cause
equipment damage.
This device is shipped with default passwords. Default passwords should

be changed to private passwords at installation. Failure to change each
default password to a private password may allow unauthorized access. NR
shall not be responsible for any damage resulting from unauthorized access.
DO NOT look into the fiber (laser) ports/connectors.
DO NOT look into the end of an optical cable connected to an optical output.
DO NOT perform any procedures or adjustments that this instruction

manual does not describe.
During installation, maintenance, or testing of the optical ports, ONLY use

the test equipment qualified for Class 1 laser products!
II PCS-9611S Feeder Relay

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Preface
Incorporated components, such as LEDs, transceivers, and laser emitters,

are NOT user serviceable. Return units to NR for repair or replacement.
Equipment components are SENSITIVE to electrostatic discharge (ESD).

Undetectable permanent damage can result if you do not use proper ESD
procedures. Ground yourself, your work surface, and this equipment
BEFORE removing any cover from this equipment. If your facility is not
equipped to work with these components, contact NR about returning this
device and related NR equipment for service.
Insufficiently rated insulation can deteriorate under abnormal operating

conditions and cause equipment damage. For external circuits, use wiring
of SUFFICIENTLY RATED insulation that will not break down under
abnormal operating conditions.
SEVERE power and ground problems can occur on the communications

ports of this equipment as a result of using non-standard cables. Please use
the wiring method recommended in the manual for communication terminals.
DO NOT connect power to the relay until you have completed these
procedures and receive instruction to apply power. Equipment damage can
result otherwise.
Use of controls or adjustments, or performance of procedures other than

those specified herein, may RESULT IN hazardous radiation exposure.
The firmware may be upgraded to add new features or enhance/modify

existing features, please MAKE SURE that the version of this manual is
compatible with the product in your hand.
Document Conventions
 The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The
PCS-9611S Feeder Relay III

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Preface
Glossary also contains definitions of important terms.
 Menu path is connected with the arrow "→" and bold.
For example: the access path of protection settings is: MainMenu→Settings→Protection

Settings
 Settings not in the table should be placed in brackets.
For example: the system setting [Opt_SysFreq]
 Cross-references are presented in italics.
For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1
 Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed
meanings, should be written in double quotes and bold.
For example: press the button "ENT".
Symbols
 AND Gate
& & &
 OR Gate
>=1 >=1 >=1
 Comparator
 Binary signal Input
BI xxx
 Signal input
SIG xxx
 Setting input
IV PCS-9611S Feeder Relay

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Preface
SET xxx
 Enable input
EN xxx
 Timer
Optional definite-time or inverse-time characteristics
Timer
t
t
 Timer
Fixed delay pickup (10ms), fixed delay drop-out (2ms)
10ms 2ms
 Timer
Settable delay pickup, fixed delay drop-out
[Tset1] 0ms
 Timer
Fixed delay pickup, settable delay drop-out
0ms [Tset2]
 Timer
Settable delay pickup, settable delay drop-out
[Tset1] [Tset2]
 Generator
 Transformer
PCS-9611S Feeder Relay V

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Preface
 Reactor
 Motor
 Capacitor
 Busbar
 Circuit breaker
52
 Current transformer
3CT
*
 Voltage transformer
3VT
 Disconnector
VI PCS-9611S Feeder Relay

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Preface
 Earth
Warranty
This product is covered by the standard NR 10-year warranty. For warranty details, please consult
the manufacturer or agent for warranty information.
Document Structure
This manual is a comprehensive work covering the theories of protection, control, supervision,
measurement, etc. and the structure & technical data of relevant hardware. Read the sections that
pertain to your application to gain valuable information about using this device. To concentrate on
the target sections of this manual as your job needs and responsibilities dictate. An overview of
each manual section and section topics follows.
1 Introduction
Introduces the features of this device, summarizes functions and applications of the device.
2 Technical Data
Lists device specifications, type tests, and ratings.
3 Protection Functions
Describes the function of various protection elements, gives detailed specifics on protection
scheme logic, and provides the relevant logic diagrams.
4 Control Functions
Describes the logic for the control of disconnectors and circuit breakers.
5 Measurement
Provides information on viewing fundamental and metering quantities for voltages and currents, as
well as power and energy metering data.
6 Supervision
Describes self-supervision technique to help diagnose potential difficulties should these occur and
includes the list of status notification messages. Provides a troubleshooting chart for common
device operation problems.
7 System Functions
Describes how to perform fundamental operations such as clock synchronization, communicating
with the device, switching active setting group, checking relay status, reading event reports and
SER (Sequential Events Recorder) records.
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Preface
8 Hardware
Describes the hardware of the PCS S series device family and provides general information on the
product structure and the modules’ information.
9 Settings
Provides a list of all PCS-9611S settings and their ranges, unit, steps, defaults. The organization
of the settings is similar to the settings organization in the device and in the PCS-Studio
configuration tool.
Appendix A Glossary
Describes the abbreviations adopted in this manual.
Document Revision History

PN: ZL_PCS-9611S_Electrified Railway_Technical Manual_EN_Overseas General_X
Current version: R1.00
Corresponding
Version Date Description of change
Document Software
R1.00 R1.00 2021-04-20  Form the original manual.
VIII PCS-9611S Feeder Relay

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Introduction
1 Introduction
1
Table of Contents
1.1 Functions ......................................................................................................... 1-1

1.2 Features............................................................................................................ 1-4
List of Figures
Figure 0-1 Functional diagram of PCS-9611S .......................................................................... 1-1
PCS-9611S Feeder Relay 1-a

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1 Introduction
1-b PCS-9611S Feeder Relay

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Introduction
Application
PCS-9611S is a protection, control and monitoring unit for the feeder and incoming feeder of
electrified railway power system under direct feeding mode or autotransformer feeding mode. This 1
relay is suitable for wall surface mounted indoors or outdoors or flush mounted into a control panel.
The function diagram of this relay is shown in Figure 0-1.
Busbar
1VT
52
27 21L 50/51P SOTF FL 83ATS AR

1VT
1CT
*
50BF 50/51D VTS FR
Load
Figure 0-1 Functional diagram of PCS-9611S
The PCS-9611S is widely adopted not only for conventional substations, but also for digital
substations. It supports IEC 61850 Editions 1 and 2 and provides GOOSE with high real-time
performance. The process level network supports peer-to-peer (P2P) mode and networking mode,
including single network mode and dual network mode. The station level network can also receive
and send MMS messages (such as interlocking signals) or process level GOOSE messages (such
as circuit breakers or disconnectors positions and trip signals).
1.1 Functions
1 Protection functions
ANSI Protection Functions Remark

 Up to 3 zones distance protection with settable
direction
21L Distance protection  Load blinders are provided to prevent mis-operation for
heavy load flow
 Second harmonic blocking function
PCS-9611S Feeder Relay 1-1

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1 Introduction
 Up to 3 stages with independent logic

 The direction control element can be set as no
1 50/51P Phase overcurrent protection


direction, forward direction and reverse direction
Voltage control element for each stage
 One stage of DPFC overcurrent protection
50/51D DPFC overcurrent protection
 Two stage of undervoltage protection
27P Undervoltage protection
 It will be blocked when the circuit breaker is open
 two stages of overvoltage protection
59P Overvoltage protection

 Two stages of thermal overload protection,
49 Thermal overload protection  One stage for alarm purpose and the other stage for
trip purpose
 One stage of breaker failure protection
 Breaker failure protection and re-trip function
50BF Breaker failure protection  It can be initiated by current, circuit breaker position or
external binary input
 Two time delays
 One stage of overcurrent SOTF protection
SOTF Switch-on-to-fault protection
 One stage of distance SOTF protection
Incoming feeder auto-transfer  It is completed by the cooperation of two devices
83ATS
switch  It is triggered by the undervoltage protection
 One shot or multi-shot
79 Auto-reclosing
 Supports no check or live charge check
 The piecewise linearized reactance approximation
FL Fault locator
method
Voltage transformer
VTS
supervision
TCS Tripping circuit supervision
2 Control functions
 Switchgear control
 Double point status synthesis
 Remote/Local control mode switch
 Interlocking logic for control
 Direct control
 Switchgear trip counter
3 Measurement and metering
 U, I, P, Q, Cos
1-2 PCS-9611S Feeder Relay

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Introduction
 Max.15th harmonics
 Energy metering (active and reactive energies for import and export)
 Power Quality Supervision (PQS) with Total Harmonic Distortion (THD)

1
4 Supervision functions
 VT circuit supervision
 Self-diagnostic
 DC power supply supervision
 System frequency supervision
 Event recorder including 1024 disturbance items, 1024 change-of-state events, 1024
supervision events, 256 control logs and 1024 device logs.
 Disturbance recorder including 64 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file).
 Single line diagram representation in display
5 Communication functions
 Support of various protocols
 Modbus
 DNP3
 IEC 60870-5-103
 IEC 61850 Ed1 & Ed2
 IEC 62439 Parallel Redundancy Protocol (PRP)
 IEC 62439 High-availability Seamless Ring (HSR) Redundancy Protocol
 IEEE 802.1w Rapid Spanning Tree Protocol (RSTP)
 Support for digital substation
 Extendable quantity of communication interfaces
 Support of IEC 61850 MMS Server
 Support of IEC 61850-8-1 GOOSE
 Up to four 10Base-T/100Base-TX copper Ethernet ports
 Up to four 100Base-FX optical Ethernet ports
 Two RS-485 serial ports for communication or printer
 One RS-485/TTL serial port for clock synchronization

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1 Introduction
 One BNC connector for clock synchronization
6 User Interfaces
1  Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and set-point
adjustment
 Push buttons for open/close, switch for selection between local and remote control, and
user's login and logout authority management
 4 Programmable operator pushbuttons with user-configurable labels
 Up to 15/18 (6U, 1/3 × 19" or 6U, 1/2 × 19" chassis) programmable target LEDs with user-
configurable labels
 1 RS-232 rear port for printer (by jumper)
 Language switchover—English+ selected language
 Configuration tool—PCS-Studio
7 Additional functions
 User programmable logic
 Fault location
 Clock synchronization
 IRIG-B: IRIG-B via RS-485 differential level or TTL level
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 IEEE1588: Clock message based on IEEE1588 via Ethernet network
 SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
 SNTP (BC): Broadcast SNTP mode via Ethernet network
 Message (IEC103/Modbus/DNP3): Clock messages through IEC103 protocol,

Modbus protocol and DNP3 protocol
 Cyber security
 NERC CIP
 IEC 62351
 IEC 62443
 IEEE 1686
1.2 Features
 Unified software and hardware platform, comprehensive power grid solutions of protection,

Date: 2021-04-20
Introduction
control, measurement and monitoring, easy to use and maintain.
 High reliability and redundancy design for drive systems of the sampling circuit and the output
circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD 1
can mutually check and detect the potential abnormality in the sampling circuit in time. The
control power supply of the output relay is independent with the control circuit of trigger signals,
which can prevent from undesired operation caused by the abnormality of drive circuit of output
relays.
 Various function modules can satisfy various situations according to the different requirements
of users. Flexible and universal logic programming, user-defined configuration of BI/BOs,
buttons and LEDs and powerful analogue programming are supported.
 Modularized hardware design makes the device be easily upgraded or repaired by a qualified
service person. It can be combined with different I/O modules, with online self-check and
monitoring function, and the device can be restored from abnormal operation only need to
replace a single abnormal module.
 Support memory check and error correction function, ensure high reliability and safety.
 Support the internet communication protocol of native PRP/HSR and RSTP.
 Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351
communication service, GOOSE communication in station level & process level, SV
communication with multi-sampling rate.
 Fully comply with cyber security standards, including IEC62443, IEC62351, IEEE1686, NERC-
CIP, support role based access control (RBAC), security audit, security encryption
communication and security tool, improve the cyber security capability of devices.
 Powerful COMTRADE fault and disturbance recording function is supported. The whole
recording time is automatically configurable by the fault duration, which is convenient to fault
analysis and replay. The recording sample rate is up to 9.6kHz.
 Settable secondary rated current (1A/5A) and settable voltage threshold of binary input
 Support small size and large size LCD, control and multifunction button
 Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other
mounting methods.
 Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm2 lead
 Multiple variants with case size 6U, 1/3 × 19" or 6U, 1/2 × 19"
 Protection class of front side is up to IP54
 PCS-Studio engineering tool is the application software on the user's PC for the interface with
PCS S series devices providing all the related functionality. It ranges from device configuration
to entire substation design of bay integration.
 Support IEEE1588, IRIG-B clock synchronization

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1 Introduction
 Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and
its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the
1 abnormality in advance.
 Support setup up to 40 users and allow each user to own different password and access
authority.
 Fully integrates multi functions into one device and can realize the protection and monitoring
function of feeder and incoming feeder etc.
 Comprehensive functionality includes distance protection, overcurrent protection, DPFC

overcurrent protection, breaker failure protection, undervoltage protection, switch-on-to-fault
protection etc. The auto-reclosing, auto-transfer switch (ATS) function, measuring, monitoring
and control function are supported. The high sampling rate of recording is up to 9.6kHz.
 Both of the distance protection and DPFC overcurrent protection are combined with harmonic
blocking and harmonics suppression function to prevent the device from miss-operation.
 Complete event recording function is provided: 64 latest protection operation reports, 1024
latest supervision records, 1024 latest control operation records, 1024 latest user operation
records and 1024 latest records of time tagged sequence of event (SOE) can be recorded.

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2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1 2

2.1.1 AC Current Input................................................................................................................... 2-1
2.1.2 AC Voltage Input................................................................................................................... 2-1
2.1.3 Power Supply ....................................................................................................................... 2-1
2.1.4 Binary Input .......................................................................................................................... 2-2
2.1.5 Binary Output ....................................................................................................................... 2-4
2.2 Mechanical Specifications .............................................................................. 2-5

2.3 Ambient Temperature and Humidity Range .................................................. 2-6
2.4 Communication Port ....................................................................................... 2-6
2.4.1 EIA-485 Port ......................................................................................................................... 2-6
2.4.2 Ethernet Port ........................................................................................................................ 2-6
2.4.3 Optical Fiber Port ................................................................................................................. 2-7
2.4.4 Print Port............................................................................................................................... 2-7
2.4.5 Clock Synchronization Port .................................................................................................. 2-7
2.5 Type Tests ........................................................................................................ 2-8

2.5.1 Environmental Tests ............................................................................................................. 2-8
2.5.2 Mechanical Tests .................................................................................................................. 2-8
2.5.3 Electrical Tests...................................................................................................................... 2-8
2.5.4 Electromagnetic Compatibility .............................................................................................. 2-8
2.6 Certifications.................................................................................................. 2-10

2.7 Liquid Crystal Display (LCD) ........................................................................ 2-10
2.8 Terminals ........................................................................................................ 2-11
2.8.1 Ring Ferrule ........................................................................................................................ 2-11
2.8.2 Pin Ferrule .......................................................................................................................... 2-11
2.9 Measurement Scope and Accuracy ............................................................. 2-11

2.10 Management Function................................................................................. 2-12

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2 Technical Data
2.10.1 Control Performance ........................................................................................................ 2-12
2.10.2 Clock Performance ........................................................................................................... 2-12
2.10.3 Fault and Disturbance Recording .................................................................................... 2-12
2.10.4 Binary Input Signal ........................................................................................................... 2-12
2 2.11 Protective Functions ................................................................................... 2-12

2.11.1 Distance Protection (21L) ................................................................................................. 2-12
2.11.2 Phase Overcurrent Protection (50/51P) ........................................................................... 2-12
2.11.3 DPFC Overcurrent Protection .......................................................................................... 2-13
2.11.4 Undervoltage Protection (27P) ......................................................................................... 2-13
2.11.5 Breaker Failure Protection (50BF) ................................................................................... 2-13
2.11.6 Switch-on-to-Fault Protection (SOTF) .............................................................................. 2-14
2.11.7 Auto-reclosing (79) ........................................................................................................... 2-14
2.11.8 Fault Locator ..................................................................................................................... 2-14
2.12 Communication Functions ......................................................................... 2-14

2.12.1 GOOSE ............................................................................................................................ 2-14

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2 Technical Data
2.1 Electrical Specifications
2.1.1 AC Current Input

 Conventional AC current input
Nominal frequency (fn) 50Hz, 60Hz 2

Rated current (In) 1A/5A (Settable)
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden <0.05VA/phase @1A, <0.25VA/phase @5A
2.1.2 AC Voltage Input
Nominal frequency (fn) 50Hz, 60Hz
Rated voltage (Un) 100V~130V
Linear to 1V~300V
Thermal withstand Phase-to-ground Phase-to-phase
-continuously 300V 519V
-10s 600V 1038V
-1s 660V 1141V
Burden at rated <0.10VA/phase @100V
2.1.3 Power Supply
100Vac/110Vac/115Vac
110Vdc/125Vdc 24Vdc/30Vdc
Rated voltage 120Vac/127Vac/220Vac
220Vdc/250Vdc 48Vdc/60Vdc
230Vac/240Vac/250Vac
IEC 61000-4-11:2017
Permissible voltage range IEC 61000-4-29:2000
88~300Vdc 80~275Vac 18~72Vdc
IEC 60255-26:2013
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage
Burden Quiescent condition <15W (Default hardware configuration)

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2 Technical Data
Additional for each

0.25W ~ 0.35W
energized SFP
Quiescent condition: <1W
For BI modules with high power
binary inputs (Binary inputs which

2 provide settable conducting mode
by high power with constant
current drain):
0.014W @24Vdc
0.031W @48Vdc
0.096W @110Vdc
Additional for each BI 0.115W @125Vdc

Additional for each energized
module 0.27W @220Vdc
binary input
0.33W @250Vdc
For BI modules without high
power binary inputs:
0.004W @24Vdc
0.015W @48Vdc
0.08W @110Vdc
0.106W @125Vdc
0.32W @220Vdc
0.41W @250Vdc
Additional for each BO Quiescent condition: <0.1W
module Additional for each energized relay: <0.44W
2.1.4 Binary Input
Settable pickup voltage and dropout voltage
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.73mA 0.83mA 1.47mA 1.67mA
On value (Default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc
Off value (Default set) <55Vdc <62.5Vdc <110Vdc <125Vdc
Maximum permissible voltage 300Vdc
Withstand voltage 2000Vac, 2800Vdc (1 min)

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2 Technical Data
Settable pickup voltage and dropout voltage which supports high-power binary input
Rated voltage 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 0.86mA 0.92mA 1.23mA 1.33mA
On value (Default set) 69.3~132Vdc 78.75~160Vdc 138.6~264Vdc 157.5~300Vdc

2
Off value (Default set) <55Vdc <62.5Vdc <110Vdc <125Vdc
Rated voltage 110Vac 220Vac
Rated current drain 0.73mA 1.47mA
On value (Default set) 69.3~132Vac 138.6~264Vac
Off value (Default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 110Vac 220Vac
On value (Default set) 69.3~132Vac 138.6~264Vac
Off value (Default set) <55Vac <110Vac
Maximum permissible voltage 300Vac
Rated voltage 24Vdc 48Vdc
Rated current drain 0.16mA 0.32mA
On value (Default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (Default set) <12Vdc <24Vdc

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2 Technical Data
Rated voltage 24Vdc 48Vdc
2 Rated current drain 0.58mA 0.66mA
On value (Default set) 15.12~28.8Vdc 30.24~57.6Vdc
Off value (Default set) <12Vdc <24Vdc
2.1.5 Binary Output
Tripping/signalling contact
Output mode Potential free contact
Maximum system voltage 250Vac, 300Vdc
Continuous carry 10A
Pickup time (Typical value) <5ms
Drop-off time (Resistive load) <6ms
0.5A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms) 0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
0.5A@48Vdc
0.35A@110Vdc
Cyclic capacity (2.5 cycle/second,
0.30A@125Vdc
L/R=40ms)
0.20A@220Vdc
0.15A@250Vdc
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Up to 18 (6U, 1/3 × 19", ring ferrule), 22 (6U, 1/3 × 19", pin ferrule), 44
Number (6U, 1/2 × 19", ring ferrule) or 56 (6U, 1/2 × 19", pin ferrule) binary
outputs according to various hardware configurations

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2 Technical Data
Heavy-capacity tripping contact
Output mode Potential free contact
MOV Protection (Maximum voltage) 350Vdc, 275Vac
Continuous carry 10A
Pickup time (Typical value) <1ms
Drop-out time (Resistive load) <10ms 2

10A@48V L/R=40ms
10A@110V L/R=40ms
Breaking capacity 10A@125V L/R=40ms
10A@220V L/R=20ms
10A@250V L/R=20ms
10A@48V L/R=40ms
Cyclic Capacity (4cycles in 1 second, 10A@110V L/R=40ms
followed by 2 minutes idle for thermal 10A@125V L/R=40ms
dissipation) 10A@220V L/R=20ms
10A@250V L/R=20ms
30A@3s
Short duration current
50A@1s
Durability (Loaded contact) 10000 operations
Up to 4 (6U, 1/3 × 19", ring ferrule) or 12 (6U, 1/2 × 19", ring ferrule)
Number heavy-capacity binary outputs according to various hardware
configurations
2.2 Mechanical Specifications
Chassis color Silver grey
Approx. 8.66kg (6U, 1/2 × 19")

Weight per device
Approx. 6.93kg (6U, 1/3 × 19")
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated front plate
Protection Class
Standard IEC 60529-2013
IP52
Front side
IP54 (valid for surface mounting mode of 6U, 1/3 × 19" or 6U, 1/2 × 19"

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2 Technical Data
case with sealing strip)
Other sides IP50
Rear side, connection terminals IP20
2.3 Ambient Temperature and Humidity Range

2
Standard IEC 60255-1:2009
-40°C to +80°C (Readability of display may be impaired below -20°C

Operating temperature
and above 70°C)
Transport and storage temperature

-40°C to +80°C
range
Permissible humidity 5%~95%, without condensation
Pollution degree Ⅱ
Altitude <3000m
2.4 Communication Port
2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997 or Modbus
Maximum capacity 32
Maximum transmission distance 500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port
Connector type RJ-45
Transmission standard 100Base-TX
Max. transmission distance 100m
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
Connector type LC
Fiber type Multi mode
Wave length 1310nm

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2 Technical Data
Transmission standard 100Base-FX
Max. transmission distance 2km
Min. transmission power 50μm: -24dBm 62.5μm: -20dBm
Min. receiving power -31dBm
Protocol IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
Safety level Isolation to ELV level 2

2.4.3 Optical Fiber Port
For Process Level
Characteristics Glass optical fiber
Connector type LC
Fiber type Multi mode
Transmission standard 100Base-FX
Max. transmission distance 2km
Wave length 1310nm/850nm
Min. transmission power -20dBm
Min. receiving power -31dBm
2.4.4 Print Port
Type RS-232
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
2.4.5 Clock Synchronization Port
Type RS-485 serial port
Input Demodulated IRIG-B or PPS
Nominal voltage 5Vdc±10%
Maximum voltage 5.5Vdc
Input impedance 2.5kΩ
Isolation 500Vdc
Type BNC port (Female connector)
Input Demodulated IRIG-B or PPS
Nominal voltage 5Vdc±10%

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2 Technical Data
Maximum voltage 5.5Vdc
Characteristic impedance 50Ω
Isolation 500Vdc
2.5 Type Tests

2
2.5.1 Environmental Tests
Dry cold test IEC60068-2-1:2007
Dry heat test IEC60068-2-2:2007
Damp heat test, cyclic IEC60068-2-30:2005
2.5.2 Mechanical Tests
Vibration IEC 60255-21-1:1988 Class Ⅱ
Shock IEC 60255-21-2:1988 Class Ⅱ
Bump IEC 60255-21-2:1988 Class Ⅰ
Seismic IEC 60255-21-3:1988 Class Ⅱ
2.5.3 Electrical Tests
Standard IEC 60255-27:2013
Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category Ⅲ
Insulation resistance measurements Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-26:2013
1MHz burst disturbance test Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 61000-4-2:2008 class Ⅳ
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radio frequency interference tests
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz, 1400~2700MHz

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2 Technical Data
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
IEC 60255-26:2013
Fast transient disturbance tests Power supply, I/O, Earth: class Ⅲ, 4kV, 5kHz, 5/50ns
Communication terminals: class Ⅲ, 2kV, 5kHz, 5/50ns 2

IEC 60255-26:2013
Power supply, AC input, I/O port: class Ⅲ, 1.2/50μs

Surge immunity test
Common mode: 4kV
Differential mode: 2kV
IEC 60255-26:2013
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ, 10V (rms), 150
Conducted RF electromagnetic
kHz~80MHz
disturbance
Spot frequency
10V (rms), f=27MHz/68MHz
Power frequency magnetic field IEC 61000-4-8: 2009
immunity class Ⅴ, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2016
Pulse magnetic field immunity
class Ⅲ, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic field IEC 61000-4-10:2016
immunity class Ⅲ, 100kHz & 1MHz–100A/m
IEC 60255-26:2013
Conducted emission 0.15MHz~0.50MHz: 79dB (μV) quasi peak, 66dB (μV) average
0.50MHz~30MHz: 73dB (μV) quasi peak, 60dB (μV) average
IEC 60255-26:2013
30MHz~230MHz: 40dB (μV/m) quasi peak @10m,
50dB (μV/m) quasi peak @3m

Below 1GHz
230MHz~1000MHz: 47dB (μV/m) quasi peak @10m,
Radiated emission 57dB (μV/m) quasi peak @3m
1GHz~3GHz: 56dB (μV/m) average, 76dB (μV/m)
peak @3m
Above 1GHz
3GHz~6GHz: 60dB (μV/m) average, 80dB (μV/m)
peak @3m
Auxiliary power supply performance

IEC 60255-26:2013
- Voltage dips

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2 Technical Data
-Voltage short interruptions

Up to 200ms for dips to 40% of rated voltage without reset
50ms for interruption without rebooting without energy storage board
(Typical configuration)
500ms for interruption without rebooting with energy storage board
2 (Typical configuration)
2.6 Certifications
 ISO9001:2015
 ISO14001:2015
 ISO45001:2018
 ISO/IEC27001:2013
 CMMI L5
 EMC: 2014/30/EU, EN60255-26:2013
 Products safety (LVD): 2014/35/EU, EN60255-27:2014
 BS EN 50419:2006 (Directive 2012/19/EU (WEEE));
 RoHS directive 2011/65/EU;
 RoHS directive (EU) 2015/863;
 IEC 61850: Edition 2, Parts 6, 7-1, 7-2, 7-3,7-4 and 8-1
 IEC 61850: Edition 2, GOOSE Performance Class P1 (3ms)
 IEEE 1588: IEEE Std C37.238TM-2017
 DNP: DNP 3.0
 PRP: IEC 62439-3 Ed.3 (IS 2016)
 HSR: IEC 62439-3 Ed.3 (IS 2016)
2.7 Liquid Crystal Display (LCD)
Type Resolution
Large size (6U 1/2 × 19" case) 320x240 pixels
Small size (6U 1/3 × 19" case) 240x160 pixels

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2 Technical Data
2.8 Terminals
2.8.1 Ring Ferrule
Connection Type Wire Size Screw Type Torque
Screw terminals, 1.5~4mm2 lead

2
AC current M4 1.6~1.8 N⋅m
AC voltage Screw terminals, 0.8~4mm2 lead M4 1.6~1.8 N⋅m
Power supply Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N⋅m
Contact I/O Screw terminals, 0.8~4mm2 lead M4 0.8~1.4 N⋅m
Grounding (Earthing) connection BVR type, 0.8~4mm2 lead M3 0.6~0.8 N⋅m
2.8.2 Pin Ferrule
Connection Type Wire Size Screw Type Torque
Power supply Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N⋅m
Contact I/O Screw terminals, 0.3~3.3mm2 lead M2.5 0.4~0.6 N⋅m
2.9 Measurement Scope and Accuracy
Item Range Accuracy
±0.2° at 0.2×In＜I＜4.0×In
Phase range 0°~360°
±0.5° at 0.1×In＜I＜0.2×In
Frequency fn±5Hz Max. 0.002Hz
±0.2% of I at 0.2×In＜I＜4.0×In
Current 0.06~4.00In
±0.6% of I at 0.06×In＜I＜0.2×In
Voltage 5~300V 0.2% of U at 5V<U<300V
±0.5% of P, @Un, at 0.1×In＜I＜4.0×In

Active power (W) 0.06~4.00In
±1% of P, @Un, at 0.06×In＜I＜0.1×In
±0.5% of Q, @Un, at 0.1×In＜I＜4.0×In

Reactive power (VAr) 0.06~4.00In
±1% of Q, @Un, at 0.06×In＜I＜0.1×In
±0.5% of S, @Un, at 0.1×In＜I＜4.0×In

Apparent power (VA) 0.06~4.00In
±1% of S, @Un, at 0.06×In＜I＜0.1×In
±0.5% of Wh, @Un, at 0.1×In＜I＜4.0×In

Energy (Wh) 0.06~4.00In
±1% of Wh, @Un, at 0.06×In＜I＜0.1×In
±0.5% of VArh, @Un, at 0.1×In＜I＜4.0×In

Energy (VAh) 0.06~4.00In
±1% of VArh, @Un, at 0.06×In＜I＜0.1×In

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2 Technical Data
2.10 Management Function
2.10.1 Control Performance
Control mode Local or remote
Response time of local control ≤1s

2 Response time of remote control ≤3s
2.10.2 Clock Performance
Real time clock accuracy ≤1s/day
Accuracy of GPS synchronization ≤1ms
External time synchronization IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.10.3 Fault and Disturbance Recording
Settable pre-disturbance, post-disturbance and maximum recorded

Duration & Recording position
duration
Sampling rate Up to 9.6kHz
2.10.4 Binary Input Signal
Resolution of binary input signal ≤1ms
Binary input mode Potential-free contact
2.11 Protective Functions
2.11.1 Distance Protection (21L)
Impedance setting accuracy ≤5%×Setting or 0.1Ω, whichever is greater
Resetting ratio 1.05
Operating time accuracy ≤1%×Setting+40ms
2.11.2 Phase Overcurrent Protection (50/51P)
Pickup current 1.0×Setting
Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater
Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater
Pickup time ≤25ms (at 2 times current setting)
Operating time delay accuracy ≤1%×Setting or 25ms (at 2 times current setting)

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2 Technical Data
(Definite-time characteristics)
Operating time delay accuracy

≤5% of calculated value + 1% current tolerance or 35ms (1.2≤I/Ip≤30)
(Inverse-time characteristics)
Drop-out time accuracy (Definite-time

≤1%×Setting or 30ms
characteristics) 2
Drop-out time accuracy (Inverse-time
≤5% of calculated value or 30ms
characteristics)
Drop-out ratio 0.95
2.11.3 DPFC Overcurrent Protection
Drop-out time accuracy ≤1%×Setting or 30ms
Drop-out ratio 0.95
2.11.4 Undervoltage Protection (27P)
Pickup voltage 1.0×Setting
Voltage setting accuracy ≤1%×Setting or 0.1V, whichever is greater
Pickup time ≤35ms (at 0.9 times voltage setting)
Operating time delay accuracy ≤1%×Setting or 35ms (at 0.9 times voltage setting)
Drop-out time accuracy ≤1%×Setting or 30ms
Drop-out ratio Settable 1.00~1.20, default value: 1.03
2.11.5 Breaker Failure Protection (50BF)

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2 Technical Data
Drop-out time <20ms (at 2 times current setting)
Drop-out ratio 0.95
2.11.6 Switch-on-to-Fault Protection (SOTF)
 Overcurrent SOTF Protection

2 Current setting accuracy ≤1%×Setting or 0.01In, whichever is greater
Pickup time accuracy ≤30ms (at 2 times current setting)
Drop-out time ≤30ms
Drop-out ratio 0.98 (phase overcurrent SOTF protection)
 Distance SOTF Protection
Impedance setting accuracy ≤5%×Setting or 0.1Ω, whichever is greater
Resetting ratio 1.05
Operating time delay accuracy ≤1%×Setting+40ms
2.11.7 Auto-reclosing (79)

Voltage setting accuracy
≤1%×Setting or 0.1V, whichever is greater
(synchronism check)
Time delay accuracy (synchronism
≤1%×Setting+20ms
check)
Time delay accuracy (Reclaim) ≤1%×Setting+20ms
Time delay accuracy (Reclosing) ≤1%×Setting+20ms
2.11.8 Fault Locator

Accuracy in case of metallic short-
<500m
circuit failure
The error may be greater for non-metallic short-circuit
2.12 Communication Functions

2.12.1 GOOSE
Receiving Control Block (RCB) Max. 64 (Typical configuration: 50×FCD+200×BOOL+16×FLOAT)
Sending Control Block (SCB) Max. 16 (Typical configuration: 100×BOOL)

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2 Technical Data
Receiving route delay Max. 2ms
Sending route delay Max. 3ms
The capacity of GOOSE receiving and sending is determined by the

number of configured boards and control & protection functions. 2

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2 Technical Data

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Table of Contents
3.1 One-phase Current Element (TCUR1P).......................................................... 3-1

3.1.1 Function Description............................................................................................................. 3-1
3.1.2 Function Block Diagram ....................................................................................................... 3-1
3.1.3 I/O Signals ............................................................................................................................ 3-1 3

3.1.4 Settings................................................................................................................................. 3-1
3.2 One-phase Voltage Element (TVOL1P) .......................................................... 3-2

3.2.3 I/O Signals ............................................................................................................................ 3-2
3.2.4 Settings................................................................................................................................. 3-3
3.3 Distance Protection (21L) ............................................................................... 3-3

3.3.1 Functions Description ........................................................................................................... 3-3
3.3.3 I/O Signals ............................................................................................................................ 3-5
3.3.4 Logic ..................................................................................................................................... 3-6
3.3.5 Settings................................................................................................................................. 3-6
3.4 Phase Overcurrent Protection (50/51P) ......................................................... 3-7

3.4.2 Function Block Diagram ..................................................................................................... 3-15
3.4.3 I/O Signal ............................................................................................................................ 3-15
3.4.4 Logic ................................................................................................................................... 3-16
3.4.5 Settings............................................................................................................................... 3-16
3.5 DPFC Overcurrent Protection (50/51D) ........................................................ 3-19

3.5.1 Function Description........................................................................................................... 3-19
3.5.3 I/O Signal ............................................................................................................................ 3-21

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3.5.4 Logic ................................................................................................................................... 3-21
3.5.5 Settings............................................................................................................................... 3-22
3.6 Undervoltage Protection (27P) ..................................................................... 3-22

3.6.3 I/O Signal ............................................................................................................................ 3-29
3.6.4 Logic ................................................................................................................................... 3-30
3 3.6.5 Settings............................................................................................................................... 3-30
3.7 Breaker Failure Protection (50BF) ................................................................ 3-31

3.7.3 I/O Signals .......................................................................................................................... 3-32
3.7.4 Logic ................................................................................................................................... 3-33
3.7.5 Settings............................................................................................................................... 3-34
3.8 Switch-on-to-Fault Protection (SOTF).......................................................... 3-35

3.8.3 I/O Signals .......................................................................................................................... 3-37
3.8.4 Logic ................................................................................................................................... 3-37
3.8.5 Settings............................................................................................................................... 3-39
3.9 Automatic Reclosure (79).............................................................................. 3-40

3.9.3 I/O Signals .......................................................................................................................... 3-48
3.9.4 Settings............................................................................................................................... 3-49
List of Figures
Figure 3.3-1 The operating characteristic curve of distance protection ............................... 3-4
Figure 3.3-2 The enabling and blocking logic of distance protection ................................... 3-5
Figure 3.3-3 Logic diagram of the fault detector element of distance protection................ 3-5

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Figure 3.3-4 Logic diagram of zone x of distance protection................................................. 3-6
Figure 3.4-1 The enabling and blocking logic of phase overcurrent protection .................. 3-8
Figure 3.4-2 Logic diagram of the fault detector element of phase overcurrent protection. 3-
8
Figure 3.4-3 Logic diagram of the voltage control element of phase overcurrent protection
....................................................................................................................................................... 3-9
Figure 3.4-4 Logic diagram of harmonic control element of phase overcurrent protection 3-
10
Figure 3.4-5 Definite-time operation characteristic curve of phase overcurrent protection 3- 3

11
Figure 3.4-6 Inverse-time operation characteristic curve of phase overcurrent protection . 3-

12
Figure 3.4-7 Definite-time drop-out characteristic of phase overcurrent protection......... 3-13
Figure 3.4-8 Inverse-time drop-out characteristic curve of phase overcurrent protection .. 3-

14
Figure 3.4-9 Inverse-time drop-out characteristic of phase overcurrent protection ......... 3-15
Figure 3.4-10 Logic diagram of phase overcurrent protection ............................................ 3-16
Figure 3.5-1 The enabling and blocking logic of DPFC overcurrent protection ................ 3-20
Figure 3.5-2 Logic diagram of the fault detector element of DPFC overcurrent protection . 3-
21
Figure 3.5-3 Logic diagram of DPFC overcurrent protection ............................................... 3-21
Figure 3.6-1 The enabling and blocking logic of phase undervoltage protection ............. 3-27
Figure 3.6-2 Logic diagram of the fault detector element of phase undervoltage protection
..................................................................................................................................................... 3-28
Figure 3.6-3 Definite-time operation characteristic curve of phase undervoltage protection

..................................................................................................................................................... 3-28
Figure 3.6-4 Definite-time drop-out characteristic of undervoltage protection ................. 3-29
Figure 3.6-5 Logic diagram of phase undervoltage protection ............................................ 3-30
Figure 3.7-1 Logic of enabling breaker failure protection .................................................... 3-33
Figure 3.7-2 Logic of breaker failure initiating signal abnormality...................................... 3-33
Figure 3.7-3 Logic of breaker failure protection .................................................................... 3-34
Figure 3.8-1 The enabling and blocking logic of SOTF protection ...................................... 3-36
Figure 3.8-2 Logic of auto-reclosing signal............................................................................ 3-37
PCS-9611S Feeder Relay 3-c

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Figure 3.8-3 Logic of manual closing signal .......................................................................... 3-38
Figure 3.8-4 Logic of phase overcurrent SOTF protection ................................................... 3-38
Figure 3.8-5 Logic of distance SOTF protection .................................................................... 3-39
Figure 3.9-1 Logic of enabling AR ........................................................................................... 3-41
Figure 3.9-2 Logic of AR block................................................................................................. 3-42
Figure 3.9-3 Logic of AR ready ................................................................................................ 3-43
Figure 3.9-4 Tripping initiating AR ........................................................................................... 3-43
3 Figure 3.9-5 CB state initiating AR .......................................................................................... 3-44
Figure 3.9-6 One-shot AR ......................................................................................................... 3-44
Figure 3.9-7 Reclosing output logic ........................................................................................ 3-45
Figure 3.9-8 Reclosing failure and success ........................................................................... 3-46
Figure 3.9-9 Transient fault ...................................................................................................... 3-47
Figure 3.9-10 Permanent fault ([79.Num]=2)........................................................................... 3-47
3-d PCS-9611S Feeder Relay

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3.1 One-phase Current Element (TCUR1P)
One-phase current element is responsible for pre-processing measured one-phase current and
calculating the magnitude and the phase angle of the one-phase current, etc. All calculated
information of one-phase current element is used for the protection logic calculation.
3.1.1 Function Description

One-phase current element has following functions:
Pre-process measured one-phase current

1.
3
2. Calculate information related to the one-phase current
3.1.2 Function Block Diagram
TCUR1P TCUR1P TCUR1P
in_ip I1P in_ip I1P in_ip I1P
It_Sec If_Sec Itf_Sec
Ang(It) Ang(If) Ang(Itf)
It.Flg_OnLoad If.Flg_OnLoad Itf.Flg_OnLoad
3.1.3 I/O Signals

No. Input signal Description
1 in_ip Measured one-phase current
No. Output signal Description
1 I1P A current data set
2 It_Sec Amplitude of traction catenary secondary current
3 Ang(It) Phase angle of traction catenary current
4 It.Flg_OnLoad A flag indicating there is load current
5 If_Sec Amplitude of feeder secondary current
6 Ang(If) Phase angle of feeder current
7 If.Flg_OnLoad A flag indicating there is load current
8 Itf_Sec Amplitude of vector difference of traction catenary current and feeder current
9 Ang(Itf) Phase angle of vector difference of traction catenary current and feeder current
10 Itf.Flg_OnLoad A flag indicating there is load current
3.1.4 Settings
One-phase current element is a basic element, for a specific application, the

displayed settings may have different prefixes in front of them.

Date: 2021-04-20
Access path: MainMenu  Settings  Global Settings  System Settings
Uni
No. Item Range Step Default Description
t
1 Prot.I1n 0~9999 1 A 1000 Rated primary value of protection phase CT
Rated secondary value of protection phase
2 Prot.I2n 1, 5 - A 1
CT
The logic setting determines that whether the
Disabled; CT polarity of the protection CT is reversed.
3 Prot.En_RevCT - - Disabled
Enabled Enabled: The CT polarity is reversed
Disabled: The CT polarity is not reversed
3
3.2 One-phase Voltage Element (TVOL1P)
One-phase voltage element is responsible for pre-processing one-phase voltage and calculating
the magnitude and the phase angle of the one-phase voltage, etc. All calculated information of one-
phase voltage element is used for the protection logic calculation.

One-phase voltage element has following functions:
1. Pre-process measured one-phase voltage
2. Calculate information related to one-phase voltage
TVOL1P TVOL1P
in_up U1P in_up U1P
Ut_Sec Uf_Sec
Ang(Ut) Ang(Uf)
3.2.3 I/O Signals

1 in_up Measured one-phase voltage
1 U1P A voltage data set
2 Ut_Sec Amplitude of the one-phase voltage (secondary value)
3 Ang(Ut) Phase angle of the one-phase voltage
4 Uf_Sec Amplitude of the one-phase voltage (secondary value)
5 Ang(Uf) Phase angle of the one-phase voltage

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3.2.4 Settings
One-phase voltage element is a basic element, for a specific application,

the displayed settings may have different prefixes in front of them.
No. Item Range Step Unit Default Description

1 Prot.U1n 0~1100 0.01 kV 10 Rated primary value of protection VT
2 Prot.U2n 1~200 0.01 V 100 Rated secondary value of protection VT 3
3.3 Distance Protection (21L)
Distance protection is the main protection for feeder and incoming feeder. The device provides
three zones independent distance protections with polygon characteristics.
3.3.1 Functions Description

For the electrified railways that are towed by electric locomotives, especially for the heavy-loaded
lines, if the traction heavy load and the regenerative restraint current are superimposed, or the
traction heavy load and the excitation inrush current are superimposed, it may cause the mal-
operation of the conventional distance protection. At the same time, no matter whether the power
factor compensation device is installed on the locomotive, there are always more or less harmonic
components in the load current of the traction electric network.
The device uses the comprehensive harmonic components of the load current as the control
quantity to adaptively adjust the operating boundary of the distance relay. If the operating boundary
of the conventional distance relay is Zset, the operating boundary of the adaptive distance relay is:
1
𝑍𝑑𝑐 = 𝑍
1 + 𝐾235 𝑠𝑒𝑡
Where:
𝐾235 = (𝐼2 + 𝐼3 + 𝐼5 )/𝐼1, it is the comprehensive harmonic ratio.
The adaptive distance relay operating boundary can be enabled/disabled via the logic setting
[21Lx.En_Hm_Restrain].

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jX
A B
X1
3
α φL
C
R
β R1
Figure 3.3-1 The operating characteristic curve of distance protection
In where:
① is the operating boundary of the adaptive distance relay;
② is the operating boundary of zone 1 of distance protection after have harmonic;
R1 is the resistance setting of zone 1 of distance protection;
X1 is the reactance setting of zone 1 of distance protection;
The device is equipped with 3 zones of distance protection, which can be enabled/disabled via
corresponding logic setting, and can be set as forward direction, reverse direction and
forward/reverse direction respectively. The second harmonic blocking function is also available,
which is controlled by the logic setting [21Lx.En_Hm2_Blk]. when the second harmonic component
is greater than the setting [21Lx.HMB.K_Hm2], the distance protection will be blocked. When VT
circuit fails, the distance protection will be blocked with no time delay.
Under auto-transformer (AT) feeding mode, the traction catenary voltage is used to calculate the
impedance. If the traction catenary VT circuit fails, the feeder voltage will be automatically switched
to be used for impedance calculation.
Distance protection can be enabled or disabled via the settings or binary input signals, for some
specific applications, distance protection needs to be blocked by the external signal, so the device
provides a function block input signal to be used to block distance protection. The enabling and
blocking logic of distance protection is shown in the figure below:

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EN 21Lx.En &
21Lx.On
SIG 21Lx.Enable
&
SIG 21Lx.Block 1 21Lx.Blocked
SIG Fail_Device
&
21Lx.Valid
Figure 3.3-2 The enabling and blocking logic of distance protection

3
SIG 21Lx.On
SIG Ip Calculate DPFC current ΔIp>[FD.DPFC.I_Set] 1 &

21Lx.Pkp
Ip>[FD.OC.I_Set]
SIG 21Lx.Valid
Figure 3.3-3 Logic diagram of the fault detector element of distance protection
Where:
Ip: If it is under direct feeding mode, it is the traction catenary current; if it is under auto-transformer
feeding mode, it is the vector difference of traction catenary current and feeder current.
21L
21Lx.Enable 21Lx.On
21Lx.Block 21Lx.Blocked
21Lx.Valid
21Lx.St
21Lx.Op
3.3.3 I/O Signals

No. Input Signal Description
1 21Lx.Enable Input signal of enabling zone x of distance protection (x=1~3)
2 21Lx.Block Input signal of blocking zone x of distance protection (x=1~3)
No. Output Signal Description
1 21Lx.On Zone x of distance protection is enabled (x=1~3)

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2 21Lx.Blocked Zone x of distance protection is blocked (x=1~3)

3 21Lx.Valid Zone x of distance protection is valid (x=1~3)
4 21Lx.St Zone x of distance protection starts (x=1~3)
5 21Lx.Op Zone x of distance protection operates (x=1~3)
3.3.4 Logic
SIG T.VTS.Alm or T.VTS.InstAlm

&
SIG F.VTS.Alm or F.VTS.InstAlm >=1
3 SET [Opt_FeedingSystem]=Direct
&
SIG 21L.HMB.Op & [21Lx.ZG.t_Op] 0 21Lx.ZG.Op
EN [21L.En_Hm_Blk]
SIG Flag.21Lx
SIG 21Lx.Pkp
Figure 3.3-4 Logic diagram of zone x of distance protection
Where:
Flag.21Lx: the measured impedance falls within the operating zone of zone x of distance protection.
3.3.5 Settings
Access path: MainMenu  Settings  Protection Settings  DistProt Settings
No. Setting Range Default Unit Step Description

Current setting of DPFC
1 FD.DPFC.I_Set 0.05 ~ 200 0.5 A 0.001
current fault detector element
Current setting of phase
2 FD.OC.I_Set 0.05 ~ 200 0.5 A 0.001
current fault detector element
The angle of directional line in
3 21L.Ang_Alpha 60~85 85 ° 1
the first quadrant
The angle of directional line in
4 21L.Ang_Beta 5~30 15 ° 1
the fourth quadrant
Angle setting of load trapezoid
characteristics, it should be
set according to the maximum
5 21L.LoadEnch.phi 5~50 30 ° 1
load area angle (φLoad_Max),
φLoad_Max+5° is
recommended.

Date: 2021-04-20
Resistance setting of load

trapezoid characteristics, it
should be set according to the
6 21L.LoadEnch.R_Set 0.5~300 10 Ω 0.001
minimum load resistance,
70%~90% minimum load
resistance is recommended.
The percent setting of the
7 21L.HMB.K_Hm2 0.1~1 0.2 - 0.001 harmonic control element of
distance protection
The current setting for
8 21L.HMB.I_Rls 2~150 20 A 0.001 releasing the harmonic control
element of distance protection
3
The logic setting for
Disabled; enabling/disabling the second
9 21Lx.En_Hm2_Blk Enabled - -
Enabled harmonic blocking function of
distance protection
enabling/disabling the
comprehensive harmonic
Disabled;
10 21Lx.En_Hm_Restrain Disabled; - - component which is used to
Enabled
adaptively adjust the operating
boundary of the impedance
relay.
Phase angle of positive-
11 21Lx.phi1_Reach 60~85 75 ° 0.1 sequence impedance for zone
x of distance protection
Forward
Direction option for zone x of
12 21Lx.DirMode Reverse Forward - -
distance protection
Forward&Reverse
The reactance setting of zone
13 21Lx.X_Set 0.5 ~ 600 5 Ω 0.001
The resistance setting of zone
14 21Lx.R_Set 0.5 ~ 300 5 Ω 0.001
The time delay setting of zone
15 21Lx.t_Op 0 ~ 100 0.1 s 0.001
Disabled;
16 21Lx.En Enabled - - enabling/disabling zone x of
Enabled
distance protection
3.4 Phase Overcurrent Protection (50/51P)

The phase overcurrent protection can be used as the backup protection for feeder and incoming
feeder.

Date: 2021-04-20

The device can provide three stages of phase overcurrent protection with independent logic. Each
stage can be independently set as definite-time characteristics or inverse-time characteristics. The
drop-out characteristics can be set as instantaneous drop-out, definite-time drop-out or inverse-
time drop-out. Users can choose whether it is blocked by the voltage control element or harmonic
control element. The phase overcurrent protection picks up when the current exceeds the current
threshold value, and operates after a certain time delay, once the fault disappears, the phase
overcurrent protection will drop-out.
Phase overcurrent protection can be enabled or disabled via the settings or binary input signals,
3 for some specific applications, overcurrent protection needs to be blocked by the external signal,
so the device provides a function block input signal to be used to block overcurrent protection. The
enabling and blocking logic of phase overcurrent protection is shown in the figure below:
EN 50/51Px.En &
50/51Px.On
SIG 50/51Px.Enable
&
SIG 50/51Px.Block ≥1 50/51Px.Blocked
SIG Fail_Device
&
50/51Px.Valid
Figure 3.4-1 The enabling and blocking logic of phase overcurrent protection
The logic diagram of the fault detector element of phase overcurrent protection is as follows:
SET Ip>0.95×[50/51Px.I_Set] &

&
SIG 50/51P.VCE.Op 0 500ms &
50/51Px.Pkp
SIG 50/51Px.On
SIG 50/51Px.Valid
&
FD.Pkp
SET [50/51Px.Opt_Trp/Alm]=Alm
Figure 3.4-2 Logic diagram of the fault detector element of phase overcurrent protection
Where:

Date: 2021-04-20
3.4.1.1 Voltage Control Element
When a fault occurs at the remote end of a feeder, the fault current is relatively small, so the voltage
control element can be adopted to increase the sensitivity for this kind of fault. Users can enable
or disable the voltage control element via the setting [50/51Px.En_Volt_Blk] (x=1~3).
For direct feeding mode, if the traction catenary voltage is lower than the low-voltage setting
[50/51P.VCE.Up], the voltage control element will operate to release phase overcurrent protection.
For auto-transformer (AT) feeding mode, if the traction catenary voltage is lower than the low-
voltage setting [50/51P.VCE.Up], the voltage control element will operate to release phase
overcurrent protection. If the traction catenary VT circuit fails, the feeder voltage will be used to
determine the low-voltage condition, when the feeder voltage is lower than the low-voltage setting 3
[50/51P.VCE.Up], the voltage control element will operate to release phase overcurrent protection.
SET Ut<[50/51P.VCE.Up] &
SET Direct feeding mode >=1

50/51P.VCE.Op
SET Auto-transformer feeding mode &
SET Ut<[50/51P.VCE.Up] &
SET VT circuit failure >=1
&
SET Uf<[50/51P.VCE.Up]
Figure 3.4-3 Logic diagram of the voltage control element of phase overcurrent protection
3.4.1.2 Harmonic Control Element
When transformer and other equipment are energized without any load, the inrush current may be
generated, which may cause the mal-operation of the phase overcurrent protection. According to
the characteristics of high secondary harmonic component in the inrush current and low secondary
harmonic component in common fault current, the secondary harmonic control element is added to
prevent the phase overcurrent protection from mal-operation due to inrush current.
When the fundamental current is greater than the setting [50/51P.HMB.I_Rls], the harmonic
blocking element of the corresponding phase is released.
The following figure shows the logic diagram of the harmonic control element of phase overcurrent
protection.

Date: 2021-04-20
SET Ip>[50/51P.HMB.I_Rls] &

50/51P.HMB.Op
SET Ip2/Ip1>[50/51P.HMB.K_Hm2]
Figure 3.4-4 Logic diagram of harmonic control element of phase overcurrent protection
Where:
Ip1: the fundamental current
Ip2: the 2nd harmonic current

3 3.4.1.3 Operation Characteristic
Phase overcurrent protection can operate without time delay or operate with a definite-time limit, it
can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and
ANSI C37.112 standards. Phase overcurrent protection can support definite-time limit, IEC & ANSI
standard inverse time limit and user-defined inverse-time limit, users can select the wanted
operating curve by the setting [50/51Px.Opt_Curve] (x=1~3), the relationship between the value of
the setting and the curve is shown in the table below.
50/51Px.Opt_Curve Time Characteristic k α c tr

ANSIE ANSI Extremely Inverse 28.2 2.0 0.1217 29.1
ANSIV ANSI Very inverse 19.61 2.0 0.491 21.6
ANSIN ANSI Normal Inverse 0.0086 0.02 0.0185 0.46
ANSIM ANSI Moderately Inverse 0.0515 0.02 0.114 4.85
ANSIDefTime ANSI Definite Time - - - -
ANSILTE ANSI Long Time Extremely Inverse 64.07 2.0 0.25 30
ANSILTV ANSI Long Time Very Inverse 28.55 2.0 0.712 13.46
ANSILT ANSI Long Time Inverse 0.086 0.02 0.185 4.6
IECN IEC Normal Inverse 0.14 0.02 0 -
IECV IEC Very inverse 13.5 1.0 0 -
IEC IEC Inverse 0.14 0.02 0 -
IECE IEC Extremely inverse 80.0 2.0 0 -
IECST IEC Short-time inverse 0.05 0.04 0 -
IECLT IEC Long-time inverse 120.0 1.0 0 -
IECDefTime IEC Definite Time - - - -
UserDefine Programmable
Only when the setting [50/51Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-
time characteristic is selected, the settings [50/51Px.K], [50/51Px.C] and [50/51Px.Alpha] are useful,
the inverse-time operating curve is determined by the three settings.
 Without time delay
When I > Ip , phase overcurrent protection operates immediately.
 Definite-time characteristic

Date: 2021-04-20
When I > Ip , the protection operates with a time delay of top (i.e. the value of the setting
[50/51Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op 3
IP I
Figure 3.4-5 Definite-time operation characteristic curve of phase overcurrent protection
 Inverse-time characteristic
When I > Ip , the inverse-time accumulator begins to accumulate, and the operating time is
affected by the applied current I . The operating time will decrease with the current increasing,
but the operating time shall not less than tmin , i.e. the setting [50/51Px.tmin] (x=1~3). The inverse-
time operation characteristic equation is:
 k 
t 
 c   TMS
 ( I / I P )  1 
Where:
Ip is the current setting [50/51Px.I_Set];
TMS is the inverse-time time multiplier, i.e. the setting [50/51Px.TMS];
k is the inverse-time coefficient K, i.e. the setting [50/51Px.K];

c is the inverse-time coefficient C, i.e. the setting [50/51Px.C];
 is the inverse-time coefficient Alpha, i.e. the setting [50/51Px.Alpha];
I is the measured current.
The inverse-time operation characteristic curve is shown as below:

Date: 2021-04-20
3 t min
IP ID I
Figure 3.4-6 Inverse-time operation characteristic curve of phase overcurrent protection
When the applied current is not a fixed value, but changes with time, the operating behaviour of
the protection is shown in the following equation:
T0
1
 t ( I )dt
0
1
Where:
T0 is the operating time of the protection element;
t(I) is the theoretical operating time when the current is I.
3.4.1.4 Drop-out Characteristic
The supported drop-out characteristics of the phase overcurrent protection include instantaneous
drop-out, definite-time drop-out and ANSI inverse-time drop-out.
When the operating curve is selected as definite-time, IEC inverse-time or user-defined inverse-
time characteristic, the drop-out characteristic can only be selected as instantaneous drop-out or
definite-time drop-out, if inverse-time drop-out is selected, the alarm signal "Fail_Settings" will be
issued and the device will be blocked.
When the operating curve is selected as ANSI inverse-time characteristic, the drop-out
characteristic can be selected as instantaneous drop-out, definite-time drop-out and ANSI inverse-
time drop-out.
 Instantaneous drop-out
When I <0.95* Ip , the protection drops out immediately.
 Definite-time drop-out

Date: 2021-04-20
When I <0.95* Ip , the protection drops out with a time delay of tdr (i.e. the value of the setting
[50/51Px.t_DropOut]), and the drop-out characteristic curve is shown in the following figure:
Start time
I>Ip
Start
signal
3
Operating
signal
Protection
Operating threshold operate
Operating
counter
t dr t dr t dr
Dropout time setting
Dropout time
Dropout time
Figure 3.4-7 Definite-time drop-out characteristic of phase overcurrent protection
 Inverse-time drop-out
When I > Ip , the inverse-time operating accumulator begins to accumulate, the accumulated
value after tp (Assuming tp is less than the theoretical operating time) is calculated according
to the following equation:
tp
1
I tp   dt
0
t ( I )
At this time, if I <0.95* Ip , the protection element starts drop-out, and the drop-out characteristic
meets the following equation:
TR
1
I tp  t
0 R (I )
dt  0
Where:
TR is the drop-out time;

tR( I ) is the drop-out characteristic equation

Date: 2021-04-20
When I <0.95* Ip , the inverse-time drop-out characteristic equation is as follows:
 tr 
tR   2
 TMS
1  ( I / I P ) 
Where:
Ip is the current setting [50/51Px.I_Set];
TMS is the inverse-time factor, i.e. the setting [50/51Px.TMS];
tr is the drop-out time coefficient, it is the drop-out time required for the current to drop to 0 after
3 the protection operates.
I is the measured current.
When 0.95* Ip < I < Ip , the accumulator will neither accumulate nor drop out
The inverse time drop-out characteristic curve is shown in the figure below.
tr
IP I
Figure 3.4-8 Inverse-time drop-out characteristic curve of phase overcurrent protection
The correspondence between the start signal, operating signal, and operating accumulator in the
inverse-time drop-out characteristic is shown in the figure below:

Date: 2021-04-20
Start time
I>Ip
Start
signal
Operating
signal
3
Protection
Operating
counter
tr Dropout time coefficient

Dropout time
Dropout time
Figure 3.4-9 Inverse-time drop-out characteristic of phase overcurrent protection
50/51P
50/51Px.Enable 50/51Px.On
50/51Px.Block 50/51Px.Blocked
50/51Px.Valid
50/51Px.St
50/51Px.Op
50/51Px.Alm
3.4.3 I/O Signal

Stage x of phase overcurrent protection enabling input, it is triggered from
1 50/51Px.Enable
binary input or programmable logic etc. (x=1~3)
Stage x of phase overcurrent protection blocking input, it is triggered from
2 50/51Px.Block
binary input or programmable logic etc. (x=1~3)
1 50/51Px.On Stage x of phase overcurrent protection is enabled
2 50/51Px.Blocked Stage x of phase overcurrent protection is blocked
3 50/51Px.Valid Stage x of phase overcurrent protection is valid

Date: 2021-04-20
4 50/51Px.St Stage x of phase overcurrent protection starts

5 50/51Px.Op Stage x of phase overcurrent protection operates
6 50/51Px.Alm Stage x of phase overcurrent protection alarms
3.4.4 Logic
SET Ip>[50/51Px.I_Set]
SIG 50/51P.VCE.Op >=1 &
EN [50/51Px.En_Volt_Blk]
50/51Px.St
3 SIG 50/51P.HMB.Op & & Timer

t
&
t
EN [50/51Px.En_Hm_Blk] 50/51Px.Op
SIG 50/51Px.Pkp
SET [50/51Px.Opt_Trp/Alm]=Trp
&
50/51Px.Alm
SET [50/51Px.Opt_Trp/Alm]=Alm
Figure 3.4-10 Logic diagram of phase overcurrent protection
3.4.5 Settings
Access path: MainMenu  Settings  Protection Settings  OC Settings
No. Settings Range Default Unit Step Description

The low voltage
blocking setting of the
1 50/51P.VCE.Up 10~100 70 V 0.001 voltage control element
of phase overcurrent
protection
The percent setting of
the harmonic control
2 50/51P.HMB.K_Hm2 0.1~1 0.2 - 0.001
element of phase
overcurrent protection
releasing the harmonic
3 50/51P.HMB.I_Rls 2~150 20 A 0.001 control element of
phase overcurrent
protection
The current setting of
4 50/51Px.I_Set 0.05~200 15 A 0.001 stage x of phase

Date: 2021-04-20

The operating time
setting of stage x of
5 50/51Px.t_Op 0 ~100 0.1 s 0.001
phase overcurrent
protection
The drop-out time
6 50/51Px.t_DropOut 0 ~100 0 s 0.001
phase overcurrent
protection
enabling/disabling the 3
voltage control element
of stage x of phase
Disabled: stage x of
phase overcurrent
Disabled;
7 50/51Px.En_Volt_Blk Disabled - - protection is not
Enabled
controlled by the
Enabled: stage x of
phase overcurrent
protection is controlled
by the voltage control
element
harmonic control
element of stage x of
phase overcurrent
protection
phase overcurrent
Disabled;
8 50/51Px.En_Hm_Blk Disabled - - protection is not
Enabled
controlled by the
harmonic control
element
Enabled: stage x of
phase overcurrent
by the harmonic control
element

Date: 2021-04-20

Disabled; enabling/disabling the
9 50/51Px.En Enabled - -
Enabled stage 1 of phase
Enabling stage x of
phase overcurrent
Trp; protection operate to
10 50/51Px.Opt_Trp/Alm Trp - -
Alm trip or alarm.
Trp: for tripping purpose
3 Alm: for alarm purpose

ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
ANSILTE; The setting for selecting
ANSILTV; the inverse-time
ANSILT; operation characteristic
11 50/51Px.Opt_Curve IECDefTime - -
IECN; curve of stage x of
IECV; phase overcurrent
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine
The setting for selecting
the inverse-time drop-
out characteristic curve
of stage x of phase
Inst; overcurrent protection
12 50/51Px.Opt_Curve_DropOut DefTime; Inst - - Inst: instantaneous
IDMT drop-out
DefTime: definite-time
drop-out
IDMT: inverse-time
drop-out
The time multiplier
13 50/51Px.TMS 0.04~ 20 1 - 0.001
phase overcurrent
protection

Date: 2021-04-20

The minimum operating
time setting of stage x
14 50/51Px.tmin 0 ~10 0.02 s 0.001
protection
The constant “k” of the
customized inverse-
time operation
15 50/51Px.K 0.001~120 0.14 - 0.0001
characteristic of stage x
protection
3
The constant “α” of the
customized inverse-
time operation
16 50/51Px.Alpha 0.01 ~3 0.02 - 0.0001
protection
The constant “C” of the
customized inverse-
time operation
17 50/51Px.C 0 ~1 0 - 0.0001
protection
3.5 DPFC Overcurrent Protection (50/51D)
DPFC is the abbreviation of “deviation of power frequency component”. The

DPFC current is the difference between the fault current and the current of
one cycle before the fault.

When a high-resistance grounding fault occurs in the traction catenary, the measured impedance
is several to ten times higher than that of a conventional fault, and the distance protection cannot
operate correctly.
In order to prevent the distance protection and phase instantaneous overcurrent protection from
refusing to operate in the event of a high-resistance grounding fault happens. The device adopts
DPFC (deviation of power frequency component) overcurrent protection that with higher harmonics
suppression function as the backup protection. When the current higher harmonics ratio is larger
than the setting, the higher harmonics suppression protection will operate. The protection principle
is as follows:
∆𝐼 = ∆𝐼1 − 𝐾 × 𝐾235 × 𝐼1_𝑎𝑓𝑡𝑒𝑟

Date: 2021-04-20
= 𝐼1_𝑎𝑓𝑡𝑒𝑟 − 𝐼1_𝑏𝑒𝑓𝑜𝑟𝑒 − 𝐾 × 𝐾235 × 𝐼1_𝑎𝑓𝑡𝑒𝑟
≥ (1 + 𝐾235 ) × ∆𝐼𝑠𝑒𝑡
∆𝐼 ≥ (1 + 𝐾235 ) × ∆𝐼𝑠𝑒𝑡
Where:
𝐼1_𝑏𝑒𝑓𝑜𝑟𝑒 , 𝐼1_𝑎𝑓𝑡𝑒𝑟 is the power frequency component of the current of one cycle before the fault.
𝐼1_𝑎𝑓𝑡𝑒𝑟 is the power frequency component of the fault current.
𝐾235 = (𝐼2 + 𝐼3 + 𝐼5 )/𝐼1, it is the comprehensive harmonic ratio.
3 𝐾 = 𝐼𝑛𝑡(10 × 𝐾235 ), it is the adaptive suppression coefficient
It can be seen from the analysis:
Load→Fault: If the fault current is considered to be a pure sine wave, then K235 =0, so the current
operating quantity of the relay is the deviation of power frequency component.
Load→Load: The greater the comprehensive harmonic ratio of the load current, the greater the K
value, the smaller the operating quantity of the relay, the larger the operating boundary of the relay,
and the more difficult it is for the relay to mal-operate.
Harmonic suppression function can be enabled/disabled via the logic setting

[50/51D.En_Hm_Restrain].
The second harmonic blocking function is available for DPFC overcurrent protection (which is
controlled by the logic setting [50/51D.En_Hm2_Blk]). When the second harmonic ratio is greater
than the setting [50/51D.HMB.K_Hm2], the DPFC overcurrent protection is blocked.
DPFC overcurrent protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, theprotection needs to be blocked by the external signal, so the device
provides a function block input signal to be used to block DPFC overcurrent protection. The
enabling and blocking logic of phase overcurrent protection is shown in the figure below:
EN 50/51D.En &
50/51D.On
SIG 50/51D.Enable
&
SIG 50/51D.Block 1 50/51D.Blocked
SIG Fail_Device
&
50/51D.Valid
Figure 3.5-1 The enabling and blocking logic of DPFC overcurrent protection
The logic diagram of the fault detector element of DPFC overcurrent protection is as follows:

Date: 2021-04-20
SET ΔI 0.95 (1+K235)·ΔIdz &

0 500ms &
SIG 50/51D.On 50/51D.Pkp
SIG 50/51D.Valid
Figure 3.5-2 Logic diagram of the fault detector element of DPFC overcurrent protection
50D 3
50/51D.Enable 50/51D.On
50/51DBlock 50/51D.Blocked
50/51D.Valid
50/51D.St
50/51D.Op
3.5.3 I/O Signal

DPFC overcurrent protection enabling input, it is triggered from binary
1 50/51D.Enable
input or programmable logic etc.
DPFC overcurrent protection blocking input, it is triggered from binary input
2 50/51D.Block
or programmable logic etc.
1 50/51D.On DPFC overcurrent protection is enabled
2 50/51D.Blocked DPFC overcurrent protection is blocked
3 50/51D.Valid DPFC overcurrent protection is valid
4 50/51D.St DPFC overcurrent protection starts
5 50/51D.Op DPFC overcurrent protection operates
3.5.4 Logic
SIG 50/51D.HMB.Op &
EN [50/51D.En_Hm2_Blk]
SIG ΔI (1+K235)·ΔIdz & &

[50/51D.t_Op] 0 50/51D.Op
EN [50/51D.En]
SIG 50/51D.Pkp
Figure 3.5-3 Logic diagram of DPFC overcurrent protection

Date: 2021-04-20
3.5.5 Settings
Access path: MainMenu  Settings  Protection Settings  OCD Settings

1 50/51D.En_Hm2_Blk Disabled - -
Enabled harmonic blocking function of DPFC
The second harmonic coefficient
setting, which is ueds for the second
3
2 50/51D.HMB.K_Hm2 0.1~1 0.2 - 0.001
harmonic blocking function of DPFC
Disabled; enabling/disabling the harmonic
3 50/51D.En_Hm_Restrain Disabled - -
Enabled suppression function of DPFC
The DPFC current setting of DPFC
4 50/51D.I_Set 0.05~200 15 A 0.001
The time delay setting of DPFC
5 50/51D.t_Op 0 ~ 100 0.1 s 0.001
Disabled;
6 50/51D.En Enabled - - enabling/disabling the DPFC
Enabled
3.6 逆功率保护 (32R)
3.6.1 功能描述
本装置提供两段逆功率保护。当系统中出现功率反向流动，功率幅值高于设定门槛，逆功率保
护动作。逆功率保护为定时限动作特性，返回特性默认为立即返回。逆功率保护可以经外部信号投
入、闭锁。
逆功率保护可经定值投退，当【功能投入】控制字为 1，且“功能使能输入”信号为 1 时，逆功

率保护功能投入。对于某种特定应用中，逆功率保护需要经外部信号闭锁，提供了“功能闭锁输入”
信号来闭锁逆功率保护。
逆功率保护功能投入、闭锁逻辑如下图所示：

Date: 2021-04-20
EN 功能投入 & 功能投入
SIG 功能使能输入
&
功能闭锁
SIG 功能闭锁输入 ≥1
SIG 装置闭锁
& 功能有效
图 3.6-1 逆功率保护功能投入、闭锁 3
逆功率保护整组启动逻辑图如下所示：
SET 功率幅值>返回值 &
SI G 功率方向为反
逆功率保护整组启动
& 0ms 500ms

&
SET U < U_set &
& 装置整组启动
SET Imax< I_set
SI G 功能投入
SI G 功能有效
EN 报警投入
图 3.6-2 逆功率保护整组启动
其中：
逆功率保护功率计算公式为 P  U * Ip 。
返回值为 0.95 乘以【功率定值】。
U 为电压值，在 AT 模式下，默认采用 T 相电压，T 相 PT 断线时自动切换为 F 相电压。

Ip 为电流值，在直供模式下取馈线电流，在 AT 模式下取 Itf 。
I max 为电流最大值，在直供模式下取馈线电流，在 AT 模式下取 Itf 。

Uset 为电压闭锁定值， Iset 为电流闭锁定值。
3.6.1.1 动作特性
逆功率保护经定时限延时动作，动作特性满足 IEC60255-3 以及 ANSI C37.112 标准。 P  0 并
且 | P | P Set 时，经过延时定值 top 后保护动作，动作特性曲线如下图所示：

Date: 2021-04-20
top
P P_Set 0
图 3.6-3 逆功率保护定时限动作特性曲线
3.6.1.2 返回特性
逆功率保护返回特性支持立即返回。
对于立即返回特性，当 P  0 或 | P | 0.95 * P Set 时，动作元件立即返回。
3.6.2 功能模块
32R
32Rx.Enable 32Rx.On
32Rx.Block 32Rx.Blocked
32Rx.Valid
32Rx.St
32Rx.Op
32Rx.Alm
3.6.3 输入/输出信号
表 3.6-1 逆功率保护输入/输出信号
序配置属
输入信号描述
号性
1 32Rx.Enable 使能输入可配
2 32Rx.Block 闭锁输入可配
序 .输出信号描述

Date: 2021-04-20
序配置属
输入信号描述
号性
号
1 32Rx.On 功能投入可配
2 32Rx.Blocked 功能闭锁可配
3 32Rx.Valid 功能有效可配
4 32Rx.St 启动可配
5 32Rx.Op 动作可配
6 32Rx.Alm 报警可配
3.6.4 逻辑 3
SET 功率幅值>定值 &
SIG 功率方向为反
逆功率保护启动
SET U < U_set &
& Timer
SET Imax < I_set
t
& 逆功率保护动作
SIG 装置整组启动
& 逆功率保护报警
EN 报警投入
图 3.6-4 逆功率保护逻辑图
3.6.5 定值
表 3.6-2 逆功率保护定值单
序默认
定值范围单位步长描述
号值
1 逆功率保护电压闭锁定值 5~120 5 V 0.001 电压闭锁定值
2 逆功率保护电流闭锁定值 0.01~1 0.1 p.u. 0.001 电流闭锁定值，按照标幺值整定
3 逆功率保护Ⅰ段功率定值 0.1~10 0.15 p.u. 0.001 按照标幺值整定
0.01 0.1 s 0.001
4 逆功率保护Ⅰ段时间定值
~100
退出投入 -
5 逆功率保护Ⅰ段投入 0：退出；1：投入
投入
跳闸跳闸 -
6 逆功率保护Ⅰ段报警投入 0：跳闸；1 告警
告警
7 逆功率保护Ⅱ段功率定值 0.1~2 1 p.u. 0.001 按照标幺值整定

Date: 2021-04-20
序默认
定值范围单位步长描述
号值
0.01 0.1 s 0.001
8 逆功率保护Ⅱ段时间定值
~100
退出投入 -
9 逆功率保护Ⅱ段投入 0：退出；1：投入
投入
跳闸跳闸 -
10 逆功率保护Ⅱ段报警投入 0：跳闸；1 告警
告警
3 3.7 Undervoltage Protection (27P)

The device can provide two stages of phase undervoltage protection with independent logic. When
the voltage drops in the system and it is lower than the voltage threshold, phase undervoltage
protection will operate.
Taking into account that the role of undervoltage protection is to remove the running device from
the system, but in order to prevent that undervoltage protection is always operating when it is not
charged, the breaker closed position check criterion is added, users can choose to detect the
breaker position, current or no-check as the releasing condition for the protection.
In addition, the undervoltage protection also provides the alarm function, prompting the voltage
drop of the system, it allows users to find the cause timely, and preventing further deterioration of
the fault. Each stage of phase undervoltage protection can be independently set as definite-time
characteristics and supported drop-out characteristics include instantaneous drop-out and definite-
time drop-out.
The breaker closed position check mode is configured via the setting [27P.Opt_LogicMode], it
includes:
[27P.Opt_LogicMode]=None: no-check;
[27P.Opt_LogicMode]=Curr: check the current;
[27P.Opt_LogicMode]=CBPos: check the breaker position;
[27P.Opt_LogicMode]=CurrAndCBPos: check the current and the breaker position;
[27P.Opt_LogicMode]=CurrOrCBPos: check the current or the breaker position.
Undervoltage protection can be enabled or disabled via the settings or binary input signals, for
some specific applications, undervoltage protection needs to be blocked by the external signal, so
the device provides a function block input signal to be used to block undervoltage protection. The
enabling and blocking logic of undervoltage protection is shown in the figure below:

Date: 2021-04-20
EN 27Px.En &
27Px.On
SIG 27Px.Enable
&
SIG 27Px.Block 1 27Px.Blocked
SIG Fail_Device
&
27Px.Valid
Figure 3.7-1 The enabling and blocking logic of phase undervoltage protection
3
The logic diagram of the fault detector element of phase undervoltage protection is as follows:
SET Ut<[U_DropOut] &
SET [Opt_FeedingSystem]=Direct >=1

Pickup voltage criterion
SET [Opt_FeedingSystem]=AT &
SET Ut<[U_DropOut] &
SET Uf<[U_DropOut]
SET [27P.Opt_LogicMode]=None
SET [27P.Opt_LogicMode]=Curr & >=1

>=1
SIG Ip > 0.04In Auxiliary criterion
SET [27P.Opt_LogicMode]=CBPos &
SIG CB closed position
>=1
&
>=1
SET [27P.Opt_LogicMode]=CurrOrCBPos
&
&
SET [27P.Opt_LogicMode]=CurrAndCBPos

Date: 2021-04-20
SIG Pickup voltage criterion

& 27Px.Pkp
SIG Auxiliary criterion 0 500ms &
SIG 27Px.On
&
FD.Pkp
SIG 27Px.Valid
SET [27Px.Opt_Trp/Alm]=Alm
Figure 3.7-2 Logic diagram of the fault detector element of phase undervoltage protection
Where:
3 U_DropOut: the drop-out voltage value, i.e. [27Px.K_DropOut]*[27Px.U_Set]
3.7.1.1 Operation Characteristic
When U < Up , the protection operates with a time delay of top (i.e. the value of the setting
[27Px.t_Op]), and the operation characteristic curve is shown in the following figure:
t op
Up U
Figure 3.7-3 Definite-time operation characteristic curve of phase undervoltage protection
3.7.1.2 Drop-out Characteristic
The supported drop-out characteristics of the undervoltage protection include instantaneous drop-
out and definite-time drop-out.
 Instantaneous drop-out
When U >[27Px.K_DropOut]* Up , the protection drops out immediately.
 Definite-time drop-out
When U >[27Px.K_DropOut]* Up , the protection drops out with a time delay of tdr (i.e. the value
of the setting [27Px.t_DropOut]), and the drop-out characteristic curve is shown in the following
figure:

Date: 2021-04-20
Start time
U<Up
Start
signal
Operating
signal
3
Protection
Operating
counter
t dr t dr t dr
Dropout time setting
Dropout time
Dropout time
Figure 3.7-4 Definite-time drop-out characteristic of undervoltage protection
27P
27Px.Enable 27Px.On
27Px.Block 27Px.Blocked
27Px.Valid
27Px.St
27Px.Op
27Px.Alm
3.7.3 I/O Signal

Stage x of phase undervoltage protection enabling input, it is triggered from binary
1 27Px.Enable
input or programmable logic etc. (x=1~2)
Stage x of phase undervoltage protection blocking input, it is triggered from binary
2 27Px.Block
input or programmable logic etc. (x=1~2)

Date: 2021-04-20
1 27Px.On Stage x of phase undervoltage protection is enabled

2 27Px.Blocked Stage x of phase undervoltage protection is blocked
3 27Px.Valid Stage x of phase undervoltage protection is valid
4 27Px.St Stage x of phase undervoltage protection starts
5 27Px.Op Stage x of phase undervoltage protection operates
6 27Px.Alm Stage x of undervoltage protection alarms
3.7.4 Logic
SET Ut<[27Px.U_Set] &

3 SET [Opt_FeedingSystem]=Direct >=1
Voltage criterion
SET [Opt_FeedingSystem]=AT &
SET Ut<[27Px.U_Set] &
SET Uf<[27Px.U_Set]
SIG Voltage criterion 27Px.St

&
SIG Auxiliary criterion &
[27Px.t_Op] [27Px.t_DropOut]
SIG 27Px.On
SIG 27Px.Pkp
&
27Px.Op
SET [27Px.Opt_Trp/Alm]=Trp
&
27Px.Alm
SET [27Px.Opt_Trp/Alm]=Alm
Figure 3.7-5 Logic diagram of phase undervoltage protection
Where:
Auxiliary criterion: please refer to Figure 3.7-2.
3.7.5 Settings
Access path: MainMenu  Settings  Protection Settings  UV Settings

The voltage setting of
1 27Px.U_Set 5~120 80 V 0.001 stage x of phase
undervoltage protection
The drop-out coefficient
2 27Px.K_DropOut 1~1.2 1.03 - 0.001 of stage x of phase

Date: 2021-04-20

The operating time setting
3 27Px.t_Op 0.1 ~100 1 s 0.001 of stage x of phase
The drop-out time setting
4 27Px.t_DropOut 0 ~100 0 s 0.001 of stage x of phase
5 27Px.En Enabled - -
Enabled stage x of phase
undervoltage protection 3
Enabling stage x of phase
Trp;
6 27Px.Opt_Trp/Alm Trp - - operate to trip or alarm.
Alm
Alm: for alarm purpose
3.8 Breaker Failure Protection (50BF)

When a fault happens to the power system, the device will operate to trip the circuit breaker, and
the fault will be isolated by opening the circuit breaker. If the circuit breaker fails to open within the
certain time due to some abnormalities (for example, low tripping pressure), the fault may cause
system stability being destroyed or electrical equipment being damaged. Breaker failure protection
is adopted to issue a backup tripping command to trip adjacent circuit breakers, and isolate the
fault as requested by the device.
According to the tripping information from the device and the auxiliary information (the current and
the position) of target circuit breaker, breaker failure protection constitutes the criterion to
discriminate whether the target circuit fails to open. If the criterion is confirmed, breaker failure
protection will operate to trip the target circuit breaker with the time delay [50BF.t_ReTrp], trip it
again with the time delay [50BF.t1_Op] and trip the adjacent circuit breakers with the time delay
[50BF.t2_Op]. As a special backup protection, breaker failure protection can quickly isolate the fault,
reduce the affected range by the fault, keep system stability and prevent generators, transformers
and other primary equipment from seriously damaged.

For breaker failure protection, re-trip and two time delays are available.
3.8.1.1 Re-trip
When breaker failure protection receives initiating signal of tripping and phase overcurrent element
of any phase operates, the device will issue tripping command to re-trip the target circuit breaker
with the time delay [50BF.t_ReTrp].
3.8.1.2 First Time Delay
As similar as re-trip, the device will operate to re-trip the target circuit breaker again with the time

Date: 2021-04-20
delay [50BF.t1_Op] when the relevant operating criterion is satisfied.
3.8.1.3 Second Time delay
As similar as re-trip, the device will operate to trip the adjacent circuit breakers with the time delay
[50BF.t2_Op] when the relevant operating criterion is satisfied.
3.8.1.4 Current Criterion
𝐼𝑝 > [50𝐵𝐹. 𝐼_𝑆𝑒𝑡]
For some special faults (for example, mechanical protection or undervoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
3 order to make breaker failure protection can also operate under the above situation, an input signal
"50BF.ExTrp_WOI" is equipped to initiate breaker failure protection, once the input signal is
energized, normally closed auxiliary contact of circuit breaker is chosen in addition to breaker failure
current check to trigger breaker failure timer. The device takes current as priority with CB auxiliary
contact "50BF.52b" as an option criterion for breaker failure check.
When the initiating signal of breaker failure protection is energized for longer than 10s, an alarm
signal "50BF.Alm_Init" will be issued, and will drop out with a time delay of 10s.
50BF
50BF.Enable 50BF.On
50BF.Block 50BF.Blocked
50BF.ExTrp 50BF.Valid
50BF.ExTrp_WOI 50BF.St
50BF.Op_ReTrp
50BF.Op_t1
50BF.Op_t2
50BF.Alm_Init
3.8.3 I/O Signals

Breaker failure protection enabling input, it is triggered from binary input or
1 50BF.Enable
programmable logic etc.
Breaker failure protection blocking input, it is triggered from binary input or
2 50BF.Block
3 50BF.ExtTrp Input signal of initiating breaker failure protection
Input signal of initiating breaker failure protection with the position check of
4 50BF.ExtTrp_WOI
the circuit breaker

Date: 2021-04-20
1 50BF.On Breaker failure protection is enabled.

2 50BF.Blocked Breaker failure protection is blocked.
3 50BF.Valid Breaker failure protection is valid.
4 50BF.St Breaker failure protection starts
5 50BF.Op_ReTrp Breaker failure protection operates to re-trip three-phases circuit breaker.
6 50BF.Op_t1 Breaker failure protection operates with the time delay [50BF.t1_Op].
7 50BF.Op_t2 Breaker failure protection operates with the time delay [50BF.t2_Op].
8 50BF.Alm_Init The initiating signal of breaker failure protection is energized consistently.
3.8.4 Logic
EN [50BF.En] & 3
50BF.On
SIG 50BF.Enable
&
SIG 50BF.Block >=1 50BF.Blocked
SIG Fail_Device
&
50BF.Valid
Figure 3.8-1 Logic of enabling breaker failure protection
SIG 50BF.ExtTrp 10s 10s >=1
SIG 50BF.ExtTrp_WOI 10s 10s
&
EN [50BF.En_Alm_Init] 50BF.Alm_Init
SIG 50BF.Valid
Figure 3.8-2 Logic of breaker failure initiating signal abnormality

Date: 2021-04-20
SIG 50BF.Valid &
SIG 50BF.Alm_Init
EN [50BF.En_ReTrp] &
[50BF.t_ReTrp] 0 50BF.Op_ReTrp
EN [50BF.En_Ip]
&
SET Ip>[50BF.I_Set]
SIG 50BF.ExtTrp >=1

&
SIG 50BF.ExtTrp_WOI [50BF.t1_Op] 0 50BF.Op_t1
&
3
EN [50BF.En_CB_Ctrl]
SIG 50BF.52b >=1

50BF.St
EN [50BF.En_t1]
&
[50BF.t2_Op] 0 50BF.Op_t2
EN [50BF.En_t2]
Figure 3.8-3 Logic of breaker failure protection
Where:
50BF.52b: Input signal of open position of circuit breaker.
3.8.5 Settings
Access path: MainMenu  Settings  Protection Settings  BFP Settings

The phase current setting of breaker
1 50BF.I_Set 0.05~200 1.000 A 0.001
failure protection
The re-trip time delay of breaker failure
2 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
3 50BF.t1_Op 0~20 0.100 s 0.001
protection
The second time delay of breaker failure
4 50BF.t2_Op 0~20 0.200 s 0.001
protection
Disabled Enabling/disabling breaker failure
5 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
6 50BF.En_ReTrp Enabled - -
Enabled breaker failure protection
Disabled Enabling/disabling the first time delay of
7 50BF.En_t1 Disabled - -
Disabled Enabling/disabling the second time delay
Enabled of breaker failure protection

Date: 2021-04-20
Enabling/disabling phase overcurrent

Disabled
9 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
three-phases initiating signal
Enabling/disabling breaker failure
50BF.En_CB_Ctr Disabled
10 Disabled - - protection be initiated by normally closed
l Enabled
contact of circuit breaker
50BF.En_Alm_Ini Disabled Enabling/disabling abnormality check of
11 Disabled - -
t Enabled breaker failure initiating signal
3.9 Switch-on-to-Fault Protection (SOTF)

When the line is put into operation or the power is restored, the circuit breaker is necessary to be 3
closed automatically, it is possible to switch on to a permanent fault. Switch-on-to-fault (SOTF)
protection can quickly operate to remove the fault and reduce the impact of the fault on the system.

The device can provide one stage of phase overcurrent SOTF protection and one stage of distance
SOTF protection. The SOTF protection is with definite-time delay characteristic and instantaneous
drop-out characteristic, it can be enabled or blocked by the external binary input.
The SOTF protection can be enabled or disabled via the settings or binary input signals, for some
specific applications, the protection needs to be blocked by the external signal, so the device
provides a function block input signal to be used to block SOTF protection. The enabling and
blocking logic of the SOTF protection is shown in the figure below:

Date: 2021-04-20
EN 50PSOTF.En &
50PSOTF.On
SIG 50PSOTF.Enable
&
SIG 50PSOTF.Block ≥1 50PSOTF.Blocked
SIG Fail_Device
&
50PSOTF.Valid
3
EN 21SOTF.En &
21SOTF.On
SIG 21SOTF.Enable
&
SIG 21SOTF.Block 1 21SOTF.Blocked
SIG Fail_Device
&
21SOTF.Valid
Figure 3.9-1 The enabling and blocking logic of SOTF protection
The SOTF protection must be initiated by auto-reclosing signal or manual closing signal, the
initiating time can be set by the setting [STOF.t_En]. After the acceleration condition is satisfied,
the SOTF protection will operate with a time delay of [50PSOTF.t_Op]/[21SOTF.t_Op].
If the current changes from “no” to “have”, and the breaker position changes from “open” to “closed”,
it will be judged that the acceleration condition for manual closing is satisfied. Then the manual
closing signal will be kept for a certain time which is determined by the setting [SOTF.t_En], and
SOTF protection will be enabled.
Second harmonic blocking can be selected by the setting

[50PSOTF.En_Hm2_Blk]/[21SOTF.En_Hm2_Blk] to prevent the mal-operation due to inrush
current. The harmonic blocking characteristic of the phase overcurrent SOTF protection is
consistent with that of phase overcurrent protection.
The harmonic blocking characteristic of the distance SOTF protection is consistent with that of
distance protection.
In order to improve the reliability, phase overcurrent SOTF protection can select voltage control
element. Users can enable or disable the voltage control element via the logic setting
[50PSOFT.En_Volt_Blk]. The voltage control element of phase overcurrent SOTF protection is
consistent with that of phase overcurrent protection.

Date: 2021-04-20
50PSOTF 21SOTF
50PSOTF.Enable 50PSOTF.On 21SOTF.Enable 21SOTF.On
50PSOTF.Block 50PSOTF.Blocked 21SOTF.Block 21SOTF.Blocked
SOTF.in_mancls 50PSOTF.Valid SOTF.in_mancls 21SOTF.Valid
50PSOTF.Op 21SOTF.Op
50PSOTF.St 21SOTF.St
3
3.9.3 I/O Signals
Phase overcurrent SOTF protection enabling input, it is triggered from binary
1 50PSOTF.Enable
Phase overcurrent SOTF protection blocking input, it is triggered from binary
2 50PSOTF.Block
Distance SOTF protection enabling input, it is triggered from binary input or
3 21SOTF.Enable
Distance SOTF protection blocking input, it is triggered from binary input or
4 21SOTF.Block
Manual closing input signal, it is triggered from binary input or programmable
5 SOTF.in_mancls
logic etc.
1 50PSOTF.On Phase overcurrent SOTF protection is enabled.
2 50PSOTF.Blocked Phase overcurrent SOTF protection is blocked
3 50PSOTF.Valid Phase overcurrent SOTF protection is valid
4 50PSOTF.Op Phase overcurrent SOTF protection operates.
5 50PSOTF.St Phase overcurrent SOTF protection starts.
6 21SOTF.On Distance SOTF protection is enabled.
7 21SOTF.Op Distance SOTF protection operates.
8 21SOTF.Blocked Distance SOTF protection is blocked
9 21SOTF.Valid Distance SOTF protection is valid
10 21SOTF.St Distance SOTF protection starts.
3.9.4 Logic
SIG 79.Close: 0->1 0 [SOTF.t_En] AR signal
Figure 3.9-2 Logic of auto-reclosing signal

Date: 2021-04-20
SIG Breaker open position &
SIG FD.Pkp
&
SIG FD.Pkp &
SIG No current &
SET [SOTF.Opt_Mode_ManCls]=CBPos
SIG FD.Pkp &

& >=1
SIG SOTF.in_mancls 0 [SOTF.t_En] Manual closing signal
3 SET [SOTF.Opt_Mode_ManCls]=ManClsBI
>=1
&
SET [SOTF.Opt_Mode_ManCls]=ManClsBI
/CBPos
Figure 3.9-3 Logic of manual closing signal
If current is not detected, and the breaker is open, it will be judged that the acceleration condition
for manual closing is satisfied.
SIG AR signal >=1
SIG Manual closing signal
SET Ip>[50PSOTF.I_Set]
SIG Ip 2nd Hm Detect & &
EN [50PSOTF.En_Hm2_Blk]
SIG 50/51P.VCE.Op >=1
EN [50/51PSOTF.En_Volt_Blk]
&
[50PSOTF.t_Op] 0 50PSOTF.Op
SIG 50PSOTF.Valid
50PSOTF.St
Figure 3.9-4 Logic of phase overcurrent SOTF protection

Date: 2021-04-20
SIG Ip 2nd Hm Detect &
SIG [21SOTF.En_Hm2_Blk]
SIG AR signal >=1
SIG Manual closing signal

21SOTF.St
SIG T.VTS.Alm or T.VTS.InstAlm
&
[21SOTF.t_Op] 0 21SOTF.Op
&
SIG F.VTS.Alm or F.VTS.InstAlm >=1
SET [Opt_FeedingSystem]=Direct
3
SIG Flag.21SOTF &
SIG [21SOTF.En] &
SIG 21Lx.Pkp
Figure 3.9-5 Logic of distance SOTF protection
Where:
Flag.21SOTF: the measured impedance falls within the operating zone of distance SOTFprotection.
3.9.5 Settings
Access path: MainMenu  Settings  Protection Settings  SOTF Settings

Logic setting for selecting
the manual closing SOTF
ManClsBI
trigger mode:
1 SOTF.Opt_Mode_ManCls CBPos CBPos - -
circuit breaker position,
ManClsBI/CBPos
manual closing input, or
either.
The initiating time for the
2 SOTF.t_En 0.2~100 3 s 0.001
SOTF protection
3 50PSOTF.I_Set 0.05~200 1 A 0.001 overcurrent SOTF
protection
Time delay for phase
4 50PSOTF.t_Op 0~100 0.1 s 0.001 overcurrent SOTF
protection

Date: 2021-04-20
Enabling/disabling phase
Disabled
5 50PSOTF.En Enabled - - overcurrent SOTF
Enabled
protection
Enabling/disabling
Disabled second harmonic blocking
6 50PSOTF.En_Hm2_Blk Enabled - -
Enabled for phase overcurrent
SOTF protection
undervoltage supervision
Disabled
7 50PSOTF.En_Volt_Blk Enabled - - logic for phase
Enabled
3 overcurrent
protection
SOTF
Time delay for distance

8 21SOTF.t_Op 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling
9 21SOTFx.En Enabled - -
Enabled distance SOTF protection
Enabling/disabling
Disabled
10 21SOTFx.En_Hm2_Blk Disabled - - distance SOTF protection
Enabled
blocked by harmonic
Disabled
11 21LSOTFx.En_Hm_Restrain Disabled - - harmonic suppression
Enabled
function of distance SOTF
protection
3.10 Automatic Reclosure (79)

To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. AR are installed to restore the faulted section of the transmission system once the
fault is extinguished (providing it is a transient fault). For certain transmission systems, AR is used
to improve system stability by restoring critical transmission paths as soon as possible.

AR can be used with either integrated device or external device. When AR is used with integrated
device, the internal protection logic can initiate AR, moreover, a tripping contact from external
device can be connected to the device via input signal to initiate integrated AR.
When AR is used as an independent device, it can be initiated by operating signal of protections.

The device can output some configurable output signals (such as, contact signals or digital signal,
for example, GOOSE signal) to initiate external AR or block external AR. The contact signals
includes tripping signal, blocking AR signal and protection operating signal, etc,. According to
requirement, these contacts can be selectively connected to external AR and the device can be set
as one-shot or multi-shot AR.

Date: 2021-04-20
3.10.1.1 Enable AR
When the setting [79.Opt_Enable] is set as "Setting&Config", AR is determined whether it is

enabled or disabled by the external input signal and the internal setting. Otherwise, it is only
determined by the internal setting. When AR is enabled, the device outputs the signal "79.On",
otherwise the device outputs the signal "79.Off".
The logic of enabling AR is:
EN [79.En] &
>=1
3
SET [79.Opt_Enable]=Setting 79.On
SET [79.Opt_Enable]=Setting&Config & 79.Off
SIG 79.Enable
&
SIG 79.Block
Figure 3.10-1 Logic of enabling AR
3.10.1.2 Synchronism Check for AR
The device provides auto-reclosing (AR) function. According to the setting [Opt_CBConfig], there
are three auto-reclosing mode can be selected.
Synchronism check
No. CB configuration mode Note
mode for AR
Used for substation, feeder of sub-section
1 [Opt_CBConfig]= “Feeder” AR without any check
post
2 [Opt_CBConfig]= “Incmg” Live check for single side Used for incoming feeder of sub-section post
[Opt_CBConfig]= “Single Live check for double Used for single parallel circuit breaker of auto-
3
parallel” sides transformer substation and section post
[Opt_CBConfig]= “Double Used for double parallel circuit breaker of
4 Live check for single side
parallel” auto-transformer substation and section post
Based on the chosen synchronism check mode for AR, the device judges whether the synchronism
condition is satisfied, and then implement reclosing.
3.10.1.3 AR Ready
AR must be ready to operate before performing reclosing. The output signal [79.Ready] means that
the auto-reclosure can perform at least one time of reclosing function, i.e., breaker open-close-
open.
When the device is energized or after the settings are modified, AR cannot be ready unless the
following conditions are met:
1. AR is enabled.
2. The circuit breaker is ready, such as, normal storage energy and no low pressure signal.

Date: 2021-04-20
3. The duration of the circuit breaker in closed position pre-fault is greater than the setting
[79.t_CBClsd].
4. There is no the signal of blocking AR.
After AR operates, it must reset, i.e. [79.Active]=0, in addition to the above conditions for reclosing
again.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After the fault is cleared, the tripping signal will drop out immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [79.t_PersistTrp], AR will be blocked, as shown in following figure
3 The input signal [79.CB_Healthy] must be energized before AR gets ready. Because most circuit
breakers can finish one complete process: open-closed-open, it is necessary that circuit breaker
has enough energy before reclosing. When the time delay of AR is exhausted, AR will be blocked
if the input signal [79.CB_Healthy] is still not energized within time delay [79.t_CBReady]. If this
function is not required, the input signal [79.CB_Healthy] can be not to configure, and its state will
be thought as “1” by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input signal of blocking AR, when the circuit breaker is open by manually and there is CB
position input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not
initiated and no any trip signal.
SIG Any tripping signal [79.t_PersistTrp] 0 >=1

0 [79.t_DDO_Blk] 79.Blocked
SIG 79.LockOut
Figure 3.10-2 Logic of AR block
When AR is disabled, AR fails, synchronism check fails or last shot is reached, or when the internal
blocking condition of AR is met. AR will be discharged immediately and next AR will be disabled.
When the input signal [79.LockOut] is energized, AR will be blocked immediately. The blocking flag
of AR will be also controlled by the internal blocking condition of AR. When the blocking flag of AR
is valid, AR will be blocked immediately. The logic of AR ready is shown as below
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop out with a time delay [79.t_DDO_Blk] after blocking signal disappears.

Date: 2021-04-20
>=1
SIG CB closed position [79.t_CBClsd] 100ms &
SIG 79.Active >=1
SIG Any tripping signal

& &
2s 0 79.Ready
SIG 79.Inprog
BI [79.CB_Healthy] 0 [79.t_CBReady] &

SIG 79.Blocked >=1
SIG 79.Lockout
>=1
&
3
SIG 79.Failed
>=1
SIG 79.Fail_Chk
SIG Last shot is made
SIG 79.On
Figure 3.10-3 Logic of AR ready
When any protection element operates to trip, the device will output a signal [79.Active] until AR
drop out (Reset Command). Any tripping signal can be from external protection device or internal
protection element.
3.10.1.4 AR Initiation
AR can be initiated by the tripping signal of line protection or CB state.
1. AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When AR is ready to reclosing (“79.Ready”=1) and the tripping signal is received, this tripping
signal will be kept in the device, and AR will be initiated after the tripping signal drops out. The
tripping signal kept in the device will be cleared after the completion of AR sequence (Reset
Command). Its logic is shown as below.
SIG Reset Command &

>=1
SIG Trip Signal
& AR Initiation
SIG 79.Ready
Figure 3.10-4 Tripping initiating AR

Date: 2021-04-20
2. AR initiated by CB state
AR can be initiated by CB state by setting the setting [79.En_CBInit]. Under normal conditions,
when AR is ready to reclose (“79.Ready”=1), AR will be initiated if circuit breaker is open and
corresponding phase current is nil. AR initiated by CB state logic is shown as below. Usually
normally closed contact of circuit breaker is used to reflect CB state.
SIG CB open
&
EN [79.En_CBInit] & AR Initiation
3 SIG 79.Ready
Figure 3.10-5 CB state initiating AR
3.10.1.5 AR Reclosing
When the dead time delay of AR expires after AR is initiated, if the synchronism check is enabled,
the release of reclosing signal shall be subject to the result of synchronism check.
After the dead time delay of AR expires, if the synchronism check is still unsuccessful within the
time delay [79.t_wait_Chk], the signal of synchronism check failure ("79.Fail_Chk") will be output
and the AR will be blocked.
[79.t_Dd_S1] 0 & AR Pulse

If 79.Inhibit_AR operates,
SIG 79.Inhibit_AR then circuit of time delay
will be interrupted. >=1
& [79.t_Wait_Chk] 0 79.Fail_Chk
SIG AR Initiation
SIG 79.Ok_Chk
Figure 3.10-6 One-shot AR
Reclosing pulse length may be set through the setting [79.t_PW]. For the circuit breaker without
anti-pump interlock, the setting [79.En_CutPulse] is available to control the reclosing pulse. When
this function is enabled, if the device operates to trip during reclosing, the reclosing pulse will drop
out immediately, so as to prevent multi-shot reclosing onto fault. After the reclosing signal is issued,
AR will drop out with time delay [79.t_Reclaim], and can carry out next reclosing.
The reclaim timer is started when the CB closing signal is given. The reclaim timer defines a time
from the issue of the reclosing command, after which the reclosing function resets. Should a new
trip occur during this time, it is treated as a continuation of the first fault.

Date: 2021-04-20
SI G AR Pulse 0ms [79.t_PW]
& 79.Out
SI G Trip
&
EN [ 79.En _ CutPulse ]
>=1
&
SIG 79.Out [79.t_ Reclaim] 0ms Reset Command
Figure 3.10-7 Reclosing output logic 3

3.10.1.6 Reclosing Failure and Success
For line fault, the fault will be cleared after the device operates to trip. When the following cases
appear, the reclosing is unsuccessful.
1. If any protection element operates to trip when AR is enabled ("79.On"=1) and AR is not ready
("79.Ready"=0), the device will output the signal "79.Failed".
2. For one-shot AR, if the tripping signal is received again within reclaim time after the reclosing
pulse is issued, the reclosing shall be considered as unsuccessful.
3. For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping signal is received again after the last reclosing pulse is issued, the reclosing shall be
considered as unsuccessful.
4. The setting [79.En_FailCheck] is available to judge whether the reclosing is successful by CB

state, when it is set as “Enabled”. If CB is still in open position with a time delay [79.t_Fail] after
the reclosing pulse is issued, the reclosing shall be considered as unsuccessful. For this case,
the device will issue a signal "79.Failed" to indicate that the reclosing is unsuccessful, and this
signal will drop out after (Reset Command). AR will be blocked if the reclosing shall be
considered as unsuccessful.
After unsuccessful AR is confirmed, AR will be blocked.

Date: 2021-04-20
SIG 79.On
&
SIG 79.Ready
SIG Any tripping command

& >=1
0 100ms
>=1
SIG Last shot is made 79.Failed
SIG 79.Inprog
&
SIG 79.Blocked
>=1
3 SIG AR Pulse &

[79.t_Fail ] 0
&
SIG CB closed
EN [79.En_ FailCheck ]
&
79.Succeeded
&
0 [79.t_Fail ]
SIG Reset Command 0s 2s 79.Completed
Figure 3.10-8 Reclosing failure and success
3.10.1.7 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [79.Num], the
maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR is
selected. Some corresponding settings may be hidden if one-shot AR is selected.
 [79.Num]=1
It means one-shot reclosing. Line protection device will operate to trip when a transient fault occurs
on the line and AR will be initiated. After the dead time delay for AR is expired, the device will send
reclosing pulse, and then AR will drop out after the time delay [79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure "79.Failed".
 [79.Num]>1
It means multi-shot reclosing. For multi-shot reclosing, line protection device will operate to trip
when a transient fault occurs on the line and AR will be initiated. After the dead time delay of the
first reclosing is expired, the device will send reclosing pulse, and then AR will drop out after the
time delay [79.t_Reclaim] to ready for the next reclosing. For permanent fault, the device will
operate to trip again after the reclosing is performed, and then AR is initiated after the tripping
contact drops off. After the time delay for AR is expired, the device will send reclosing pulse. The
sequence is repeated until the reclosing is successful or the maximum permit reclosing number
[79.Num] is reached.
3.10.1.8 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.

Date: 2021-04-20
Signal
Fault
Trip
CB 52b
Open [79.t_Reclaim]
3
79.t_Reclaim
79.Active
79.Inprog [79.t_Dd_S1]
79.Ok_Chk
AR Out [79.t_PW]
79.Perm_Trp
79.Failed
Time
Figure 3.10-9 Transient fault
Signal
Fault
Trip
Open Open
52b
[79.t_Reclaim]
79.t_Reclaim
79.Active
79.Inprog [79.t_Dd_S1] [79.t_Dd_S2]
79.Ok_Chk
AR Out [79.t_PW] [79.t_PW]
79.Perm_Trp
79.Failed 200ms
Time
Figure 3.10-10 Permanent fault ([79.Num]=2)

Date: 2021-04-20
79
79. Enable 79.On
79.Block 79.Off
79.Trp 79. Close
79. Lockout 79. Ready
79.CB_ Healthy 79.AR_Blkd
3
79.Clr_ Counter 79. Active
79. Inprog
79.Inprog_S1
79.Inprog_S2
79.Inprog_S3
79.Inprog_S4
79. Rcls_ Status
79.Failed
79.Succeeded
79.Completed
79.Fail_Chk
3.10.3 I/O Signals

Input signal of enabling AR, it is triggered from binary input or programmable logic
1 79.Enable
etc.
Input signal of blocking AR, it is triggered from binary input or programmable logic
2 79.Block
etc.
3 79.Trp Input signal of three-phase tripping from line protection to initiate AR
Input signal of blocking reclosing, usually it is connected with the operating signals
4 79.Lockout of definite-time protection, transformer protection and busbar differential protection,
etc.
The input for indicating whether circuit breaker has enough energy to perform the
5 79.CB_Healthy
close function
6 79.Clr_Counter Clear the reclosing counter
1 79.On AR is enabled.
2 79.Off AR is disabled.
3 79.Close AR operates.
4 79.Ready AR have been ready for reclosing cycle.
5 79.Blocked AR is blocked.

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6 79.Active AR logic is active.

7 79.Inprog AR cycle is in progress
8 79.Inprog_S1 First AR cycle is in progress
9 79.Inprog_S2 Second AR cycle is in progress
10 79.Inprog_S3 Third AR cycle is in progress
11 79.Inprog_S4 Fourth AR cycle is in progress
AR status
0: AR is preprocessed
12 79.Status 1: AR is ready.
2: AR is in progress.
3: AR is successful. 3
13 79.Failed Auto-reclosing fails
14 79.Succeeded Auto-reclosing is successful
15 79.Fail_Chk Synchro-check for AR fails
16 79.Completed AR is completed.
3.10.4 Settings
Access path: MainMenu  Settings  Protection Settings  AR Settings
Uni
No. Settings Range Default Step Description
t
The logic setting used to select the
circuit breaker configuration, the
auto-reclosing mode will be
changed according to it.
Feeder: Used for substation, feeder
Feeder; of sub-section post
Incmg; Incmg: Used for incoming feeder of
Single parallel; sub-section post

1 79.Opt_CBConfig Feeder - -
Single parallel: Used for single
Double
parallel circuit breaker of auto-
parallel
transformer substation and section
post
Double parallel: Used for double
parallel circuit breaker of auto-
transformer substation and section
post
The live voltage check setting of
2 79.U_LvChk 10~100 70 V 0.001
reclosing
Maximum number of reclosing
3 79.Num 1~4 1 - 1
attempts
4 79.t_Dd_S1 0~600 0.600 s 0.001 Dead time of first shot reclosing
5 79.t_Dd_S2 0~600 0.600 s 0.001 Dead time of second shot reclosing

Date: 2021-04-20
Uni
t
6 79.t_Dd_S3 0~600 0.600 s 0.001 Dead time of third shot reclosing
7 79.t_Dd_S4 0~600 0.600 s 0.001 Dead time of fourth shot reclosing
Time delay of circuit breaker in

8 79.t_CBClsd 0~600 5.000 s 0.001
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
signal [79.CB_Healthy] is de-
9 79.t_CBReady 0~600 5.000 s 0.001
3 energized and if it is not energized

within this time delay, AR will be
blocked.
Maximum wait time for
10 79.t_Wait_Chk 0~600 10.000 s 0.001
synchronism check
11 79.t_Reclaim 0~600 15.000 s 0.001 Reclaim time of AR
Drop-out time delay of blocking AR,

when blocking signal for AR
12 79.t_DDO_BlkAR 0~600 5.000 s 0.001
disappears, AR blocking condition
drops out after this time delay
Time delay of excessive trip signal
13 79.t_PersistTrp 0~600 0.200 s 0.001
to block AR
Time delay allow for CB status
14 79.t_Fail 0~600 0.200 s 0.001 change to conform reclosing
successful
15 79.t_PW_AR 0~600 0.120 s 0.001 Pulse width of AR closing signal
Enabling/disabling confirm whether

Disabled
16 79.En_FailCheck Disabled - - AR is successful by checking CB
Enabled
state
Disabled Enabling/disabling adjust the
17 79.En_CutPulse Disabled - -
Enabled length of reclosing pulse
Disabled
18 79.En Enabled - - Enabling/disabling auto-reclosing
Enabled
Enabling/disabling AR by external
input signal besides logic setting
Setting
Setting [79.En]
19 79.Opt_Enable Setting&Confi - -
Setting: only the setting
g
Setting&Config: the setting and
configuration signal
Disabled Enabling/disabling AR be initiated
20 79.En_CBInit Disabled - -
Enabled by open state of circuit breaker

Date: 2021-04-20
3.11 Fault Location (FL)

When the device is used for a feeder under direct feeding mode, it adopts the piecewise linearized
reactance approximation method to measure the fault location. It is required to input the total
kilometers and total reactance value from each segment point of the line to the starting point when
configure the setting value. In order to make the measured fault location more accurate, the
calculation result of the reactance data of the last cycle before the current disappears is adopted.
When the setting [FL.En_kmPost] is set as “Enabled”, the measurement result shows the kilometer
post, and the kilometer post calculation equation is as follows: 3
𝑆 = 𝑆0 + 𝑆𝐷 × 𝐿 + 𝐿𝐷 × 𝐿𝐶
𝑆0: corresponds to the setting [FL.kmPost_Substation];
𝐿: the fault distance from the substation to the faulty point;
𝑆𝐷 : corresponds to the setting [FL.Opt_Dir_kmPost]. Determine the increase or decrease according

to the feeding section direction managed by the fault location device. When [FL.Opt_Dir_kmPost]=0,
𝑆𝐷 = −1; when [FL.Opt_Dir_kmPost]=1, 𝑆𝐷 = 1.
𝐿𝐶 : corresponds to the setting [LineLength], it is line length from the traction substation to the feeder.
𝐿𝐷 : contrary to 𝑆𝐷 , 𝐿𝐷 = −𝑆𝐷 .
For the increasing section of the kilometer post of the feeding section, when the calculated actual
kilometer post data is less than or equal to 𝑆0, it indicates that the fault happens within the feeder
cable range. For the decreasing section of the kilometer post of the feeding section, when the
calculated actual kilometer post data is greater than or equal to 𝑆0 , it indicates that the fault
happens within the feeder cable range.
FL
Fault_Location
3.11.3 I/O Signals

1 Fault_Location The result of fault location
3.11.4 Settings
Access path: MainMenu  Settings  Protection Settings  Line Settings
No. Settings Range Default Unit Step Remark

1 FL.En Disabled Disabled - - The logic setting for enabling/disabling

Date: 2021-04-20

Enabled fault location function
The logic setting for enabling/disabling
Disabled the kilometer post display, if it is
2 FL.En_kmPost Disabled - -
Enabled enabled, the measurement result of
fault location shows the kilometer post.
3 FL.kmPost_Substation 0~9999 100 km 0.001 The kilometer post of the substation
The setting for selecting the kilometer
4 FL.Opt_Dir_kmPost 0~1 0 - 1
post direction.
The line length from the traction
3 5 FL.LineLength 0 ~ 100 10 km 0.001
substation to the feeder
6 FL.Num_Point 1 ~ 12 1 - 1 The segment point number
7 FL.X_01 0 ~ 600 5 Ω 0.001 The reactance value of the 1st point
8 FL.Location_01 0 ~ 100 10 km 0.001 The location of the 1st point
9 ……
10 FL.X_12 0 ~ 600 5 Ω 0.001 The reactance value of the 12th point
11 FL.Location_12 0 ~ 100 10 km 0.001 The location of the 12th point
3.12 Incoming Feeder Auto-transfer Switch (83ATS)

When the logic setting for enable/disable auto-transfer switch (ATS) function [Link_ATS] is set as
“1” and the binary input for enabling ATS function [BI_ATS] is energized, if the loss-of-voltage
protection operates, and the incoming feeder circuit breaker is tripped successfully, the ATS
initiating signal will be issued to initiate the ATS function of the protection device of another
incoming feeder. And if the ATS function is ready, the ATS protection will operate to close the circuit
breaker of the incoming feeder.
In order to meet the requirements of ATS, ATS is allowed only after the function is ready.
 Conditions for ATS
1) The incoming feeder voltage is larger than the live voltage check setting [79.U_LvChk]..
2) The circuit breaker is open.
After all above conditions are met at the same time, ATS is ready with a time delay of 15s.
 Discharge conditions
1) The circuit breaker is closed.
2) The normally closed auxiliary contact is abnormal.
3) The control circuit fails.
4) Incoming feeder ATS protection operates.

Date: 2021-04-20
If any of above conditions is met, ATS is discharged.
 Operating process
When ATS is ready, if the ATS initiating binary input [ATS.Init] is energized, ATS is initiated. After
the circuit breaker closing command is issued, if the circuit breaker closed position signal is not
received after the time delay of [ATS.t_Fail], the ATS fails signal [ATS.Failed] will be issued. After
the circuit breaker closing command is issued, if the circuit breaker closed position signal is
received after the time delay of [t_DPU_BI_CB], the ATS success signal [ATS.Succeeded] will be
issued.

3
ATS
ATS.Enable ATS.Ready
ATS.Block ATS.Failed
ATS.Init
ATS.Succeed
3.12.3 I/O Signals

1 ATS.Enable ATS enabling input, it is triggered from binary input or programmable logic etc.
2 ATS.Block ATS blocking input, it is triggered from binary input or programmable logic etc.
3 ATS.Init ATS initiating binary input
1 ATS.Ready ATS have been ready for reclosing cycle.
2 ATS.Failed ATS fails
3 ATS.Succeeded ATS is successful
3.12.4 Settings
Access path: MainMenu  Settings  Protection Settings  ATS Settings
No. Setting Default Range Step Unit Description

Disabled; The logic setting for enabling/disabling ATS
1 ATS.En Disabled - -
Enabled function
Time delay allow for CB status change to
2 ATS.t_Fail 0.200 0~600 0.001 s
conform closing successful
3.13 VT Circuit Supervision (VTS)
In this section, the prefix “x” can be “T” or “F”, “T” corresponds to the traction
catenary VT and “F” corresponds to the feeder VT.

Date: 2021-04-20
3.13.1 General Application

The purpose of VT circuit supervision is to detect whether VT circuit is normal. Some protection
functions should be disabled when measurement from VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
 Only current protection functions are enabled and VT is not connected to the device.
3  The specific current protection has picked up before the satisfaction of conditions of VT circuit
failure alarm.

VT circuit supervision can detect failure on VT. Under normal condition, the device continuously
supervises input voltage from VT. The VT circuit failure alarm will be issued with configurable time
delay if the voltage is less than the setting [VTS.U_Set], and the current is larger than the setting
[VTS.I_LowLmt] and less than the setting [VTS.I_UpLmt].
VT (secondary circuit) MCB auxiliary contact can be connected to the binary input circuit of the
device as a binary signal. If the MCB has been opened (i.e. "x.VTS.MCB_VT" is energized), the
device will consider that the VT circuit is in a bad condition and issue an alarm without a time delay.
If the auxiliary contact is not connected to the device, VT circuit supervision will be issued with time
delay as mentioned in previous paragraph.
When VT is not connected into the device, the alarm shall be not issued if the logic setting [En_VT]
is set as "Disabled". However, the alarm is still issued if the binary input "x.VTS.MCB_VT" is
energized, no matter that the logic setting [En_VT] is set as "Disabled" or "Enabled".
3.13.3 Function Block
VTS
x.VTS.Enable x.VTS.Alm
x.VTS.Block x.VTS.InstAlm
x.VTS.MCB_VT
3.13.4 I/O Signals

VT circuit supervision enabling input, it is triggered from binary input or
1 x.VTS.Enable
programmable logic etc (x = T or F).
VT circuit supervision blocking input, it is triggered from binary input or
2 x.VTS.Block
programmable logic etc (x = T or F).

Date: 2021-04-20
3 x.VTS.MCB_VT Binary input for VT MCB auxiliary contact (x = T or F)

1 x.VTS.Alm Alarm signal to indicate VT circuit fails (x = T or F)
2 x.VTS.InstAlm Instantaneous alarm signal to indicate VT circuit failure (x = T or F)
3.13.5 Logic
SET Ux<[VTS.U_Set]
>=1
SET Ix<[VTS.I_UpLmt] [VTS.t_DPU] [VTS.t_DDO] &
3
SET Ix>[VTS.I_LowLmt]
>=1
EN [En_VT]
&
x.VTS.Alm
BI x.VTS.MCB_VT
EN [VTS.En]
&
SIG x.VTS.Enable
SIG x.VTS.Block
Figure 3.13-1 VT circuit supervision logic diagram
SET Ux<[VTS.U_Set]
>=1
SET Ix<[VTS.I_UpLmt] 25ms 0ms &
SET Ix>[VTS.I_LowLmt]
>=1
EN [En_VT]
&
x.VTS.InstAlm
BI x.VTS.MCB_VT
EN [VTS.En]
&
SIG x.VTS.Enable
SIG x.VTS.Block
Figure 3.13-2 Instantaneous VT circuit supervision logic diagram
3.13.6 Settings
Access path: MainMenu  Settings  Global Settings  Superv Settings

The voltage threshold for VT circuit
1 VTS.U_Set 50 10~ 100 0.01 V
supervision
The current upper limit setting for
2 VTS.I_UpLmt 0.1 (0.1~20)In 0.01 A
VT circuit supervision

Date: 2021-04-20

The current lower limit setting for
3 VTS.I_LowLmt 0.04 (0 ~ 20)In 0.01 A
VT circuit supervision
Delay pickup setting for the alarm
4 VTS.t_DPU 1.500 0.2~30 0.001 s
of VT circuit supervision
Delay drop off setting for the alarm
5 VTS.t_DDO 10.000 0.2~30 0.001 s
Disabled; Logic setting for alarm function of
6 VTS.En Enabled - -
Enabled VT circuit supervision

Date: 2021-04-20
4 Control Functions
4 Control Functions
Table of Contents
4.1 Switchgear Control .......................................................................................... 4-1

4.1.1 Functional Description .......................................................................................................... 4-1
4.1.2 Operation Theory ................................................................................................................. 4-2
4.1.4 I/O Signals ............................................................................................................................ 4-5
4.1.5 Logics ................................................................................................................................... 4-7

4
4.1.6 Settings................................................................................................................................. 4-9
List of Figures
Figure 4.1-1 Logic diagram of switchgear closing operation................................................. 4-7
Figure 4.1-2 Logic diagram of switchgear opening operation ............................................... 4-7
Figure 4.1-3 Logic diagram of DPS alarm ................................................................................. 4-8
Figure 4.1-4 Logic diagram of trip counter triggering ............................................................. 4-8
Figure 4.1-5 Logic diagram of Interlocking .............................................................................. 4-8
Figure 4.1-6 Logic diagram of manual control ......................................................................... 4-9
List of Tables
Table 4.1-1 Remote/Local control mode switch logic ............................................................. 4-2

Date: 2021-04-20
4 Control Functions

Date: 2021-04-20
4 Control Functions
4.1 Switchgear Control

The switchgear control function is mainly used to realize operation of primary equipment such as
circuit breaker (CB), disconnect switch (DS) and earthing switch (ES). This function can be divided
into remote control and local control according to the control source location. A remote control
mainly refers to remote control commands from substation automation system (SAS) or network
control center (NCC). However, a control triggered manually from the device LCD, by a terminal
contact or by a panel handle is a local control. The switchgear control function is closely related to
interlocking, double point status (DPS), remote/local control mode switching and trip counter.
4.1.1 Functional Description

A control command can realize various control signals such as the CB/DS/ES opening/closing. In
order to ensure the reliability of the control output, a locking circuit is added to each control object.
The operation is strictly in accordance with the selection, check and execution steps, to ensure that
the control operation can be safely and reliably implemented. In addition, the device has a hardware 4
self-checking and blocking function to prevent hardware damage from mal-operation output.
When the device is in the remote-control mode, the control command may be sent via
communication protocol; when it is in the local control mode, the local operation may be performed
on the device LCD or panel handle.
A complete control process is:
1. Protocol module sends a selection command;
2. Control module responds the success or failure result of selection;
3. If the selection is successful, the protocol module sends an execution command, otherwise it
sends a cancel command;
4. Control module responds the success or failure result of execution;
5. The control operation may be open/close or up/down/stop.
When the device is in the maintenance status, it can still respond to local control commands.
The switchgear control function can cooperate with functions such as synchronism check and
interlocking criteria calculation to complete the output of the corresponding operation command. It
can realize the normal control output in one bay and the interlocking and programmable logic
configuration between bays.
This device supports the following functional control module:
Module Description
CSWI Control of circuit breaker (CB), disconnector switch (DS) or earthing switch (ES)
RMTLOC Remote or local control mode
XCBR Synthesis of CB position, three-phase or phase separated
XSWI Synthesis of DS/ES position
SXCBR/SCSWI Trip counter of CB/DS/ES

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4 Control Functions
Module Description
RSYN Synchronism check for CB closing
CILO Interlocking logic for CB/DS/ES control
MCSWI Manual control of CB/DS/ES
CHKPOS Position verification for switchgear control
4.1.2 Operation Theory

The initiation of a control command may be sent to the device by the SCADA or the NCC through
communication protocol. It may also be the operation of the device LCD or the manual triggering
through configured signal. The command is sent by the CPU to the control module for processing,
and a control record is made on the CPU module according to the control result.
4.1.2.1 Remote/Local Control Mode Switch
Since the source of a control command may be SAS or NCC, or may be triggered by the device
4 LCD or terminal contact, it is necessary to provide a remote/local control mode switch function.
The remote/local control mode switch function determines whether the device is in the remote or
the local control permission state through the configuration of terminal contact, function key, or
binary signal. Each control object provides a remote/local input, and the control module determines
the current control authority to be remote or local according to the input value. By default, if the
input is not configured, any control operation is blocked.
Table 4.1-1 Remote/Local control mode switch logic
in_Remote in_Local Remote Control Local Control

NULL NULL Disable Disable
0 NULL Disable Enable
1 NULL Enable Disable
NULL 0 Enable Disable
NULL 1 Disable Enable
0 0 Disable Disable
0 1 Disable Enable
1 0 Enable Disable
1 1 Enable Enable
4.1.2.2 Double Point Status
A double point status (DPS), which usually indicates switchgear status, can be derived from 2
ordinary binary inputs. The signification of a DPS is shown in the following table. For switchgear
status, only the 2 statuses "01" and "10" indicating respectively the positions opening and closing
are valid. The other 2 statuses "00" and "11", i.e. intermediate or bad status, will cause the alarm
"DPS.Alm".
DPS Bit0 = 0 Bit0 = 1

Bit1 = 0 DPS_INT DPS_OFF
Bit1 = 1 DPS_ON DPS_BAD

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4 Control Functions
For the convenient use in user-defined logic programming, this functional module derives four
single-bit outputs to indicate each DSP state.
Indication Signal
DPS State
DPS_ON DPS_OFF DPS_INT DPS_BAD
ON 1 0 0 0
OFF 0 1 0 0
INT 0 0 1 0
BAD 0 0 0 1
This unit also supports the DPS synthesis through switchgear opening and closing positions after
jittering processing. The synthetic DPS contains original SOE timestamp. The CB control function
supports phase-segregated position inputs and can synthesize these inputs into general position.
In accordance with the control object, the DPS synthesis function is divided into 2 modules: XCBR
and XSWI. The XCBR is mainly used for CB position synthesis, including phase-segregated
positions, while the XSWI is used DS or ES position synthesis.
4
4.1.2.3 Trip Counter
The trip counter function takes the DPS of switchgear position as input count the trip times. For CB,
this device supports phase-segregated and general trip counter. The trip counter function is
triggered by DPS change. The counting result is stored in non-volatile memory for power-off holding.
Use the clear command from the menu in local LCD or customized binary signal to reset trip counter.
4.1.2.4 Interlocking
The interlocking function will influence the control operation output. When the function is enabled,
the device determines whether the control operation is permitted based on the interlocking logic
result. Each control object is equipped with an independent interlocking logic which supports
unlocking operation through a binary signal.
The interlocking function is very important for the control operation of switchgears. During the
operation of primary equipment, the positions of the relevant equipment must be correct for
operation permission. For remote control, i.e. command from SAS or NCC, this device could detect
the interlocking logic depending on the message within the command; for local control through
device LCD or terminal contact, please use the corresponding logic setting to enable/disable the
interlocking function.
4.1.2.5 Manual Control
The switchgear control function supports manual control function that can be configured with a
terminal contact or binary signal to trigger the control operation.
The manual control function supports the control input configuration of selection and open/close.
When the control object selection input is configured, the signal "1" indicates that the current control
object has to be selected before a control operation; if the control object selection input is not
configured, the control command can be directly issued without judgment of selection.

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4 Control Functions
4.1.2.6 Switchgear Position Verification
The position verification function is provided during switchgear control process. In a control function
block of circuit breaker, disconnector or earthing switch, if the input “in_CheckPos_En” is set as 1,
the CB/DS/ES position shall be verified when receiving a remote or local control command.
The verification logic complies with IEC 61850 standard is:
 A control object only permits to be opened when its DPS is CLOSE;
 A control object only permits to be closed when its DPS is OPEN;
 The device shall respond control command failed with the cause of failure when its DPS is INT,
BAD or opposite (i.e. OPEN while opening or CLOSE while closing).
4.1.2.7 Direct Control
For applications such as signal reset and function enable/disable, the control mode is generally
4 direct control, i.e. execution without selection before, direct control with normal security in IEC
61850.
The direct control function provides remote/local switch and interlocking configurations. The control
command is usually issued directly by the SAS. It also supports the command triggered by binary
signal.

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4 Control Functions
XCBR: circuit breaker; XSWI: disconnector switch or earthing switch
In above figure, the signals related to three-phase (phase-A, phase-B, and phase-C) and the
synchronization are used by the conventional three-phase power system, and do not need to be
configured in the traction power supply system of electrified railway.
4.1.4 I/O Signals
The prefix CB** for circuit breaker and DS** for disconnector switch in the
following lists are hidden since their description (if valid) are similar.

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4 Control Functions

1 in_en Enabling function
2 In_blk Disabling function
3 in_Remote Remote control mode
4 in_Local Local control mode
5 in_Pos_NO Normally opened contact input for DPS opening position
6 in_Pos_NC Normally closed contact input for DPS closing position
7 in_N_Trp Opening command for trip counter
8 in_Clr_Cnt Clear trip counters
9 in_Rsyn Structure pointer of synchronism check element
10 in_EnaOpn Opening permission for interlocking
11 in_EnaCls Closing permission for interlocking
12 in_CILO_Bypass Bypass for interlocking
13 in_Manual_Sel Selection for manual control
4 14 in_Manual_Opn Opening for manual control
15 in_Manual_Cls Closing for manual control
16 in_CheckPos_En Input signal of enabling of position verification function for switchgear control
1 NO_DPS DPS opening position
2 NC_DPS DPS closing position
3 DPS Synthetic DPS for switchgear position
4 N_Trp Trip counter
5 Opn_Enabled Permission of opening operation
6 Cls_Enabled Permission of closing operation
7 Opn/Cls_Enabled Permission of operation (Opn_Enabled OR Cls_Enabled)
8 Opn_Exec Opening operation
9 Cls_Exec Closing operation
10 Opn_Sel Opening selection
11 Cls_Sel Closing selection
12 DPS.Alm Alarm signal when DPS status is BAD or INT
13 Cmd_ManSel Selection command for manual control
14 Cmd_ManOpn Opening command for manual control
15 Cmd_ManCls Closing command for manual control
16 DPS_ON Single-bit DPS state indication of ON
17 DPS_OFF Single-bit DPS state indication of OFF
18 DPS_INT Single-bit DPS state indication of INT
19 DPS_BAD Single-bit DPS state indication of BAD
In above table, the prefix can be “CB” or “DS01”~“DS04”.

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4 Control Functions
4.1.5 Logics
The prefix CB** for circuit breaker and DS** for disconnector switch in the
following diagrams are hidden since their logics (if valid) are similar.
EN [CB.En_CILO_Cls] >=1
SIG CB.Cls_Enabled
SIG CB Control Mode = Remote &

& 0 [CB.t_PW_Cls] CB.Cls_Exec
SIG CB.Cls_Exec_Man >=1 >=1
CB closing cmd. from device local HMI
&
4
CB closing cmd. from SCADA/Gateway
EN [DS**.En_CILO_Cls] >=1
SIG DS**.Cls_Enabled
SIG DS** Control Mode = Remote & &

>=1 0 [DS**.t_PW_Cls] DS**.Cls_Exec
SIG DS**.Cls_Exec_Man >=1
DS** closing cmd. from device local HMI &
DS** closing cmd. from SCADA/Gateway
Figure 4.1-1 Logic diagram of switchgear closing operation
EN [XXXX.En_CILO_Opn] >=1
SIG XXXX.Opn_Enabled
SIG XXXX Control Mode = Remote & &

>=1 0 [XXXX.t_PW_Opn] XXXX.Opn_Exec
SIG XXXX.Opn_Exec_Man >=1
XXXX opening cmd. from device local HMI &
XXXX opening cmd. from SCADA/Gateway
Figure 4.1-2 Logic diagram of switchgear opening operation

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4 Control Functions
SIG XXXX.DPS=BAD >=1

&
SIG XXXX.DPS= INT [XXXX.DPS.t_Alm] [XXXX.DPS.t_Alm] XXXX.Alm_DPS
EN [XXXX.DPS.En_Alm]
Figure 4.1-3 Logic diagram of DPS alarm
SIG Rasing edge of in_N_Trp & N_Trp + 1
SIG DPS change form ON to OFF
Figure 4.1-4 Logic diagram of trip counter triggering
4 From SCADA/Gateway with

"Interlocking"
Remote control
>=1
The interlocking logic of
Local control
XXXX is activated
From device HMI with "InterlockChk"
>=1
From energized contact via binary input &
SIG Manual control
EN [XXXX.En_CILO_Opn] >=1
EN [XXXX.En_CILO_Cls]
Figure 4.1-5 Logic diagram of Interlocking

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4 Control Functions
SIG in_Manual_Sel = NUL &

>=1
SIG in_Manual_Opn
SIG in_Manual_Sel &
SIG in_Manual_Opn
&
SIG Opn_Enabled Opn_Exec_Man
SIG Control mode = Local
SIG in_Manual_Sel = NUL &
SIG in_Manual_Cls
>=1
SIG in_Manual_Sel &
4
SIG in_Manual_Cls
&
SIG Cls_Enabled Cls_Exec_Man
SIG Control mode = Local
Figure 4.1-6 Logic diagram of manual control
4.1.6 Settings
4.1.6.1 Double Point Status Settings
Access path: Main Menu  Settings  Meas Control Settings  DPS Settings

Delay Pick Up (DPU) time, i.e.
1 CB.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of the circuit
breaker
Disabled or Logic setting for DPS alarm of the
2 CB.DPS.En_Alm Disabled - -
Enabled circuit breaker
Operation time delay of DPS alarm
3 CB.DPS.t_Alm 500 0~60000 1 ms
of the circuit breaker
Delay Pick Up (DPU) time, i.e.
4 DS**.DPS.t_DPU 500 0~60000 1 ms debounce time, for DPS of
disconnector switch ** (**=01~09)
Logic setting for DPS alarm of the
Disabled or
5 DS**.DPS.En_Alm Disabled - - circuit breaker of disconnector switch
Enabled
** (**=01~09)
Operation time delay of DPS alarm
6 DS**.DPS.t_Alm 500 0~60000 1 ms of the circuit breaker of disconnector
switch ** (**=01~09)

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4 Control Functions
4.1.6.1 Control Settings
Access path: Main Menu  Settings  Meas Control Settings  Control Settings

Pulse Width (PW), i.e. holding time,
1 CB.t_PW_Opn 500 0~60000 1 ms for opening output of the circuit
breaker
2 CB.t_PW_Cls 500 0~60000 1 ms for closing output of the circuit
breaker
3 DS**.t_PW_Opn 500 0~60000 1 ms for direct opening output of
4 4 DS**.t_PW_Cls 500 0~60000 1 ms for direct closing output of

5 DirCtrl**.t_PW_Opn 500 0~60000 1 ms
for direct opening output
6 DirCtrl**.t_PW_Cls 500 0~60000 1 ms
for direct closing output
4.1.6.2 Interlocking Logic Settings
Access path: Main Menu  Settings  Meas Control Settings  Interlock Settings

Logic setting for interlocking logic
Disabled or
1 CB.En_CILO_Opn Disabled - - control of closing output of the circuit
Enabled
breaker
Disabled or
2 CB.En_CILO_Cls Disabled - - control of opening output of the
Enabled
circuit breaker
Disabled or
3 DS**.En_CILO_Opn Disabled - - control of direct closing output of
Enabled
Disabled or
4 DS**.En_CILO_Cls Disabled - - control of direct opening output of
Enabled
Disabled or Logic setting for interlocking logic
5 DirCtrl**.En_CILO_Opn Disabled - -
Enabled control of direct opening output.
Disabled or Logic setting for interlocking logic
6 DirCtrl**.En_CILO_Cls Disabled - -
Enabled control of direct closing output.

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5 Measurement
5 Measurement
Table of Contents
5.1 Primary Values ................................................................................................. 5-1

5.1.1 General Values ..................................................................................................................... 5-1
5.1.2 Angle Values ......................................................................................................................... 5-1
5.1.3 Power Values........................................................................................................................ 5-1
5.1.4 Harmonics ............................................................................................................................ 5-2
5.2 Secondary Values ............................................................................................ 5-2

5.2.1 General Values ..................................................................................................................... 5-2
5.2.2 Angle Values ......................................................................................................................... 5-3
5.2.3 Power Values........................................................................................................................ 5-3 5

5.2.4 Harmonics ............................................................................................................................ 5-4
5.3 Energy Metering .............................................................................................. 5-4

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5 Measurement

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5 Measurement
5.1 Primary Values

Access path: MainMenu  “Measurements”  “Primary Values”
5.1.1 General Values
No. Symbol Definition Unit
1 It_Pri The traction catenary current A
2 If_Pri The feeder current A
3 Ut_Pri The traction catenary voltage kV
4 Uf_Pri The feeder voltage kV
5 Ut2_Pri Another group of traction catenary voltage kV
6 Uf2_Pri Another group of feeder voltage kV
7 f Frequency of protection voltage Hz
5.1.2 Angle Values
Phase angle between traction catenary voltage and traction catenary °

5
1 Ang (Ut-It)
current
2 Ang (Uf-If) Phase angle between feeder voltage and feeder current °
3 Ang (Ut-Uf) Phase angle between traction catenary voltage and feeder voltage °
4 Ang (It-If) Phase angle between traction catenary current and feeder current °
Phase angle between the traction catenary voltage and the referenced
5 Ang (Ut) voltage, currently, the traction catenary voltage is used as the referenced °
voltage.
6 Ang (Uf) Phase angle between the feeder voltage and the referenced voltage °
Phase angle between another group of traction catenary voltage and the
7 Ang (Ut2) °
referenced angle
Phase angle between another group of feeder voltage and the

8 Ang (Uf2)
referenced angle
9 Ang (It) Phase angle between traction catenary current and the referenced angle °
10 Ang (If) Phase angle between feeder current and the referenced angle °
5.1.3 Power Values
No. Sign Description Unit
1 Pt_Pri The primary value of traction catenary active power MW
2 Pf_Pri The primary value of feeder active power MW
3 Qt_Pri The primary value of traction catenary reactive power MVAr
4 Qf_Pri The primary value of feeder reactive power MVAr

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5 Measurement
5 St_Pri The primary value of traction catenary apparent power MVA
6 Sf_Pri The primary value of feeder apparent power MVA
7 P_Pri The primary value of active power MW
8 Q_Pri The primary value of reactive power MVAr
9 S_Pri The primary value of apparent power MVA
10 Cost The traction catenary power factor -
11 Cosf The feeder power factor -
12 Cos Power factor -
5.1.4 Harmonics
1 Ut_Hm01_Pri kV
2 Ut_Hm02_Pri kV
3 Ut_Hm03_Pri kV
5 4 Ut_Hm04_Pri kV
5 Ut_Hm05_Pri kV
6 Ut_Hm06_Pri kV
7 Ut_Hm07_Pri kV
8 Ut_Hm08_Pri The primary value of the 1st~15th voltage harmonic kV
9 Ut_Hm09_Pri kV
10 Ut_Hm10_Pri kV
11 Ut_Hm11_Pri kV
12 Ut_Hm12_Pri kV
13 Ut_Hm13_Pri kV
14 Ut_Hm14_Pri kV
15 Ut_Hm15_Pri kV
5.2 Secondary Values

Access path: MainMenu  “Measurements”  “Secondary Values”
5.2.1 General Values
1 It_Sec The traction catenary current A
2 If_Sec The feeder current A
3 Ut_Sec The traction catenary voltage V
4 Uf_Sec The feeder voltage V

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5 Measurement
5 Ut2_Sec Another group of traction catenary voltage V
6 Uf2_Sec Another group of feeder voltage V
7 f Frequency of protection voltage Hz
5.2.2 Angle Values
Phase angle between traction catenary voltage and traction catenary

1 Ang (Ut-It) °
current
2 Ang (Ut-It) Phase angle between feeder voltage and feeder current °
3 Ang (Ut-Uf) Phase angle between traction catenary voltage and feeder voltage °
4 Ang (It-If) Phase angle between traction catenary current and feeder current °
Phase angle between the traction catenary voltage and the referenced
5 Ang (Ut) voltage, currently, the traction catenary voltage is used as the referenced °
voltage.
6 Ang (Uf) Phase angle between the feeder voltage and the referenced voltage
Phase angle between another group of traction catenary voltage and the
°
5
7 Ang (Ut2) °
referenced angle
Phase angle between another group of feeder voltage and the

8 Ang (Uf2) °
referenced angle
9 Ang (It) Phase angle between traction catenary current and the referenced angle °
10 Ang (If) Phase angle between feeder current and the referenced angle °
5.2.3 Power Values
1 Pt_Pri The secondary value of traction catenary active power MW
2 Pf_Pri The secondary value of feeder active power MW
3 Qt_Pri The secondary value of traction catenary reactive power MVAr
4 Qf_Pri The secondary value of feeder reactive power MVAr
5 St_Pri The secondary value of traction catenary apparent power MVA
6 Sf_Pri The secondary value of feeder apparent power MVA
7 P_Pri The secondary value of active power MW
8 Q_Pri The secondary value of reactive power MVAr
9 S_Pri The secondary value of apparent power MVA
10 Cost The traction catenary power factor -
11 Cosf The feeder power factor -
12 Cos Power factor -

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5 Measurement
5.2.4 Harmonics
1 Ut_Hm01_Sec V
2 Ut_Hm02_Sec V
3 Ut_Hm03_Sec V
4 Ut_Hm04_Sec V
5 Ut_Hm05_Sec V
6 Ut_Hm06_Sec V
7 Ut_Hm07_Sec V
8 Ut_Hm08_Sec The secondary value of the 1st~15th voltage harmonic V
9 Ut_Hm09_Sec V
10 Ut_Hm10_Sec V
11 Ut_Hm11_Sec V
12 Ut_Hm12_Sec V
Ut_Hm13_Sec V
5
13
14 Ut_Hm14_Sec V
15 Ut_Hm15_Sec V
5.3 Energy Metering

Access path: MainMenu  “Measurements”  “Energy Metering”
1 EA_Accu_Fwd Positive active energy kWh
2 EA_Accu_Rev Negative active energy kWh
3 ER_Accu_Fwd Positive reactive energy kVarh
4 ER_Accu_Rev Negative reactive energy kVarh

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6 Supervision
6 Supervision
Table of Contents
6.1 Overview........................................................................................................... 6-1

6.2 Device Hardware Supervision ........................................................................ 6-1
6.2.1 Hardware Resource Consumption Supervision ................................................................... 6-2
6.2.2 Hardware Status Supervision............................................................................................... 6-2
6.2.3 Hardware Configuration Supervision ................................................................................... 6-3
6.2.4 Device Firmware Supervision .............................................................................................. 6-3
6.2.5 CPU Process and Module Supervision ................................................................................ 6-3
6.3 Analog Input Supervision ............................................................................... 6-3

6.4 Secondary Circuit Supervision ...................................................................... 6-4
6.5 Binary Input Supervision ................................................................................ 6-5
6.5.1 Debounce Time .................................................................................................................... 6-5
6.5.2 Jitter Processing ................................................................................................................... 6-6

6
6.6 Tripping Counter Statistics ............................................................................. 6-8
6.7 Supervision Alarms and Handling Suggestion ............................................. 6-9
List of Figures
Figure 6.4-1 Principle of the TCS function with two binary inputs ........................................ 6-4
Figure 6.5-1 Sequence chart of debounce technique ............................................................. 6-5
Figure 6.5-2 Debounce time configuration page ..................................................................... 6-5
Figure 6.5-3 Sequence chart of jitter processing .................................................................... 6-7
List of Tables
Table 6.7-1 Alarm description ...................................................................................................... 6-9
Table 6.7-2 Alarm handling suggestion .................................................................................... 6-15

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6 Supervision

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6 Supervision
6.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED “HEALTHY” is on, the device needs to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed if required.
6.2 Device Hardware Supervision
All hardware has real-time monitoring functions, such as CPU module monitoring, communication
interface status monitoring, power supply status monitoring. 6
The monitoring function of CPU module also includes processor self-check, memory self-check
and so on. The processor self-check is checked by designing execution instructions and data
operations. Check whether the processor can execute all instructions correctly, and whether it can
correctly calculate complex data operations to determine whether it works normally. For peripherals,
it can monitor the status of the interface module, check the input and output data, send the
communication interface and receive self-loop detection. Memory self-check is used to detect
unexpected memory errors in the running process. It can effectively prevent program logic
abnormality caused by memory errors.
The status monitoring of communication interface also includes Ethernet communication interface
monitoring and differential channel communication interface monitoring. By accessing the status
register of the communication interface, the state of the corresponding interface is obtained, such
as the state of connection, the number of sending frames, the number of frames received, and the
number of wrong frames. According to the statistics of the acquired interface state, it is detected
whether the interface work is abnormal.
The hardware supervision also includes the power supply status monitoring. The voltage monitoring
chip is used by all the power supplies. The reset voltage threshold is pre-set to the reset monitoring
circuit. When the power supply is abnormal, the voltage monitoring chip will output the reset signal
to control CPU to be in the reset state and avoid the wrong operation.

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6.2.1 Hardware Resource Consumption Supervision

1. Logic component total execution time monitoring
In the process of operation, the safety allowance should always be kept and no overload
phenomenon is allowed. When the user configures logic components with PCS-Studio, the PCS-
Studio automatically calculates the time required for the theoretical execution of the configured
components. When the security limit is exceeded, the PCS-Studio will indicate that the
configuration error is not allowed to download the current configuration to the device.
2. Module data exchange monitoring
During the operation of the device, there is a lot of data exchange between modules. The number
of data exchanges is related to the number of logical components configured by the user. When
the configuration is too large to cause the number of data exchange to exceed the upper limit
supported by the device, the PCS-Studio prompts the configuration error.
3. Configuration file size monitoring
The initialization of the device depends on the configuration files of each module. The user
configured logical components will eventually be embodied in the configuration file, limited to the
hardware memory space. When the configuration file size is more than the upper limit, the PCS-
Studio prompts the configuration error.
6.2.2 Hardware Status Supervision

6 1. Memory ECC and parity functions.
The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate
unexpected changes in memory caused by electromagnetic interference. The chip memory has
parity function. When an error occurs, the system can detect anomalies immediately, and eliminate
the logic abnormity caused by memory errors.
2. Memory error monitoring in code area and constant data area
In addition to the above hardware memory reliability measures, the device software is also
constantly checking the memory during operation, including code, constant data, and so on. Once
the error detection, the system will automatically restart the restore operation. If they detect the
error immediately after the restart, it may be the result of a permanent fault locking device hardware,
only at the moment and not restart.
3. Binary output relay drive monitoring
The reliability of the device is largely determined by the reliability of the export drive. By reading
the driving state of the binary output relay, the alarm signal will be generated and the device is
immediately blocked to prevent the relay from mal-operation when the device is not given a tripping
order and the binary output relay driver is detected in the effective state.
4. CPU temperature monitoring
The CPU chip needs to be able to ensure long-term stability under the permissible working
temperature of the specification. Therefore, it is necessary to monitor the working temperature

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6 Supervision
monitored by CPU.
6.2.3 Hardware Configuration Supervision

The device is blocked when the actual hardware configuration is not consistent with the hardware
configuration file. Compared with pre-configured modules, this device will be blocked if more
module is inserted, fewer module is inserted, and wrong modules is inserted.
6.2.4 Device Firmware Supervision

1. Each hardware module configuration check code needs to be consistent with CPU module.
The device CPU module stores the configuration check codes of other modules. In initialization
procedure, it checks whether the configuration check code of each module is consistent with the
stored code in CPU module, and if it is not consistent, this device is blocked.
2. The hardware modules and process interface versions need to be consistent with the CPU
module.
If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this
moment, each hardware module and process will be upgraded synchronously, otherwise the
version of the interface will be inconsistent.
3. Configuration text is correct.
The configuration text formed by the device calibration visualization project includes checking
whether the check code is wrong or not. 6
4. Whether any setting is over the range, whether it needs to confirm the settings.
If the setting exceeds the configuration range, the device is blocked; if some settings are added, it
is necessary to confirm the new values through the LCD.
6.2.5 CPU Process and Module Supervision

1. Monitor the heartbeat of the module.
In the operation procedure, the CPU module sends a time synchronization command to other
module, each module repeats heartbeat message to the CPU module, if it does not respond or the
heartbeat is abnormal, then this device is blocked.
2. Check whether the settings of other modules are consistent with the CPU module.
The actual values of all the settings in the CPU module are initialized to send to the corresponding
slave modules. In the process of operation, the setting values stored in the CPU module and the
setting values of other modules will be checked one by one. If they are not consistent, this device
will issue the alarm signal "Fail_Settings".
6.3 Analog Input Supervision
The sampling circuit of this device is designed as dual-design scheme. Each analog sampling

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6 Supervision
channel is sampled by two groups of ADC. The sampling data is self checking and inter checking
in real time. If any sampling circuit is abnormal, the device reports the alarm signal “Alm_Sample”,
and the protection function related to the sampling channel is disabled at the same time. When the
sampling circuit returns to normal state, the related protection is not blocked after 10s.
6.4 Secondary Circuit Supervision
The secondary circuit supervision function includes voltage transformer supervision (VTS) and
tripping/closing circuit supervision.
 VTS function
The purpose of the VTS function is to detect whether the VT analog input is normal. Because some
function, such as distance protection, will be influenced by a voltage input failure.
The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and then
issue an alarm signal and block relevant function.
See further details about the VTS function, please refer to Chapter 3.
 Tripping circuit supervision function
The tripping circuit supervision function can be realized by program the logic function of this device
6 through the PCS-Studio according to the practical application experience of the user. In this manual,
a scheme which uses two independent binary inputs to supervise the tripping circuit is
recommended.
The following figure show the recommended scheme for tripping circuit supervision and the logic
diagram of the TCS function.
DC+ DC-
52a TC
BTJ
52b
Protection Device Circuit Breaker

[BI_01]
& 600ms [Alm_TCS]
[BI_02]
Figure 6.4-1 Principle of the TCS function with two binary inputs
Where:
“BTJ” is the protection tripping output contact;
“TC” is the tripping coil of the circuit breaker;
[BI_01] is the binary input which is parallel connected with “BTJ”;
[BI_02] is the binary input which is serial connected with the “52b” contact.

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6.5 Binary Input Supervision

6.5.1 Debounce Time
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.5-1.
Binary input
state
SOE report SOE report

timestamps timestamps
Validated binary input Validated binary input
state changes state changes
1
Debounce time of Debounce time of

delayed pickup delayed dropout
Time
Figure 6.5-1 Sequence chart of debounce technique
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When 6
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the binary
input will be validated and wrote into SOE.
In order to meet flexible configurable requirement for different project field, all binary inputs provided
by the device are configurable. Through the configuration tool, this device provides two parameters
to setup debounce time of delayed pickup and drop-out based on specific binary signal.
Figure 6.5-2 Debounce time configuration page
The configurable binary signals can be classified as follows:
1. Type 1

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This type of binary inputs includes enable/disable of protection functions, AR mode selection,
“BI_RstTarg”, “BI_Maintenance”, disconnector position, settings group switch, open and
close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They are on the premise of reliability, and the debounce
time of delayed pickup and delayed drop-out is recommended to set as 100ms at least.
2. Type 2
This type of binary inputs include breaker failure initiating binary inputs,
“CSWIxx.Cmd_LocCtrl”, “CSWIxx.Cmd_RmtCtrl” and so on.
Debounce time
BI Input Signal.X1 t1 t2 &

Time delay Output
SIG Operation condition
 Time delay is equal to 0
The debounce time of delayed pickup and delayed drop-out is recommended to set as
15ms, in order to prevent binary signals from mal-operation due to mixed connection of
AC system and DC system.
 Time delay is not equal to 0

6 The debounce time of delayed pickup and delayed drop-out is recommended to set as (-
t1+ t2+Time delay)≥15ms, in order to prevent binary signals from mal-operation due to
mixed connection of AC system and DC system. Where, “t1” is the debounce time of
delayed pickup, and “t2” is the debounce time of delayed drop-out.
3. Type 3
This type of binary inputs is usually used as auxiliary input condition, and the debounce time
of delayed pickup and delayed drop-out is recommended to set as 5ms.
When users have their own reasonable setting principles, they can set the
debounce time related settings according to their own setting principles.
6.5.2 Jitter Processing

This device can handle repetitive signal or so-called jitter via binary input module with the
following settings:
[Mon_Window_Jitter] T, monitoring window of binary input jitter processing
[Num_Blk_Jitter] N, times threshold to block binary input status change due to jitter
[Blk_Window_Jitter] T', blocking window of binary input status change due to jitter

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[Num_Reblk_Jitter] N', times threshold to initiate immediately another blocking window

of binary input status change due to continuous jitter
For a binary input voltage variation, if the jitter processing function is enabled, its handling principle
is:
1. During the T,
 If the actual jitter times < N, the block will not be initiated and the status change of this
binary input will be considered.
 If the actual jitter times ≥ N, the T' is initiated, and the status change of binary input will be
ignored during the T'.
2. During the T',
 If the actual jitter times < N', the block window will expire. The final status of this binary
input will be compared to the original one before T', so as to determine whether there is a
change or not.
 If the actual jitter times ≥ N', the T' will be initiated again immediately (i.e. restart the timer),
and the status change of binary input will be ignored during the next T'.
An example of jitter processing is shown in the following sequence chart:
Debounce time Input voltage level

(falling edge)
Debounce time
(rising edge)
6
Jitter blocking flag
n=N
initiate jitter block
Signal after
debounce & jitter
n=6<N=7
n=N processing
Prolong blocking
window
T
T t7 t8
t5 t6
T T T
t1 t2 t3 t4 t9 t10 t
Figure 6.5-3 Sequence chart of jitter processing
①Red line Voltage variation of binary input
②Green line Blocking signal of binary input status change due to jitter

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③Blue line Binary input status after debounce and jitter processing
n Actual jitter times
We take N = 7 and N' = 5 in this example.
1. T = t2 - t1
 n=6<N
 No blocking, ② stays at 0 and ③ is tracing the voltage variation to create SOE.
2. T = t4 - t3, at t5
 n=7=N
 The processing initiates the blocking immediately due to jitter
 Jitter blocking, no more SOE event, ② changes its status to 1 and ③ stops the tracing.
3. T' = t6 - t5
 At t7, n = 5 =N', the processing prolongs the blocking immediately due to jitter
Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
6 
4. T'= t8 - t7
 At t9, n = 5 =N', the processing prolongs the blocking immediately due to jitter.
 Jitter blocking continues, no SOE event, ② stays at 1 and ③ keeps its status.
5. T'= t10 - t9
 n = 2 < N'
 At t10, jitter unblocking, ② changes its status to 0, the blocking window expires and ③
restart to trace the voltage varation immediately. At this point, no debounce time takes
effect and SOE can be created since then.
6.6 Tripping Counter Statistics
The tripping counter statistics function supports statistics of the tripping operation, such as circuit
breakers, disconnectors and so on. For the circuit breaker, when the position is detected from close
state to open state, the total position tripping counter is added, and the tripping counter is added
once when the position of the disconnector is detected from close state to open state.

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In addition, the statistics of the number of state change of circuit breakers and disconnectors are
also provided. The state change counter will add one when the position is detected from close state
to open state or from open state to close state.
6.7 Supervision Alarms and Handling Suggestion
Hardware circuit and operation status of this device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure, DC
converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts “BO_Fail” will be given. The
protective device then cannot work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
If the device is blocked or alarm signal is sent during operation, please do find out its reason with
the help of self-diagnostic record. If the reason cannot be found at site, please notify the factory
NR. Please do not simply press button “TARGET RESET” on the protection panel or re-energize
on the device.
Table 6.7-1 Alarm description
Running Status LED

6
No. Item Description
HEALTHY ALARM Modifiable
Fail Signals (Device will be blocked)

This signal will be issued if
any fail signal picks up and it
1 Fail_Device OFF OFF NO
will drop off when all fail
signals drop off.
any hardware or software
failure, or serious
2 Fail_DeviceInit OFF OFF NO
configuration error is
detected in the device
initialization process.
This signal will be issued
due to mismatch between
the configuration of plug-in
3 Fail_BoardConfig OFF OFF NO
modules and the designing
drawing of an applied-
specific project.
4 Fail_ProcLevelConfig OFF OFF NO
the CCD process level

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6 Supervision
Running Status LED

configure file is parsed

wrongly or the type in the file
is inconsistent with the
actual device.
After configuration file is
updated, settings of the file
and settings saved on the
device are not matched. This
5 Fail_SettingItem_Chgd OFF OFF NO signal will be issued
instantaneously and will be
latched unless the
recommended handling
suggestion is adopted.
The value of any setting is
out of scope. This signal will
be issued instantaneously
6 Fail_Setting_OvRange OFF OFF NO
and will be latched unless
the recommended handling
6 The alarm signal will be

issued instantaneously
when an error is found
7 Fail_Memory OFF OFF NO
during checking memory
data, and usually, it will
automatically drop out.
The board fails to register
the variable, because of
8 Fail_BoardRegister OFF OFF NO abnormal board, insufficient
memory space, or incorrect
configuration.
The configuration process
9 Fail_ProcessConfig OFF OFF NO
does not run properly.
The board fails to be
initialized, because of
10 Fail_BoardInit OFF OFF NO abnormal board, insufficient
memory space, or incorrect
configuration.
Error is found during
checking settings. It means
11 Fail_Settings OFF OFF NO
inappropriate or incorrect
settings for some application

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6 Supervision
Running Status LED

scenarios are checked.

This signal will be issued
instantaneously and will be
latched unless the
recommended handling
A/D sampling data push
error, the possible cause is
12 Fail_Sample OFF OFF NO that the data verification fails
or no data is sampled by A/D
converter.
The output module is
13 Fail_Output OFF OFF NO
abnormal
An abnormality is detected
14 Bx.Fail_Board OFF OFF NO during self-check of No. x
board of this device.
The PWR module is
15 P1.Fail_Board OFF OFF NO
abnormal.
Alarm Signals (Device will not be blocked)
The device is abnormal. This
signal will be issued if any
6
16 Alm_Device ON ON NO alarm signal picks up and it
will drop off when all alarm
signals drop off.
any hardware or software
17 Alm_DeviceInit ON OFF NO configuration wrong is
detected in the device
The error is found during
checking the version of
software downloaded to the
18 Alm_Version ON ON NO
device. This signal will be
issued instantaneously and
will drop off instantaneously.
Alarm signal indicating that
the equipment is in
maintenance state (the
19 Alm_Maintenance ON ON YES
binary input
[BI_Maintenance] is
energized.

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6 Supervision
Running Status LED

The device is in the

communication test mode.
20 Alm_CommTest ON ON NO This signal will be issued
instantaneously and will
drop off instantaneously.
The device is in the GOOSE
test mode. This signal will be
21 Alm_GOOSETest ON OFF NO
Management procedure will
upload and check the
parameters and settings of
each protection plug-in
22 Alm_Settings_MON ON ON NO
module regularly, if the
parameters and settings are
inconsistent, the alarm
signal will be issued.
The active group set by
settings in device and that
6 23 Alm_BI_SettingGrp ON OFF NO
set by binary input are not
matched. This signal will be
The time synchronization
24 Alm_TimeSyn ON ON YES
abnormality alarm.
The memory of CPU plug-in
25 Alm_Insuf_Memory ON ON NO
module is insufficient.
The configuration file of
IEC103 is detected to be not
26 Alm_CfgFile_IEC103 ON ON NO correct when this file is
parsed in the device
CPU module detects that
some module is reset due to
27 Alm_Board ON OFF NO
the abnormality during the
device operating.
An abnormality is detected
28 Bx.Alm_Board ON ON NO during the module self-
check.
No sufficient NOR flash
29 Alm_Insuf_NORflash ON OFF NO
space used to store the

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6 Supervision
Running Status LED

program in CPU module

The settings which are
stored in CPU module are
30 Alm_Settings ON ON NO different with the settings
which are used by other
modules.
Disturbance fault recording
31 Alm_Settings_DFR ON OFF NO
settings are set wrongly
The network mode is
inconsistent, such as the
32 Alm_NetMode_Unmatched ON OFF NO setting is set as HSR mode,
but the actual operation
mode is PRP mode.
The device's master process
33 Alm_master ON ON NO is abnormal and it is blocked
for more than 1 minute.
Error is detected in the
34 Alm_CfgFile_FPGA ON OFF NO
FPGA configuration file.
Error is detected in internal
35 Alm_DSP_HTM_Comm ON ON NO
communication.
Error is detected in the
6
36 Alm_CRC_ProcLevel ON OFF NO configuration file of process
level by CRC.
The configuration file of DNP
37 Alm_CfgFile_TCP1_DNP ON OFF NO
client 1 is incorrect.
The device is in the binary
41 Alm_BOTest ON OFF NO
output test mode.
the sampled values from the
dual A/D converters are
inconsistent or the sampled
42 Alm_Sample ON ON NO
value contains a large DC
component during the self or
mutual supervision of
sampling channels.

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6 Supervision
Running Status LED

The quality of sampled data

43 Alm_Quality ON ON NO
is abnormal.
DPS abnormality signal, if
the circuit breaker position is
intermediate or bad, this
alarm will be issued.
44 CB.DPS.Alm ON OFF YES
This signal will pick up and
drop off with a time delay
defined by
[CSWI**.DPS.t_Alm].
DPS abnormality signal, if
the switch 0x position is
intermediate or bad, this
DS0x.DPS.Alm alarm will be issued.
45 ON OFF YES
(x=1~9) This signal will pick up and
drop off with a time delay
defined by
[CSWI**.DPS.t_Alm].
The initiating signal of
6 46 50BF.Alm_Init ON ON YES breaker failure protection is

energized consistently.
Traction catenary VT circuit
fails.
This signal will pick-up with a
47 T.VTS.Alm ON ON YES
time delay of [VTS.t_DPU]
and will drop-out with a time
delay of [VTS.t_DDO].
Feeder VT circuit fails.
This signal will pick-up with a
48 F.VTS.Alm ON ON YES time delay of [VTS.t_DPU]
and will drop-out with a time
delay of [VTS.t_DDO].
GOOSE alarm signals (Device will not be blocked)
The GOOSE communication
is abnormal.
It is an overall alarm signal
and will be issued if any
49 GAlm_Overall ON ON NO
GOOSE alarm signal picks
up and it will drop-out when
all these alarm signals drop-
out.

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6 Supervision
Running Status LED

GOOSE alarm signal

50 GAlm_CfgFile ON ON NO indicating that GOOSE
configuration file is incorrect.
For GOOSE link, the
incoming data with test=true
& validity=good &
51 GAlm_Maint_Unmatched ON ON NO
operatorBlocked=false, but
the quality status (q) of the
device equals to "on".
Network A of corresponding
GOOSE link is disconnected
@Bx.Name_n_GCommLink (No GOOSE message is
52 ON ON NO
.GAlm_ADisc received within two times
TAL from corresponding
GOOSE link)
Network B of corresponding
GOOSE link is disconnected
@Bx.Name_n_GCommLink (No GOOSE message is
53 ON ON NO
.GAlm_BDisc received within two times
TAL from
GOOSE link)
corresponding
6
The GOOSE control blocks
received on network and the
GOOSE control blocks
@Bx.Name_n_GCommLink defined in GOOSE
54 ON ON NO
.GAlm_CfgUnmatched configuration file are
unmatched (Including config
version, number of data sets
and data type).
Table 6.7-2 Alarm handling suggestion
No. Item Handling suggestion
Fail Signals (Device will be blocked)

The signal is issued with other specific fail signals, and please refer to
1 Fail_Device
the handling suggestion other specific alarm signals.
2 Fail_DeviceInit Please inform the manufacturer or the agent for repair.
1. Go to the menu “Information→Borad Info”, check the abnormality
information.
3 Fail_BoardConfig
2. For the abnormality board, if the board is not used, then remove, and
if the board is used, then check whether the board is installed properly

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6 Supervision
and work normally.

Check whether the CCD process level configuration file of this device is
4 Fail_ProcLevelConfig existed and whether the file content is correct. May need to download
and update the correct CCD process level configuration file.
Please check the settings mentioned in the prompt message on the
LCD, and go to the menu “Settings” and select “Confirm_Settings”
5 Fail_SettingItem_Chgd
item to confirm settings. Then, the device will restore to normal operation
stage.
Please reset setting values according to the range described in the
6 Fail_Setting_OvRange instruction manual, then re-power or reboot the device and the device
will restore to normal operation state.
7 Fail_Memory
Please inform the manufacturer or the agent for repair.
8 Fail_BoardRegister
9 Fail_ProcessConfig View the menu "Initialization Error" to check the detailed reason, and
10 Fail_BoardInit send the reason to the manufacturer or the agent.
11 Fail_Settings Please check the settings and set them correctly
12 Fail_Sample Please check the connection of CPU plug-in module.
Put the protective device out of service at once. Inform the manufacturer
13 Fail_Output
or the agent to maintain it.
6 14 Bx.Fail_Board Please inform the manufacturer or the agent to deal with it.
15 P1.Fail_Board Please inform the manufacturer or the agent to deal with it.
Alarm Signals (Device will not be blocked)
The signal is issued with other specific alarm signals, and please refer
16 Alm_Device
to the handling suggestion other specific alarm signals.
17 Alm_DeviceInit Please inform the manufacturer or the agent to deal with it.
Users may pay no attention to the alarm signal in the project
commissioning stage, but it is needed to download the latest package
file (including correct version checksum file) provided by R&D engineer
18 Alm_Version to make the alarm signal disappear. Then users get the correct software
version. It is not allowed that the alarm signal is issued on the device
already has been put into service. The devices having being put into
service so that the alarm signal disappears.
19 Alm_Maintenance Check the binary input [BI_Maintenance].
20 Alm_CommTest No special treatment is needed, and disable the communication test
21 Alm_GOOSETest function after the completion of the test.
Put the protective device out of service at once. Inform the manufacturer
22 Alm_Settings_MON
or the agent to maintain it.
Please check the value of setting [Active_Grp] and binary input of
indicating active group, and make them matched. Then the “ALARM”
23 Alm_BI_SettingGrp
LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.

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6 Supervision
1. Check whether the selected clock synchronization mode matches the

clock synchronization source;
2. Check whether the wiring connection between the device and the
clock synchronization source is correct
3. Check whether the setting for selecting clock synchronization (i.e.
24 Alm_TimeSyn
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization,
please set the setting [Opt_TimeSyn] as “No TimeSyn”.
After the abnormality is removed, the “ALARM” LED will be extinguished
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
25 Alm_Insuf_Memory Please inform the manufacturer or the agent to deal with it.
26 Alm_CfgFile_IEC103 Please inform the manufacturer or the agent to deal with it.
27 Alm_Board
28 Bx.Alm_Board
Please inform the manufacturer or the agent to deal with it.
29 Alm_Insuf_NORflash
30 Alm_Settings
Please refer to the fault recording configuration related contents, i.e.
31 Alm_Settings_DFR
Section 7.4.
Check the setting of network mode, or upload the device log and confirm
Alm_NetMode_Unmatched
6
32
with the manufacturer or agent whether the network mode is supported.
33 Alm_master Please check the load of the device.
34 Alm_CfgFile_FPGA Please inform the manufacturer or the agent for repair.
35 Alm_DSP_HTM_Comm Please inform the manufacturer or the agent for repair.
36 Alm_CRC_ProcLevel Please check the configuration and network of the process level.
37 Alm_CfgFile_TCP1_DNP
38 Alm_CfgFile_TCP2_DNP Please contact the configuration engineer to check and confirm the
39 Alm_CfgFile_TCP3_DNP contents of DNP configuration file.
40 Alm_CfgFile_TCP4_DNP
No special treatment is needed, and disable the binary output test
41 Alm_BOTest
function after the completion of the test.
42 Alm_Sample Please check the connection of AC AI module and CPU module.
43 Alm_Quality Please check SV quality if adopting IED 61850-9-2.
44 CB.DPS.Alm
DS0x.DPS.Alm Check the corresponding DPS signal
45
(x=1~9)
46 50BF.Alm_Init Check the initiating contact of breaker failure protection
Please check the traction catenary VT secondary circuit. After the
47 T.VTS.Alm
abnormality is eliminated, the device returns to normal operation state.
Please check the feeder VT secondary circuit. After the abnormality is
48 F.VTS.Alm
eliminated, the device returns to normal operation state.
GOOSE alarm signals (Device will not be blocked)

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6 Supervision
The signal is issued with other specific GOOSE alarm signals, and
49 GAlm_Overall
please refer to the handling suggestion of them.
50 GAlm_CfgFile Inform commissioning personnel to check the GOOSE configuration file.
51 GAlm_Maint_Unmatched Please check the quality status (q) of the incoming data and the device.
@Bx.Name_n_GCommLink
52
.GAlm_ADisc
53 Please check the GOOSE network and GOOSE configuration file.
.GAlm_BDisc
54
.GAlm_CfgUnmatched
Where:
@Bx.Name_n_GCommLink is the set value of the label setting of [Bx.Name_n_GCommLink]

(n=00~63)
@Bx.Name_n_SVCommLink is the set value of the label setting of [Bx.Name_n_SVCommLink]

(n=00~03)

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7 System Functions
7 System Functions
Table of Contents
7.1 Clock Synchronization .................................................................................... 7-1

7.1.1 Clock Synchronization Mode................................................................................................ 7-1
7.1.2 Clock Synchronization Abnormality ...................................................................................... 7-1
7.1.3 Clock Synchronization Priority ............................................................................................. 7-1
7.1.4 SNTP Setup.......................................................................................................................... 7-1
7.2 State Information ............................................................................................. 7-2

7.2.1 Overview............................................................................................................................... 7-2
7.2.2 Access Method ..................................................................................................................... 7-2
7.3 Event Recording .............................................................................................. 7-3

7.3.1 Overview............................................................................................................................... 7-3
7.3.2 Disturbance Records ............................................................................................................ 7-3
7.3.3 Supervision Events............................................................................................................... 7-3
7.3.4 Binary Events ....................................................................................................................... 7-4
7.3.5 Device Logs .......................................................................................................................... 7-4 7

7.3.6 Control Logs ......................................................................................................................... 7-4
7.3.7 High-frequency Recording ................................................................................................... 7-4
7.3.8 Access Method ..................................................................................................................... 7-4
7.4 Fault Recording ............................................................................................... 7-5

7.4.1 Overview............................................................................................................................... 7-5
7.4.2 Fault Report .......................................................................................................................... 7-5
7.4.3 Fault Waveform .................................................................................................................... 7-6
7.4.4 Access Method ..................................................................................................................... 7-7
7.5 Maintenance State ........................................................................................... 7-7

7.6 Communication Test ....................................................................................... 7-7
7.7 Output Test ....................................................................................................... 7-8
7.8 Target Reset ..................................................................................................... 7-9

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7 System Functions
7.9 Switch Setting Groups .................................................................................... 7-9

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7 System Functions
7.1 Clock Synchronization
7.1.1 Clock Synchronization Mode
The device supports both hardware-based and software-based clock synchronization modes.
1. Hardware-based clock synchronization ([Opt_TimeSyn]=Conventional)
 IRIG-B: IRIG-B via RS-485 differential level, TTL level, BNC or optical fibre interface
 PPS: Pulse per second (PPS) via RS-485 differential level or binary input
 IEEE 1588: Clock message based on IEEE 1588 via Ethernet network
2. Software-based clock synchronization ([Opt_TimeSyn]=SAS)
 SNTP: Unicast (point-to-point) & broadcast SNTP mode via Ethernet network
 Clock messages: IEC 60870-5-103 protocol, Modbus protocol and DNP3.0 protocol
7.1.2 Clock Synchronization Abnormality
The device provides an alarm signal "Alm_TimeSyn", which indicates the signal of clock
synchronization is abnormal or is lost. The setting [Opt_TimeSyn] should be set reasonably
according to actual clock synchronization source. But if the setting [Opt_TimeSyn] is set as
"NoTimeSyn" and no clock synchronization signal is inputted, the device will not issue the alarm
signal.
7.1.3 Clock Synchronization Priority

7
The device provides a priority-based adaptive clock synchronization scheme, which means that it
can automatically identify multiple clock synchronization sources in the same clock synchronization
mode and choose the highest priority of clock synchronization sources.
Clock synchronization Input signal The Highest priority

Software-based
SNTP + Clock message SNTP
([Opt_TimeSyn]=SAS)
Hardware-based IRIG-B + PPS + IEEE 1588 IRIG-B
([Opt_TimeSyn]=Conventional,
PPS + IEEE 1588 PPS
[En_ConvModeSNTP]=Disabled)
Hardware-based + SNTP IRIG-B + PPS + IEEE 1588 + SNTP IRIG-B

([Opt_TimeSyn]=Conventional, PPS + IEEE 1588 + SNTP PPS
[En_ConvModeSNTP]=Enabled) IEEE 1588 + SNTP IEEE 1588
7.1.4 SNTP Setup

When the device adopts SNTP to realize clock synchronization, [IP_Server_SNTP] and
[IP_StandbyServer_SNTP] shall be set correctly.

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7 System Functions
[IP_Server_SNTP] is the address of SNTP clock synchronization server which sends SNTP timing
messages to the relay or BCU. [IP_StandbyServer_SNTP] is the address of standby SNTP clock
synchronization server.
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock

synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the

device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the

device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the device

adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP
synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it

does not receive any server response in 30s.
7.2 State Information
7.2.1 Overview
The device can provide real-time state information, including analog quantities (such primary
7 measurement value, secondary measurement value, metering value and so on) and status
quantities (supervision status, input status, output status and so on). By check these state
information, operators can know operation state of the protected equipment and whether the device
is healthy.
7.2.2 Access Method
7.2.2.1 Access by Local HMI (Human Machine Interface)
These state information can be gained via local HMI. The menu path is:
1. Analog quantities
 MainMenu  "Measurements"  "Primary Values"
 MainMenu  "Measurements"  "Secondary Values"
 MainMenu  "Measurements"  "Energy Metering"
 MainMenu  "Measurements"  "Power Quality"
 MainMenu  "Measurements"  "UserDef Values"  "UserDef Values1/2"
2. Status quantities

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7 System Functions
 MainMenu  "Status"  "Inputs"
 MainMenu  "Status"  "Outputs"
 MainMenu  "Status"  "Superv Status"
 MainMenu  "Status"  "Logic Links Status"
 MainMenu  "Status"  "Running Status"
 MainMenu  "Status"  "UserDef Status"  "UserDef Status1/2"
7.2.2.2 Access by Virtual HMI
Using the virtual LCD tool, the corresponding content can be viewed through the same menu path
as local LCD.
7.2.2.3 Access by Communication Client
Device's state information can be uploaded into clients through message communication. For
differential protocols, the state information can be gained through corresponding communication
service.
7.2.2.4 Access by Printer
The device can print the current state information, so that the operator can observe and save the
current operation condition. The access path is:
MainMenu  "Print"  "Device Status"
7.3 Event Recording
7.3.1 Overview
7
The device can store the latest 1024 time-stamped disturbance records, 1024 time-stamped binary
events, 1024 time-stamped supervision events, 256 time-stamped control logs and 1024 time-
stamped device logs. All the records are stored in non-volatile memory, and when the available
space is exhausted, the oldest record is automatically overwritten by the latest one.
7.3.2 Disturbance Records

When any protection element operates or drops out, such as fault detector, distance protection etc.,
they will be logged in event records. Disturbance records include signal name, its value before and
after changing, and the time precision is up to 1ms.
7.3.3 Supervision Events

The device is under automatic supervision all the time. If there are any failure or abnormal condition
detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event records.
Supervision events include signal name, its value before and after changing, and the time precision
is up to 1ms.

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7 System Functions
7.3.4 Binary Events

When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records. Binary events include signal name, its value
before and after changing, and the time precision is up to 1ms.
7.3.5 Device Logs

If an operator executes some operations on the device, such as reboot protective device, modify
setting, etc., they will be logged in event records. Device logs include signal name, its value before
and after changing, and the time precision is up to 1ms.
7.3.6 Control Logs

When an operator executes a control command via local LCD, PCS-Studio or communication client,
it will be logged in control logs. Control logs include time stamp, controlled object, control origination,
control position, operation condition ,interlocking condition, control command and operation result.
7.3.7 High-frequency Recording

The high-frequency recording is available by PCS-Studio. By switching the option "Disabled" or
"Enabled" to enable or disable the function in the following path through the PCS-Studio
configuration tool: Project Node → Device Node → Device Setup → Global Config → System
Config.
When high-frequency recording is enabled, a high-frequency waveforms record (9.6kHz sampling)

can also be gained besides the normal disturbance waveforms record (1.2kHz sampling). The
difference between high-frequency waveforms records and normal disturbance waveforms records
is only the sampling rate. This kind of high-resolution records is convenient to perform post-fault
system and device operation analysis.
7.3.8 Access Method
7.3.8.1 Access by Local HMI
The device provides corresponding menus to view event recorders. The menu path is:
MainMenu  "Test"  "Disturb Records"
MainMenu  "Records"  "Superv Events"
MainMenu  "Records"  "IO Events"

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7 System Functions
MainMenu  "Records"  "Device Logs"
MainMenu  "Records"  "Control Logs"
MainMenu  "Records"  "HighFreqRecords"
as local LCD.
Event recorders can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3).
The device can print event recorders, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Superv Events"
MainMenu  "Print"  "IO Events"
7.4 Fault Recording
7.4.1 Overview
Fault recorder can be used to have a better understanding of the behaviour of the power network
and related primary and secondary equipment during and after a disturbance. Analysis of the
recorded data provides valuable information that can be used to improve existing equipment. This 7
information can also be used when planning for and designing new installations.
The fault recorder is comprised of the report and the waveform, which can be triggered by pickup
signals, trip signals and configurable binary signal “BI_TrigDFR”.
The fault memory of the device is automatically updated with every recording. When the fault
memory is filled completely, the oldest records are overwritten automatically. Thus, the most recent
recordings are always stored safely. The maximum number of recordings is 64.
7.4.2 Fault Report

For each fault report, the following items are included:
1. Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2. Date and time of fault occurrence
The date and time are recorded when a system fault is detected. The time resolution is 1ms.

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7 System Functions
3. Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record. The
time resolution is 1ms.
4. Fault information
Including faulty phase, fault location and protection elements
7.4.3 Fault Waveform

A fault waveform contains all analog and digital quantities related to protection such as currents,
voltages, differential current, alarm elements, binary inputs and etc.
The overall duration of a single fault recording comprises the total duration of the configurable
recording criterion, the pre-trigger time and the post-trigger time. With the fault recording parameter,
these components can be individually set. The pre-trigger waveform recorded duration is
configured via the setting [RecDur_PreTrigDFR]. The waveform recorded duration after the fault
disappears is configured via the setting [RecDur_PostFault]. The maximum post-trigger waveform
recorded duration is configured via the setting [MaxRecDur_PostTrigDFR].
4. [MaxRecDur_PostTrigDFR]
1. [RecDur_PreTrigDFR] 2.Pickup 3. [RecDur_PostFault]
Trigger point
Total recording time
Pre-trigger recording time

7 1.
Use the setting [RecDur_PreTrigDFR] to set this time.
2. Pickup recording time
The pickup recording time cannot be set. It continues as long as any valid trigger condition, binary
or analog, persists (unless limited by the limit time, which is determined by the setting
[MaxRecDur_PostTrigDFR]).
3. Post-fault recording time
The recording time begins after all activated triggers are reset. Use the setting [RecDur_PostFault]
to set this time.
4. Maximal post-trigger recording time
Use the setting [MaxRecDur_PostTrigDFR] to set this time. If the summation of pickup recording
time and post-fault recording time is larger than maximal post-trigger recording time, the post-
trigger recording time shall be equal to the setting [MaxRecDur_PostTrigDFR].

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7 System Functions
7.4.4 Access Method
7.4.4.1 Access by Local HMI
The device provides corresponding menus to check fault recording. The menu path is:
MainMenu  "Records"  "Disturb Records"
as local LCD.
Fault recording can be uploaded into clients through corresponding communication service of the
protocol (including IEC60870-5-103, IEC61850, DNP3).
The device can print fault recording, so that the operator can observe and save the current
operation condition. The access path is:
MainMenu  "Print"  "Disturb Records"
7.5 Maintenance State
The device provides maintenance state, i.e., the binary input [BI_Maintenance] is energized, which
is convenient for maintenance work. For adopting conventional CT/VT, binary inputs and binary
outputs, maintenance state has no influence on protection logics. For binary inputs and binary
outputs by GOOSE connections. During device maintenance, the object will send GOOSE
message with Test quality attribute. The Test quality attribute indicates to the receiver device that
7
the object received via a GOOSE message was created under test conditions and not operating
conditions. If the Test quality attribute received is different with the object's Test quality attribute,
binary inputs and binary outputs by GOOSE connections will be affected based on different types
of binary inputs and binary outputs. For SV (Sampling Value) message, if the Test quality attribute
received is different with the object's Test quality attribute, the relevant protection functions will be
blocked.
For IEC60870-5-103 protocol, only the messages in link layer maintained, service messages in the
application layer which is uploaded automatically are blocked, and service messages in the
application layer which is issued by the client are rejected. For IEC61850 protocol, all Test quality
attribute set as "1". For DNP3 and ModBus protocol, they are not affected.
7.6 Communication Test
The device provides Test Mode to allow all protection elements, supervision events and binary
events to fulfill communication test, but to avoid the output contacts to close. During communication
test, protection functions are not affected, the signals generated by communication test are

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7 System Functions
recorded in relevant reports, and event recording and fault recording will not stop recording
disturbance information. The alarm signal "Alm_CommTest" will be issued to indicate the operator
when activating Test Mode and exiting Test Mode.
Communication test can be gained via local HMI and the virtual HMI, the corresponding content
can be viewed through the following menu paths:
 Events Simulation
Main Menu  "Test"  "Device Test"  "Disturb Events"
Main Menu  "Test"  "Device Test"  "Superv Events"
Main Menu  "Test"  "Device Test"  "IO Events"
 Forced Measurements
Main Menu  "Test"  "Device Test"  "Measurements"
Forced measurement ONLY affects the values modified and transmitted to

station control or control center. Primary circuit, secondary circuit and
device local logic will not be influenced. Forced value will remain during
the test until the exit of this menu.
If no input operation is carried out within 60s, this test will exit and return to
the previous menu automatically.
7.7 Output Test

7 The device provides Output Test Mode to test all outputs. Through this mode, there will be real
operations, such as contact closing and GOOSE output value change, triggered by the device to
test output circuits and links. So, protection functions outputs and the connecting primary
equipments are affected. The output signals generated by output test are not recorded, while the
entering and exiting of output test mode will be recorded in Superv Events. During the output test,
the protection functions will not stop, nor will the all recording functions.
Output test can be gained via the local LCD or virtual HMI of a debugging PC, the corresponding
content can be viewed through the following menu paths:
 Contacts Outputs
Main Menu  "Test"  "Device Test"  "Contact Outputs"
 GOOSE Outputs
Main Menu  "Test"  "Device Test"  "GOOSE Outputs"

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7 System Functions
Dismantle the wiring connection if any influence on relevant primary

equipment is undesired. The output test will cause operation of relay
contacts through secondary circuit and GOOSE link.
7.8 Target Reset
The device provides target reset which can be used to reset local signals (including magnetic
latching output relays), latched LEDs, and confirm pop-up windows of reports. The function does
not affect the protection logic and communication function. There are several ways to reset.
1. Reset via local HMI
 Access menu path: MainMenu  "Local Cmd"  "Reset Target"
 Press the command pushbutton “ESC”+“ENT” on operation panel of the device under
main interface
 Press the command pushbutton " TARGET RESET" on operation panel of the device
2. Reset via virtual HMI
Access menu path: MainMenu  "Local Cmd"  "Reset Target"
3. Reset via binary input
Energize the binary input "BI_RstTarg"
4. Reset via IEC61870-5-103

7
Use ASDU20, INF19 of IEC61870-5-103 protocol
5. Reset via remote control
Use standard remote service of corresponding protocol
7.9 Switch Setting Groups
For different applications users can save the respective function settings in so-called settings
groups, and if necessary enable them quickly. Up to 20 different settings groups can be saved in
the device. In the process, only one settings group is active at any given time. During operation,
the operator can switch between setting groups.
The device will be temporarily blocked during switching setting groups. During temporary device
blocking, the device will loss protection functions and communication functions. Alarm signals
"Fail_Device" and "Alm_Device" will be issued. There are several ways to switch setting groups.
1. Switch via local HMI

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7 System Functions
 Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings",

change the value of the setting [Active_Grp]
 Press the command pushbutton “MENU” under main interface (password is required)
2. Switch via virtual HMI
Access menu path: MainMenu  "Setting"  "Global Settings"  "System Settings", modify
the setting [Active_Grp]
3. Switch via communication client
The communication protocols IEC 60870-5-103 or IEC 61850 can be used for switching the
setting groups via a communication connection.
 Use "General Service" of IEC61870-5-103 protocol to modify the setting [Active_Grp]
 Use "SelectActiveSG" of IEC61850 protocol to switch setting groups.
4. Switch via binary signals
The device also provides an available function by configuring associated binary signals via
PCS-Studio to switch setting group, which can be external binary inputs or internal logic signals.
By default, no binary signals are configured, so the function is invalid. (The specificed
confiuration method can refer to the application manual).
Each input signal is coded with a sequence number that corresponds to a setting group. When
the associated input signal changes, the device scans all input signals and selects the input
with the smallest sequence number as the valid input. The device switches to the setting range
corresponding to the input signal. The device can switch up to 20 setting groups.

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8 Hardware
8 Hardware
Table of Contents
8.1 Overview........................................................................................................... 8-1

8.2 Typical Wiring .................................................................................................. 8-4
8.3 CT Requirement ............................................................................................... 8-7
8.4 Plug-in Module Description ............................................................................ 8-9
8.4.1 Human-machine Interface Module (NR6855/NR6856)........................................................ 8-9
8.4.2 Power Supply Module (NR6305/NR6310/NR6311) ............................................................. 8-9
8.4.3 CPU Module (NR6106) ...................................................................................................... 8-12
8.4.4 Analog Input Module (NR6641) .......................................................................................... 8-16
8.4.5 Binary Input Module (NR6601/NR6604/NR6610/NR6611)................................................ 8-19
8.4.6 Binary Output Module (NR6651/NR6652/NR6660/NR6663) ............................................ 8-27
8.4.7 Binary Input/Output Module (NR6661)............................................................................... 8-32
List of Figures
Figure 8.1-1 Hardware diagram.................................................................................................. 8-1
Figure 8.1-2 Front view of this device ......................................................................................... 8-3
Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules) ............................ 8-3
Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules) ........................... 8-4 8
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules) ......................... 8-4
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules)...................................................... 8-5
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules)........................ 8-6
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules) .................................................... 8-7
Figure 8.4-1 View of power supply module ............................................................................... 8-10
Figure 8.4-2 View of CPU module .............................................................................................. 8-14
Figure 8.4-3 Connection of communication terminal ............................................................ 8-16
Figure 8.4-4 Jumpers of printer/RS-485 port .......................................................................... 8-16
Figure 8.4-5 Schematic diagram of CT circuit automatically closed ................................... 8-17

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8 Hardware
Figure 8.4-6 Terminal definition of analog input module ...................................................... 8-18
Figure 8.4-7 connection examples .......................................................................................... 8-19
Figure 8.4-8 Voltage dependence for binary inputs .............................................................. 8-20
Figure 8.4-9 View of binary input module (NR6601A) ........................................................... 8-21
Figure 8.4-10 View of binary input module (NR6604A) ......................................................... 8-22
Figure 8.4-11 View of binary input module (NR6610A).......................................................... 8-24
Figure 8.4-12 View of binary input module (NR6611A).......................................................... 8-26
Figure 8.4-13 View of binary output module NR6651A ......................................................... 8-28
Figure 8.4-14 View of binary output module NR6651B ......................................................... 8-29
Figure 8.4-15 View of binary output module NR6652A ......................................................... 8-30
Figure 8.4-16 View of binary output module (NR6660A) ....................................................... 8-31
Figure 8.4-17 View of binary output module (NR6663A) ....................................................... 8-32
Figure 8.4-18 View of binary input/output module (NR6661A) ............................................. 8-33
List of Tables
Table 8.4-1 Terminal definition of power supply module (ring-ferrule-terminal) ..................... 8-10
Table 8.4-2 Terminal definition of power supply module (pin-ferrule-terminal)....................... 8-11
Table 8.4-3 Configuration and terminal definition of CPU module........................................... 8-14
Table 8.4-4 Terminal definition and description of binary input module (NR6601A)............... 8-21
Table 8.4-5 Terminal definition and description of binary input module (NR6604A)............... 8-23
8 Table 8.4-6 Terminal definition and description of binary input module (NR6610A) .............. 8-24
Table 8.4-7 Terminal definition and description of binary input module (NR6611A) .............. 8-26
Table 8.4-8 Terminal definition and description of NR6661A ................................................... 8-33

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8 Hardware
8.1 Overview
The modular design of this device allows this device to be easily upgraded or repaired by a qualified
service person. The faceplate is hinged to allow easy access to the configurable modules, and
back-plugging structure design makes it easy to repair or replace any module.
This device adopts one 32-bit ARM core in the CPU chip as control core for management and
monitoring function, and adopts another 32-bit ARM core in the CPU chip for all the protection
calculation. The parallel processing of sampled data can be realized in each sampling interval to
ensure ultrahigh reliability and safety of the device.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in anti-
interference. See Figure 8.1-1 for the hardware diagram.
External
Binary Input
Conventional CT/VT A/D

Output
ARM1
Relay
A/D
Pickup
ECVT Relay
ETHERNET
+E
LCD
Clock SYN
Power
Uaux LED ARM2
Supply
RJ45
Keypad
PRINT
Figure 8.1-1 Hardware diagram 8

The working process of the device is shown in above figure: the currents and voltages from
conventional CT/VT are converted into small voltage signal and sent to ARM1 core after filtered
and A/D conversion for protection calculation and fault detector respectively. The ARM1 core carries
out fault detector, protection logic calculation, tripping output, and the ARM2 core performs SOE
(sequence of event) record, waveform recording, printing, communication between the device and
SAS and communication between HMI and CPU. When the fault detector detects a fault and picks
up, the positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the device
(conventional CT/VT), and the mode of binary output (conventional binary output or GOOSE binary
output). The configurations for PCS S series based on microcomputer are classified into standard
and optional modules.

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8 Hardware
Table 8.1-1 Module configuration of this device
Module ID Module description Remark

NR6855/NR6856 Human machine interface module (HMI module) Mandatory
NR6305/6310/NR6311 Power supply module (PWR module) Mandatory
NR6106 Main CPU module (CPU module) Mandatory
NR6641 Analog input module (AI module) Mandatory
NR6601/NR6604/NR6610/NR6611 Binary input module (BI module) Mandatory
NR6651/NR6652/NR6660/NR6663 Binary output module (BO module) Mandatory
NR6661 Binary Input/output module (BI/BO module) Mandatory
 HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
 PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.
 CPU module provides functions like communication with SAS, event record, setting
management etc., and performs filtering, sampling, protection calculation and fault detector
calculation.
 AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
 BI module provides binary inputs via opto-couplers with rating voltage among AC110V/220V
or DC24V/48V/110V/125V/220V/250V (configurable).
 BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
 BI/BO module not only provides binary inputs via opto-couplers with rating voltage among
AC110V/220V or DC24V~250V (configurable), but also provides output contacts for tripping,
and signal output contact for annunciation signal, remote signal, fault and disturbance signal,
8 operation abnormal signal, etc.
Following figures show front and rear views of this device respectively.

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8 Hardware
Figure 8.1-2 Front view of this device
Figure 8.1-3 Typical rear view of this device (pin-ferrule-terminal modules)

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8 Hardware
Figure 8.1-4 Typical rear view of this device (ring-ferrule-terminal modules)
8.2 Typical Wiring
B01 B02 & B03 B04 B05 B06 P1 B01 B02 & B03 B04 P1
NR6106AA NR6641-4I4U Option Option Option NR6310A NR6106AA NR6641-4I4U Option NR6310A
BI_01+ 01 BI_01+ 01
01 IT ITn 02 01 IT ITn 02
BI_01- 02 BI_01- 02
03 IF IFn 04 BI_02+ 03 03 IF IFn 04 BI_02+ 03
BI_02- 04 BI_02- 04
NET 05 I3 I3n 06 BI_COM 05 NET 05 I3 I3n 06 BI_COM 05
BI_03 06 BI_03 06
LC 07 I4 I4n 08 LC 07 I4 I4n 08
BI_04 07 BI_04 07
LC BI_05 08 LC BI_05 08
09 10 09 10
BI_06 09 BI_06 09
11 12 BI_07 10 11 12 BI_07 10
BI_08 11 BI_08 11
13 14 BI_09 12 13 14 BI_09 12
13 13
8
15 16 BO_01 15 16 BO_01
14 14
17 UT UTn 18 15 17 UT UTn 18 15
BO_02 BO_02
16 16
01 1A 19 UF UFn 20 17 01 1A 19 UF UFn 20 17
BO_03 BO_03
02 1B 18 02 1B 18
03 SG ND
21 UT2 UT2n 22 19 03 SGND
21 UT2 UT2n 22 19
BO_04 BO_04
04 2A 20 04 2A 20
23 UF2 UFn 24 23 UF2 UFn 24
05 2B 21 05 2B 21
06 SG ND BO_05 06 SGND
BO_05
22 22
07 SYN+ 07 SYN+
23 23
08 SYN- BO_Fail 08 SYN- BO_Fail
24 24
09 SGND 09 SGND
PWR+ 25 PWR+ 25
10 SYN-TTL 10 SYN-TTL
PWR- 26 PWR- 26
CONSOLE Ground CONSOLE Ground
Figure 8.2-1 Typical hardware configuration 1 (pin-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

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8 Hardware
Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 IT
0202
SGND 0103
0203
485-2A 0104 IF
COM
0204
485-2B 0105
0205
SGND 0106
I3
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 I4
0208
TTL 0110
Multiplex RJ45
AI plug-in module
P101 + BI_01
P102 -
- P103 + BI_02
P104 -
P106 + BI_03 0217

UT
0218
P107 + BI_04 0219
UF
0220
PWR plug-in module
0221
P112 + BI_09 UT2
0222
P105 0223
P113 UF2
BO_01 0224
P114
P115
P116 BO_02
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
8
External DC power Power
supply P126 Supply
PWR-
Grounding Bus
Figure 8.2-2 Typical wiring 1 (pin-ferrule-terminal modules)

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8 Hardware
B01 B02 & B03 B04 B05 B06 B02 & B03 B01 B02 & B03 B04 P1
NR6106AA NR6641-4I4U Option Option Option NR6641-4I4U NR6106AA NR6641-2I4U Option NR6305A
01 IT ITn 02 01 IT ITn 02 01 IT ITn 02 01 BI_01+ BI_01- 02
03 IF IFn 04 03 IF IFn 04 03 IF IFn 04 03 BI_02+ BI_02- 04
NET 05 I3 I3n 06 05 I3 I3n 06 NET 05 06 05 BI_COM BI_03 06
LC 07 I4 I4n 08 07 I4 I4n 08 LC 07 08 07 BI_04 BI_05 08
LC 09 10 LC
09 10 09 10 09 BI_06 BI_07 10
11 12 11 12 11 12 11 BI_08 BI_09 12
13 14 13 14 13 14 13 BO_01 14
15 16 15 16 15 16 15 BO_02 16
17 UT UTn 18 17 UT UTn 18 17 UT UTn 18 17 BO_03 18
01 1A 19 UF UFn 20 19 UF UFn 20 01 1A 19 UF UFn 20 19 BO_04 20

02 1B 02 1B
03 SGND
21 UT2 UT2n 22 21 UT2 UT2n 22 03 SGND 21 UT2 UT2n 22 21 BO_05 22
04 2A 04 2A
23 UF2 UFn 24 23 UF2 UFn 24 23 UF2 UFn 24 23 BO_Fail 24
05 2B 05 2B
06 SGND 06 SGND
25 PWR+ PWR- 26
07 SYN+ 07 SYN+
08 SYN- 08 SYN-
09 SGND 09 SGND
10 SYN-TTL 10 SYN-TTL
CONSOLE CONSOLE
Ground
Figure 8.2-3 Typical hardware configuration 2 (ring-ferrule-terminal modules)
The following wiring is given based on above hardware configuration

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8 Hardware
Optional optical or electrical Ethernet to SCADA

485-1A 0101 0201
COM
485-1B 0102 IT
0202
SGND 0103
0203
485-2A 0104 IF
COM
0204
485-2B 0105
0205
SGND 0106
I3
SYN+ 0107 0206
Clock SYN
SYN- 0108 0207
SGND 0109 I4
0208
TTL 0110
Multiplex RJ45
AI plug-in module
P101 + BI_01
P102 -
- P103 + BI_02
P104 -
P106 + BI_03 0217

UT
0218
P107 + BI_04 0219
UF
0220
PWR plug-in module
0221
P112 + BI_09 UT2
0222
P105 0223
P113 UF2
BO_01 0224
P114
P115
P116 BO_02
P121
P122 BO_05
P123
P124 BO_Fail
PWR+ P125
8
External DC power Power
supply P126 Supply
PWR-
Grounding Bus
Figure 8.2-4 Typical wiring 2 (ring-ferrule-terminal modules)
8.3 CT Requirement
 CT Requirement
Generally, CT saturation will cause a certain time delay to the operation of a protection, which is
obvious for inverse-time overcurrent protection. When the maximum fault current is far greater than
the current seting, the operating time delay generated at this time can be ignored. If the maximum
fault current is slightly greater than the current setting, the operating time delay generated at this
time is equivalent to the primary time constant of the system. When there is an upper-lower
coordination relationship, the effect of this time delay needs to be considered. Generally, the

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requirements for CT are as follows:
′
𝐸𝑠𝑙 < 𝐸𝐴𝐿𝐹
In where:
′
𝐸𝑠𝑙 is the secondary electromotive force required for the maximum prospective fault current
According to the operating characteristics, the phase overcurrent protection and earth fault
overcurrent protection are divided into the following two situations:
For instantaneous overcurrent protection, definite-time overcurrent protection and earth fault
overcurrent protection:
′
𝐸𝑠𝑙 = 𝐼𝑝𝑐𝑓 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏′ )/𝐼𝑝𝑟
For inverse-time overcurrent protection and earth fault overcurrent protection:

′
𝐸𝑠𝑙 = 20 × 𝐼𝑠𝑒𝑡 × (𝑅𝑐𝑡 + 𝑅𝑏′ )
𝐼𝑠𝑒𝑡 is the the inverse-time reference current setting or 1.1 times of the maximum load current.
For the directional overcurrent protection and earth fault overcurrent protection, try to choose the
low remanence or no remanence CT.
The parameters are defined as follows:
𝐼𝑝𝑐𝑓 Maximum primary fault current (amps)
𝐼𝑝𝑟 Rated primary current (amps)
Actual secondary load resistance
𝑅𝑏′ = 𝑅𝑟 + 2 × 𝑅𝐿
𝑅𝑏′
𝑅𝑟 : Protection device phase current input impedance, it takes 0.01ohm
8 𝑅𝐿 : The resistance from protection device to CT single wire
Inverse-time reference current setting or 1.1 times of the maximum load current
𝐼𝑠𝑒𝑡
(amps)
 Example
The parameters are as follows:
5P30, 𝐼𝑝𝑟 =2000A, 𝐼𝑠𝑟 =5A, 𝑅𝑐𝑡 = 1.0ohm , 𝑆𝑟 =60VA, 𝐼𝑝𝑐𝑓 =40000A, 𝑅𝐿 =0.5ohm, 𝑅𝑟 =0.01ohm,
the primary time constant of the system is 80ms, calculate that whether the CT can meet the
requirements of definite-time overcurrent protection.
𝐸𝐴𝐿𝐹 = 𝐴𝐿𝐹 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑍𝑏 ) = 30 ∗ 5 ∗ (1.0 + 60/(5 ∗ 5)) = 510V

′
𝐸𝑠𝑙 = 𝐼𝑝𝑐𝑓 × 𝐼𝑠𝑟 × (𝑅𝑐𝑡 + 𝑅𝑏′ )/𝐼𝑝𝑟 = 40000 ∗ 5 ∗ (1.0 + (0.01 + 2 ∗ 0.5))/2000 = 201V

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′
𝐸𝑠𝑙 < 𝐸𝐴𝐿𝐹 , it can meet the requirements of definite-time overcurrent protection.
8.4 Plug-in Module Description

The device consists of power supply module (PWR), main CPU module (CPU), AI module, BI
module, BO plug-in module and NET-DSP plug-in module. Terminal definitions and application of
each plug-in module are introduced as follows.
8.4.1 Human-machine Interface Module (NR6855/NR6856)

The human machine interface (HMI) module is installed on the front panel of this device. It is used
to observe the running status and event information on the LCD, and configure the protection
settings and device operation mode. It can help the user to know the status of this device and
detailed event information easily, and provide convenient and friendly access interface for the user.
8.4.2 Power Supply Module (NR6305/NR6310/NR6311)

The power supply module is a DC/DC converter with electrical insulation between input and output.
It has an input voltage range as described in Chapter 2 Technical Data. The standardized output
voltages are +5Vdc and +12Vdc. The tolerances of the output voltages are continuously monitored.
The +5Vdc output provides power supply for all the electrical elements that need +5Vdc power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device
is in cold reserve.

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Figure 8.4-1 View of power supply module
Four types of power supply modules are provided: NR6305A, NR6305B, NR6310A and NR6311A.
The NR6305B is same as the NR6305A except that the NR6305B can support at least 500ms
power supply interruption. The terminal definition of NR6311A is same as that of NR6310A except
that the input voltage of NR6311A is 18~72Vdc.
 NR6305A & NR6305B
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure binary
8 output. A 26-pin connector is fixed on the power supply module. The terminal definition of the
connector is described as below.
Table 8.4-1 Terminal definition of power supply module (ring-ferrule-terminal)
Pin No. Symbol Description

01 BI_01+
The No.1 programmable binary input
02 BI_01-
03 BI_02+
04 BI_02-
05 BI_COM The common negative connection of the BI_03 to BI_09
06 BI_03 The No.3 programmable binary input

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13
BO_01 The No.1 programmable binary output
14
15
16
17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
 NR6310A & NR6311A
The power supply module also provides 9 binary inputs, 5 binary outputs and a device failure binary
output. A 22-pin connector and a 4-pin connector are fixed on the power supply module. The
terminal definition of the connector is described as below.
Table 8.4-2 Terminal definition of power supply module (pin-ferrule-terminal)

01 BI_01+
02 BI_01-
03 BI_02+
8
04 BI_02-
05 BI_COM The common negative connection of the BI_01 to BI_09
22-pin
13
14
15
16

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17
18
19
20
21
22
23
BO_Fail The device failure signal output
24
4-pin
25 PWR+ DC power supply positive input
26 PWR- DC power supply negative input
Grounded connection of the power supply
The standard rated voltage of the PWR module is self-adaptive to 18~72Vdc

(NR6311), 88~300Vdc (NR6310) or 88~275Vac (NR6305). For a non-
standard rated voltage power supply module please specify when place
order, and check whether the rated voltage of power supply module is the
same as the voltage of power source before the device being put into
service.
The PWR module a grounding screw for device grounding. The grounding
screw shall be connected to grounding screw and then connected to the
earth copper bar of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent

EMI, so effective grounding must be ensured before the device is put into
service.
8.4.3 CPU Module (NR6106)

8 The CPU module is the central part of this device, and contains a multi-core 32-bit powerful
processor and some necessary electronic elements. This powerful processor performs all of the
functions for this device: protection function, communication function, human-machine interface
function and so on. There are several A/D conversion circuits on this module, which are used to
convert the AC analog signals to corresponding DC signals for fulfilling the demand of the electrical
level standard. A high-accuracy clock chip is contained in this module, it provide accurate current
time for this device.
The main functional details of the CPU module are listed as below:
 Protection calculation and logical judgment function
The CPU module can calculate protective elements (such as overcurrent element) on the basis
of the analog sampled values (voltages and currents) and binary inputs, then it does logical
judgment function and decides whether the device needs to trip or close.

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 Communication function
The CPU module can effectively manage all communication procedures, and reliably send out
some useful information through its various communication interfaces. These interfaces are
used to communicate with a SAS or a RTU. It also can communicate with the human machine
interface module. If an event occurs (such as SOE, protective tripping event etc.), this module
will send out the relevant event information through these interfaces, and make it be easily
observed by the user.
 Support of protocols
MMS, GOOSE independent networking
MMS, GOOSE hybrid networking
 Auxiliary calculation
Based on the voltage and current inputs, the CPU module also can calculate out the metering
values, such as active power, reactive power and power factor etc. All these values can be
sent to a SAS or a RTU through the communication interfaces.
 Human-machine interface function
This module can respond the commands from the keypad of this device and show the results
on the LCD and LED indicators of this device. It also can show the operation situation and
event information for the users through the LCD and LED indicators.
 Time synchronization
This module has a local clock chip and an interface to receive time synchronized signals from
external clock source. These signals include PPS (pulse per second) signal and IRIG-B signal.
Basing on the timing message (from SAS or RTU) and the PPS signal, or basing on the IRIG-
B signal, this module can synchronize local clock with the standard clock.

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Figure 8.4-2 View of CPU module
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.

8 The configuration and terminal definition of the CPU modules are listed in following table.
Table 8.4-3 Configuration and terminal definition of CPU module
Sampling Terminal
Module ID Interface Usage Physical Layer
channel No.
2 RJ45
Ethernet
- - Ethernet communication Twisted pair wire
2 SFP
Ethernet
NR6106AA 16 01 A
RS-485 02 B To SCADA Twisted pair wire
03 SGND
04 A
RS-485 To SCADA or printer Twisted pair wire
05 B

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06 SGND
07 SYN+
RS-485 08 SYN- Cable
To clock synchronization
09 SGND
TTL 10 TTL Cable
1 RJ45
- - For debugging Twisted pair wire
Ethernet
4 SFP
Ethernet
1 ST To clock synchronization Optical fiber
NR6106AH 16 - -
connector (PPS/IRIG-B) (multi-mode)
1 RJ45
Ethernet
2 RJ45
Ethernet
2 SFP
Ethernet
01 A
RS-485 02 B To SCADA Twisted pair wire
NR6106AP 16 03 SGND
04 A
RS-485 05 B To SCADA or printer Twisted pair wire
06 SGND
1 BNC - - To clock synchronization
1 RJ45
Ethernet
The correct connection is shown in Figure 8.4-3. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the 8
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.

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Twisted pair wire

A 01
B 02
COM
SGND 03
cable with single point earthing

To the screen of other coaxial
04
Twisted pair wire

SYN+ 01
Clock SYN
SYN- 02
SGND 03
04
Cable
RTS 05
PRINT
TXD 06
SGND 07
Figure 8.4-3 Connection of communication terminal
Figure 8.4-4 Jumpers of printer/RS-485 port

8
The 2nd RS-485 port also can be configured as a printer port through the
jumpers “J10” and “J11”.
Jumper RS-485 Printer

J10 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
J11 Pin-1 and Pin-2 are connected Pin-2 and Pin-3 are connected
8.4.4 Analog Input Module (NR6641)

The analog input module is applicable for power plant or substation with conventional VT and CT,
and it can transform high AC input values to relevant low AC output value, which are suited to the
analog inputs of the CPU module. The transformers are used both to step-down the currents and
voltages to levels appropriate to the device’s electronic circuitry and to provide effective isolation

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between this device and the power system. A low pass filter circuit is connected to each transformer
(CT or VT) secondary circuit for reducing the noise of each analog AC input signal.
For the analog input module, if the plug is not put in the socket, external CT circuit is closed itself.
Just shown as below.
Plug
Socket
In
Out
plug is not put in the socket
In
Out
Put the plug in the socket
Figure 8.4-5 Schematic diagram of CT circuit automatically closed
There are several types of analog input modules. The rated current is adaptive (1A/5A). Please
declare which kind of AI module is needed before ordering. Maximum linear range of the current 8
converter is 40In.
 NR6641-4I4U: 4CT+4VT
The terminal definition of the analog input module is shown as below.

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NR6641-4I4U
01 I1 I1n 02
03 I2 I2n 04
05 I3 I3n 06
07 I4 I4n 08
09 10
11 12
13 14
15 16
17 U1 U1n 18
19 U2 U2n 20
21 U3 U3n 22
23 U4 U4n 24
Figure 8.4-6 Terminal definition of analog input module
NEVER allow the current transformer (CT) secondary circuit connected to

this device to be opened while the primary system is energized. The opened
CT secondary circuit will produce a dangerously high voltage. If this safety
precaution is disregarded, personal death, severe personal injury or
considerable equipment damage will occur.
8
Each analog input channel can be configured according to practical
application through PCS-Studio.
Some connection examples of the current transformers and voltage transformers which are
supported by this relay are shown in this section. If one of the analog inputs has no input in a
practical engineering, the relevant input terminals should be disconnected.

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T 52 T
R
F 52
IT
F
ITn
IF
IFn
UT
UTn
UF
UFn
UT2
UT2n
UF2
UF2n
Figure 8.4-7 connection examples
8.4.5 Binary Input Module (NR6601/NR6604/NR6610/NR6611)

The binary input module contains some binary inputs which are used to monitor the contact
positions of the corresponding bay, and all the binary inputs are configurable through PCS-Studio
according to practical application.
There are four kinds of BI modules available, NR6601A, NR6604A, NR6610A and NR6611A. The
binary input module can respectively provide 25, 13, 32 or 14 binary inputs.
The rated voltage of binary input is optional: 24Vdc, 30Vdc, 48Vdc, 110Vdc,
125V, 220V, 110Vac or 220Vac (@50Hz), which must be specified when
placed order. It is necessary to check whether the rated voltage of binary
input module complies with site DC power supply rating before put this
device in service. 8

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Voltage
300
157.5
138.6
125
110
78.75
69.3
62.5
55 Operation
30.24
24 Operation uncertain
15.12
12
No operation
0 24V 48V 110V 125V 220V 250V
Figure 8.4-8 Voltage dependence for binary inputs
 NR6601A
Each BI module is with a 26-pin connector for 25 binary inputs which share one common negative
power input and can be configurable. The pickup voltages and drop-out voltages of the binary
8 inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from 50%Un
to 80%Un.

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01 BI_01 BI_02 02
03 BI_03 BI_04 04
05 BI_05 BI_06 06
07 BI_07 BI_08 08
09 BI_09 BI_10 10
11 BI_11 BI_12 12
13 BI_13 BI_14 14
15 BI_15 BI_16 16
17 BI_17 BI_18 18
19 BI_19 BI_20 20
21 BI_21 BI_22 22
23 BI_23 BI_24 24
25 BI_25 BI_COM 26
Figure 8.4-9 View of binary input module (NR6601A)
A 26-pin connector is fixed on the binary input module. The terminal definition of the connector is
described as below.
Table 8.4-4 Terminal definition and description of binary input module (NR6601A)

02
03
BI_02
BI_03
8

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26 BI_COM The common negative connection of the BI_01 to BI_25.
 NR6604A
Each BI module is with a 26-pin connector for 13 binary inputs, each binary input has independent
negative power input and is configurable. The pickup voltages and drop-out voltages of the binary
inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from 50%Un
to 80%Un.
01 BI_01 Opto01- 02
03 BI_02 Opto02- 04
05 BI_03 Opto03- 06
07 BI_04 Opto04- 08
09 BI_05 Opto05- 10
11 BI_06 Opto06- 12
13 BI_07 Opto07- 14
8 15 BI_08 Opto08- 16
17 BI_09 Opto09- 18
19 BI_10 Opto10- 20
21 BI_11 Opto11- 22
23 BI_12 Opto12- 24
25 BI_13 Opto13- 26
A 26-pin connector is fixed on the binary input module. The terminal definition of the connector is
described as below.

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01 BI_01 Configurable binary input 1
02 Opto01- Negative pole of power supply of configurable binary input 1
 NR6610A 8
Each BI module is with two 18-pin connectors for 32 binary inputs. The first 16 binary inputs share
one common negative power input and the last 16 binary inputs share another common negative
power input. All binary inputs are configurable. The pickup voltages and drop-out voltages of the
binary inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range is from
50%Un to 80%Un.

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01 BI_01 19 BI_17
02 BI_02 20 BI_18
03 BI_03 21 BI_19
04 BI_04 22 BI_20
05 BI_05 23 BI_21
06 BI_06 24 BI_22
07 BI_07 25 BI_23
08 BI_08 26 BI_24
09 BI_09 27 BI_25
10 BI_10 28 BI_26
11 BI_11 29 BI_27
12 BI_12 30 BI_28
13 BI_13 31 BI_29
14 BI_14 32 BI_30
15 BI_15 33 BI_31
16 BI_16 34 BI_32
17 BI_COM 35 BI_COM
18 BI_COM 36 BI_COM
The terminal definition of the connector is described as below.
Pin Pin No. Symbol Description

8 03
04
BI_03
BI_04
18-pin

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17
BI_COM The common negative connection of the BI_01 to BI_16.
18
18-pin
35
BI_COM The common negative connection of the BI_17 to BI_32.
36
 NR6611A
Each BI module is with two 18-pin connectors for 14 binary inputs, each binary input has
independent negative power input and is configurable. The pickup voltages and drop-out voltages
of the binary inputs are settable by the setting [U_Pickup_BI] and [U_DropOut_BI], and the range
is from 50%Un to 80%Un.

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01 19
02 20
03 BI_01 21 BI_08
04 Opto01- 22 Opto08-
05 BI_02 23 BI_09
06 Opto02- 24 Opto09-
07 BI_03 25 BI_10
08 Opto03- 26 Opto10-
09 BI_04 27 BI_11
10 Opto04- 28 Opto11-
11 BI_05 29 BI_12
12 Opto05- 30 Opto12-
13 BI_06 31 BI_13
14 Opto06- 32 Opto13-
15 BI_07 33 BI_14
16 Opto07- 34 Opto14-
17 35
18 36
The terminal definition of the connector is described as below.

01 Blank -
02 Blank -
8 03
04
BI_01
Opto01-
Configurable binary input 1
Negative pole of power supply of configurable binary input 1
18-pin

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17 Blank -
18 Blank -
19 Blank -
20 Blank -
18-pin
35 Blank -
36 Blank -
8.4.6 Binary Output Module (NR6651/NR6652/NR6660/NR6663)

The binary output module consists of some necessary contact outputs, and the binary outputs are
used as tripping and closing (protection, auto-reclosing or remote control) outputs or signal outputs.
It can receive tripping commands or closing commands from the CPU module, and then executes
these commands. It also can output some alarm signals from the CPU module.
The device can provide five types of binary output modules: NR6651A, NR6651B, NR6652A,
NR6660A and NR6663A.
 NR6651A 8
The NR6651A provides 13 normal open contacts (NOC).
A 26-pin connector is fixed on the binary input module.
The terminal definition of the connector is shown as below.

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BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-13 View of binary output module NR6651A
 NR6651B
The NR6651B provides 11 normal open contacts (NOC, the first 11 contacts) and 2 normal close
contacts (NCC, the last 2 contacts).
The terminal definition of the connector is shown in as below.

8

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BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
Figure 8.4-14 View of binary output module NR6651B
 NR6652A
The NR6652A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).
The terminal definition of the connector is shown in as below. 8

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BO_01 01 02
03 04
BO_02 05 06
07 08
BO_03 09 10
11 12
BO_04 13 14
15 16
17 18
BO_05 19 20
BO_06 21 22
BO_07 23 24
BO_08 25 26
Figure 8.4-15 View of binary output module NR6652A
 NR6660A
The NR6660A provides 17 normally open contacts (NOC, the first 17 contacts) and 2 normally
close contacts (NCC, the 16th and the 17th contacts).
Two 18-pin connectors are fixed on the binary input module.
The terminal definition of the connector is shown in Figure 8.4-16.

8

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BO_01 01 02
BO_02 03 04
BO_03 05 06
BO_04 07 08
BO_05 09 10
BO_06 11 12
BO_07 13 14
BO_08 15 16
BO_09 17 18
BO_10 19 20
BO_11 21 22
BO_12 23 24
BO_13 25 26
BO_14 27 28
BO_15 29 30
BO_16 32
31
BO_16 33
BO_17 35
34
BO_17 36
Figure 8.4-16 View of binary output module (NR6660A)
 NR6663A
The NR6663A provides 4 normal open contacts (NOC, the first 4 contacts) with heavy capacity for
controlling the circuit breaker directly, and provides 4 general normal open contacts (NOC, the last
4 contacts).
Two 18-pin connectors are fixed on the binary input module.
The terminal definition of the connector is shown as below. 8

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01 02
03 04
BO_01
Heavy-capacity tripping contact

05 06
07 08
BO_02
09 10
11 12
BO_03
13 14
15 16
BO_04
17 18
19 20
21 22
General tripping/signaling contact

BO_05
23 24
25 26
BO_06
27 28
29 30
BO_07
31 32
33 34
BO_08
35 36
Figure 8.4-17 View of binary output module (NR6663A)
Each binary output can be set as a specified tripping output contact or a

signal output contact through PCS-Studio according to practical application.
8.4.7 Binary Input/Output Module (NR6661)
8 NR6661A module provides both binary inputs and binary outputs.
Two 18-pin connectors are fixed on the NR6661A module:
The upper 18-pin connector provides 16 binary inputs, the supported rated voltages of binary inputs
are listed in Chapter 2 Technical Data.
The lower 18-pin connector provides 6 normally open contacts (NOC) and 2 normally open contacts
& normally closed contacts (NOC/NCC). These binary outputs are controlled by pickup relay.

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01 BI_01
02 BI_02
03 BI_03
04 BI_04
05 BI_05 BO_01 19 20
06 BI_06 BO_02 21 22
07 BI_07 BO_03 23 24
08 BI_08 BO_04 25 26
09 BI_09 BO_05 27 28
10 BI_10 BO_06 29 30
11 BI_11 BO_07_NO 32
31
12 BI_12 BO_07_NC 33
13 BI_13 BO_08_NO 35
34
14 BI_14 BO_08_NC 36
15 BI_15
16 BI_16
COM-
17 (01-16)
COM-
18
(01-16)
Figure 8.4-18 View of binary input/output module (NR6661A)
The terminal definition of NR6661A is described as below.
Table 8.4-8 Terminal definition and description of NR6661A

03
04
BI_03
BI_04
8
18-pin

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8 Hardware
17 COM-
The common negative connection of the BI_01 to BI_16.
18 (01-16)
19 The No.01 binary output contact. It is a normally open contact
BO_01
20 (NOC).
21
BO_02 The No.02 binary output contact. It is a normally open contact.
22
23
24
25
26
27
18-pin BO_05 The No.05 binary output contact. It is a normally open contact.
28
29
30
31
The No.07 binary output contact. It can be selected as a normally
32 BO_07
open contact or a normally closed contact (NCC).
33
34
The No.08 binary output contact. It can be selected as a normally
35 BO_08
open contact or a normally closed contact.
36

Date: 2021-04-20
9 Settings
9 Settings
Table of Contents
9.1 Global Settings ................................................................................................ 9-1

9.1.1 System Settings ................................................................................................................... 9-1
9.1.2 Device Settings .................................................................................................................... 9-1
9.1.3 Communication Settings ...................................................................................................... 9-3
9.1.4 Disturbance Fault Recording Settings ............................................................................... 9-18
9.1.5 Label Settings..................................................................................................................... 9-18
9.1.6 Clock Synchronization Settings.......................................................................................... 9-18
9.1.7 OutMap Settings................................................................................................................. 9-21
9.1.8 Supervision Settings........................................................................................................... 9-21
9.2 Protection Settings ........................................................................................ 9-21

9.2.1 Distance Protection Settings .............................................................................................. 9-21
9.2.2 Phase Overcurrent Protection Settings.............................................................................. 9-22
9.2.3 DPFC Overcurrent Protection Settings .............................................................................. 9-25
9.2.4 Undervoltage Protection Settings ...................................................................................... 9-26
9.2.5 Breaker Failure Protection Settings ................................................................................... 9-27
9.2.6 Switch-on-to-Fault ProtectionSettings................................................................................ 9-27
9.2.7 Automatic Reclosure Settings ............................................................................................ 9-28
9.2.8 Fault Location Settings ....................................................................................................... 9-30
9.2.9 ATS Settings ....................................................................................................................... 9-30

9
9.3 Measurement and Control Settings ............................................................. 9-30
9.3.1 Function Settings................................................................................................................ 9-30
9.3.2 Double Point Status Settings ............................................................................................. 9-31
9.3.3 Control Settings .................................................................................................................. 9-33
9.3.4 Interlocking Logic Settings ................................................................................................. 9-34
9.4 Logic Links..................................................................................................... 9-36

9.4.1 Function Links .................................................................................................................... 9-36

Date: 2021-04-20
9 Settings
9.4.2 GOOSE Sending Links ...................................................................................................... 9-36
9.4.3 GOOSE Receiving Links .................................................................................................... 9-36

Date: 2021-04-20
9 Settings
9.1 Global Settings

9.1.1 System Settings

The number of active setting group,
several setting groups can be
1 Active_Grp 1~20 1 - 1
configured for protection settings,
and only one is active at a time.
Name of the protected primary
Max 20
2 PrimaryEquip_Name - - - equipment, such as feeder,
characters
transformer, etc.
3 Opt_SysFreq 50, 60 50Hz Hz - The system frequency.
The logic setting used to select the
Direct; system feeding mode:
4 Opt_FeedingSystem AT - -
AT AT: auto-transformer feeding system
Direct: direct feeding system
Rated primary value of protection
5 Prot.I1n 0~9999 1000 A 1
phase CT
Rated secondary value of protection
6 Prot.I2n 1, 5 1 A -
phase CT
7 Prot.U1n 0~1100 10 kV 0.01 Rated primary value of protection VT
Rated secondary value of protection
8 Prot.U2n 1~200 100 V 0.01
VT
The logic setting determines that
whether the CT polarity of the
Disabled; protection CT is reversed.
9 Prot.En_RevCT Disabled - -
Enabled Enabled: The CT polarity is reversed
Disabled: The CT polarity is not
reversed
Disabled; Logic setting to put traction catenary
10 Prot.Trac.En_VT Enabled - -
Enabled VT into service
11 Prot.Fdr.En_VT
Disabled;
Enabled - -
Logic setting to put feeder VT into 9
Enabled service
9.1.2 Device Settings

Access path: MainMenu  Settings  Global Settings  Device Settings

Logic setting to enable/disable the
Disabled debugging port. Used for debugging
1 En_DebugPort Enabled - -
Enabled tool connection, program download,
variable debugging, etc.

Date: 2021-04-20
9 Settings

Disabled Logic setting to enable/disable the
2 En_TelnetPort Disabled - -
Enabled Telnet port.
Enabled: Connecting to the device
via the software Teldevice is
Disabled supported
3 En_VirtualLCDPort Enabled - -
Enabled Disabled: Connecting to the device
via the software Teldevice is not
supported
4 Ctrl_Password 000~999 111 - - The control password via local LCD.
Disabled Override control password via local
5 En_NoCtrlPwd Enabled - -
Enabled LCD
Enabled: all the events (including
disturbance records, supervision
events, IO events, control events)
will not pop up automatically in the
Disabled main graph of local LCD, they can
6 En_PopupRecord_Blkd Disabled - -
Enabled only be viewed by entering
corresponding menus.
Disabled: these events can pop up
in the main graph of local LCD
automatically.
This setting is used to set the voltage
7 Un_BinaryInput 24~250 220 V -
level of the binary input module.
DC
Power supply mode of binary input
8 Opt_Pwr_BI AC50Hz DC - -
module
AC60Hz
This setting is used to set pickup
9 U_Pickup_BI 50%Un~80%Un 63 % 0.1
voltage of the binary input module.
This setting is used to set drop-off
10 U_Dropoff_BI 50%Un~80%Un 55 % 0.1
voltage of the binary input module.
Monitoring window of binary input
11 Mon_Window_Jitter 0.000~500.000 1 s 0.001
jitter processing
9 12 Num_Blk_Jitter 2~500000 10 - 1
Times threshold to block binary input
status change due to jitter
Blocking window of binary input
13 Blk_Window_Jitter 0.000~500.000 1 s 0.001
status change due to jitter
Times threshold to initiate
immediately another blocking
14 Num_Reblk_Jitter 1~500000 10 - 1
window of binary input status
change due to continuous jitter
The logic setting to enable/disable
Disabled
15 En_Jitter_Blk Disabled - - the jitter processing function in case
Enabled
of binary input voltage variation

Date: 2021-04-20
9 Settings

Enabled: Conducting mode by high
power with constant current drain of
binary inputs is enabled. Now the
binary input will be considered to be
energized only when the
instantaneous active power rises to
a certain value together with
constant current drain during this
mode, so as to avoid mistaken
signal.
Disabled: Conducting mode by high
power with constant current drain of
binary inputs is disabled. Now the
binary input will be considered to be
Disabled
16 En_BICheckInstP Disabled - - energized with constant current
Enabled
drain without checking the
instantaneous active power.
The conducting mode by high power
with constant current drain of binary
inputs is only available in the device
equipped with some certain modules
(e.g.: NR6604A, NR6611A). If these
modules are not equipped, this
conducting mode will be
unavailable, so this setting will be
hidden.
This setting cooperates with the BI
debouncing time configuration of
this device.
9.1.3 Communication Settings

9.1.3.1 General Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  General Comm 9
Settings

0.0.0.0~
1 IP_LAN1 198.120.0.100 - - IP address of Ethernet port A
255.255.255.255
0.0.0.0~
2 Mask_LAN1 255.255.0.0 - - Subnet mask of Ethernet port A
255.255.255.255
Disabled
3 En_LAN1 Enabled - - Put Ethernet port A into service
Enabled
4 IP_LAN2 0.0.0.0~ 198.121.0.100 - - IP address of Ethernet port B

Date: 2021-04-20
9 Settings

255.255.255.255
0.0.0.0~
5 Mask_LAN2 255.255.0.0 - - Subnet mask of Ethernet port B
255.255.255.255
Disabled
6 En_LAN2 Enabled - - Put Ethernet port B into service
Enabled
0.0.0.0~
7 IP_LAN3 198.122.0.100 - - IP address of Ethernet port C
255.255.255.255
0.0.0.0~
8 Mask_LAN3 255.255.0.0 - - Subnet mask of Ethernet port C
255.255.255.255
Disabled
9 En_LAN3 Disabled - - Put Ethernet port C into service
Enabled
0.0.0.0~
10 IP_LAN4 198.123.0.100 - - IP address of Ethernet port D
255.255.255.255
0.0.0.0~
11 Mask_LAN4 255.255.0.0 - - Subnet mask of Ethernet port D
255.255.255.255
Disabled
12 En_LAN4 Disabled - - Put Ethernet port D into service
Enabled
0.0.0.0~ IP address of the gateway
13 Gateway 0.0.0.0 - -
255.255.255.255 (router)
4800
9600
19200
14 Baud_Printer 19200 bps - Baud rate of printer port
38400
57600
115200
Disabled Enable/disable automatic
15 En_AutoPrint Disabled - -
Enabled printing function
Communication protocol of rear
RS-485 serial port 1.
IEC103
16 Protocol_RS485-1 IEC103 - - IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
9 Communication protocol of rear

RS-485 serial port 2.
IEC103
17 Protocol_RS485-2 IEC103 - - IEC103: IEC60870-5-103
Modbus
protocol
Modbus: Modbus protocol
4800
9600
19200 Baud rate of rear RS-485 serial
18 Baud_RS485-1 19200 bps -
38400 port 1.
57600
115200

Date: 2021-04-20
9 Settings

4800
9600
19200 Baud rate of rear RS-485 serial
19 Baud_RS485-2 19200 bps -
38400 port 2.
57600
115200
Communication address
between the device and the
20 Addr_RS485-1 1~254 100 - 1
SCADA or RTU via RS-485
serial port 1.
Communication address
between the device and the
21 Addr_RS485-2 1~254 100 - 1
SCADA or RTU via RS-485
serial port 2.
The setting is used to set IP
address of syslog server 01,
and the device can upload
audit log to syslog server. The
setting is invalid unless cyber
0.0.0.0~
22 IP_SyslogServer01 0.0.0.0 - - security is configured in the
255.255.255.255
device.
Syslog is a communication
protocol for message logging,
it is used for security auditing in
this device.
0.0.0.0~
255.255.255.255
device.
9
this device.
0.0.0.0~
24 IP_SyslogServer03 0.0.0.0 - - audit log to syslog server. The
255.255.255.255
security is configured in the
device.

Date: 2021-04-20
9 Settings

this device.
0.0.0.0~
255.255.255.255
device.
this device.
The setting is used to set the
26 Cfg_NetPorts_Bond 0~255 0 - - Ethernet ports that are used as
hot standby each other.
A whitelist is a list of IP
addresses that are granted
access to a certain system or
protocol. When a whitelist is
Disabled used, all IP addresses are
27 En_IP_Whitelist Disabled - -
Enabled denied access, except those
included in the whitelist.
This setting is used to
enable/disable the whitelist
function of this device.
No.** IP address of the whitelist.
0.0.0.0~ (**=01...16) This setting is
28 IP**_Whitelist 0.0.0.0 - -
255.255.255.255 effective only when the setting
[En_IP_Whitelist] is enabled.
9 Normal;
1-2:Normal,3-4:HSR;
The network method of the CPU
29 B01.Opt_NetMode 1-2:Normal,3-4:PRP; Normal - -
module located in slot No.1
1-2:Normal,3-4:RSTP;
1-2:PRP, 3-4:PRP
1. [Cfg_NetPorts_Bond]
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device supports a bond between any two
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable

Date: 2021-04-20
9 Settings
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking a CPU module with four Ethernet ports as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.
Ethernet port 1
Port 4 Port 3 Port 2 Port 1 Setting Port 4 Port 3 Port 2 Port 1 Setting
Binary Bonding Bonding Binary
Bit 3 Bit 2 Bit 1 Bit 0 Value Bit 3 Bit 2 Bit 1 Bit 0 Value
0 0 1 1 0011 3 1 0 0 1 1001 9
Ethernet port 2
0 1 0 1 0101 5 0 1 1 0 0110 6
Ethernet port 3
1 0 1 0 1010 10 1 1 0 0 1100 12
Ethernet port 4
CPU Module
The switching logic is as below.
 After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.
 When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.
 When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.
 When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal. 9
9.1.3.2 IEC61850 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC61850 Settings

It is used to set the change detection
threshold for suddenly sending
1 Pcnt_Deadband 0~100.00 1 % 0.01 measurement value to the SCADA via
the device's Ethernet port using IEC
61850 protocol

Date: 2021-04-20
9 Settings

Measurement values zero drift
2 Threshold_ZeroDrift 0.001~0.5 0.02 - 0.001
suppression threshold
If users need to support the quality
Disabled
3 En_Send_MMS_Qual_Chg Disabled - - change upload function, this parameter
Enabled
should be set as “Enabled”
It is used to select the network mode of
MMS network for the communication
with SCADA
IEC61850
4 Opt_DualNetMode_MMS IEC61850 - - IEC61850: Network mode with IEC
GB32890
61850 protocol.
GB32890: Network mode with GB32890
standard.
The identification of the IED in IEC
61850 protocol.
It cannot be an empty string and shall be
unique within an SCL file. IEDNAME
should be less than 20 characters
5 IEDNAME - TEMPLATE - -
comprising letters or digits or underline
( _ ), and it is case sensitive.
If this setting is modified, the IED name
in ".cid" file will be changed
simultaneously and vice versa.
Disabled The logic setting to enable/disable TCP
6 En_IEC62351_TCP_Port Disabled - -
Enabled port in IEC62351 protocol
Disabled The logic setting to enable/disable TCP
7 En_IEC61850_TCP_Port Enabled - -
Enabled port in IEC61850 protocol
9.1.3.3 DNP Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  DNP Settings

The logic setting to
Disabled
1 En_TCP1_DNP Disabled - - enable/disable the No.1
9 Enabled
network DNP client
The local address of the
2 Addr_Slave_TCP1_DNP 0~65519 2 - 1
No.1 network DNP client
The master address of the
3 Addr_Master_TCP1_DNP 0~65519 1 - 1
The IP address of the
0.0.0.0~
4 IP_Master_TCP1_DNP 0.0.0.0 - - master of the No.1 network
255.255.255.255
DNP client
The communication map of
5 Opt_Map_TCP1_DNP 0~4 0 - 1
the No.1 network DNP

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9 Settings

client
The timeout of the
6 t_AppLayer_TCP1_DNP 1~5 3 s 1 application layer of the
The heartbeat time interval
7 t_KeepAlive_TCP1_DNP 0~7200 120 s 1 of the No.1 network DNP
client
enable/disable the UR
Disabled
8 En_UR_TCP1_DNP Disabled - - (Unsolicited Response)
Enabled
message function of the
No.1 network DNP client.
When this setting is
enabled, the master station
must activate UR reporting
by enabling unsolicited
application function
(Function code: 20). After
activation, the No.1
Disabled network DNP client of this
9 En_MsgCtrlUR_TCP1_DNP Enabled - -
Enabled device begins to send
Class 1, 2, 3 events to the
master station
spontaneously.
disabled, this device sends
event data spontaneously
to the master station.
The online retransmission
number for sending the
10 Num_URRetry_TCP1_DNP 2~10 3 - 1
unsolicited message of the
The offline retransmission
interval for sending the
9
11 t_UROfflRetry_TCP1_DNP 1~5000 60 s 1
The default class level of
12 Class_BI_TCP1_DNP 0~3 1 - 1 the “Binary Input” of the
13 Class_AI_TCP1_DNP 0~3 2 - 1 the “Analog Input” of the
14 t_Select_TCP1_DNP 0~240 30 s 1 The selection timeout of

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9 Settings

the remote control and
remote adjustment of No.1
network DNP client
The time interval of the
time synchronization
15 t_TimeSynIntvl_TCP1_DNP 0~3600 180 s 1
function of the No.1
network DNP client
The “OBJ1” default
1-BISingleBit
16 Obj01DefltVar_TCP1_DNP 1-BISingleBit - - variation of the No.1
2-BIWithStatus
network DNP client
1-BIChWoutT 2- The “OBJ2” default
17 Obj02DefltVar_TCP1_DNP 2-BIChWithAbsTime BIChWithAb - - variation of the No.1
3-BIChWithRelTime sTime network DNP client
1-AI32Int
2-AI16Int 3- The “OBJ30” default
18 Obj30DefltVar_TCP1_DNP 3-AI32IntWoutF AI32IntWout - - variation of the No.1
4-AI16IntWoutF F network DNP client
5-AI32Flt
1-AI32IntEvWoutT 1- The “OBJ32” default
19 Obj32DefltVar_TCP1_DNP 2-AI16IntEvWoutT AI32IntEvWo - - variation of the No.1
5-AI32FltEvWoutT utT network DNP client
1-AO32Int The “OBJ40” default
20 Obj40DefltVar_TCP1_DNP 2-AO16Int 1-AO32Int - - variation of the No.1
3-AO32Flt network DNP client
Disabled
21 En_TCP2_DNP Disabled - 1 enable/disable the No.2
Enabled
network DNP client
0.0.0.0~
9 24 IP_Master_TCP2_DNP
255.255.255.255
0.0.0.0 - - master of the No.2 network
DNP client
25 Opt_Map_TCP2_DNP 0~4 0 - 1 the No.2 network DNP
client
The timeout of the
client

Date: 2021-04-20
9 Settings

Disabled
Enabled
Disabled network DNP client of this
Enabled device begins to send
master station
spontaneously.
33 Class_AI_TCP2_DNP 0~3 2 - 1
the “Analog Input” of the
9
The selection timeout of
34 t_Select_TCP2_DNP 0~240 30 s 1
network DNP client
network DNP client

Date: 2021-04-20
9 Settings

1-BISingleBit
2-BIWithStatus
network DNP client
1-AI32Int
5-AI32Flt
Disabled
Enabled
network DNP client
0.0.0.0~
255.255.255.255
DNP client
client
The timeout of the
9 No.3 network DNP client

client
Disabled
Enabled
Disabled When this setting is
Enabled enabled, the master station

Date: 2021-04-20
9 Settings

network DNP client of this
device begins to send
master station
spontaneously.
network DNP client
9
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
58 Obj30DefltVar_TCP3_DNP 1-AI32Int 3- - - The “OBJ30” default

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9 Settings

2-AI16Int AI32IntWout variation of the No.3
4-AI16IntWoutF
5-AI32Flt
Disabled
Enabled
network DNP client
0.0.0.0~
255.255.255.255
DNP client
client
The timeout of the
client
Disabled
Enabled
9 message function of the
Disabled
69 En_MsgCtrlUR_TCP4_DNP Enabled - - application function
Enabled
network DNP client of this
device begins to send

Date: 2021-04-20
9 Settings

master station
spontaneously.
network DNP client
network DNP client
1-BISingleBit
2-BIWithStatus
network DNP client
77 Obj02DefltVar_TCP4_DNP
1-BIChWoutT
2-BIChWithAbsTime
2-
BIChWithAb - -
The
variation
“OBJ2”
of the
default
No.4
9
1-AI32Int
5-AI32Flt

Date: 2021-04-20
9 Settings

9.1.3.4 IEC103 Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  IEC103 Settings

Current
The language of group caption of IEC103
Language;
protocol
Fixed Current
1 Opt_Caption_103 - - It is recommended to be set as “Fixed
Chinese; Language
Chinese” if the device communicate with
Fixed
SCADA in Chinese.
English
This setting is only used for IEC 103
protocol. If NR network IEC103 protocol is
used, the setting must be set as
Disabled “Enabled”.
2 En_Broadcast_LAN1 Disabled - -
Enabled Disabled: the device does not send UDP
messages through Ethernet port A;
Enabled: the device sends UDP
messages through Ethernet port A.
Disabled “Enabled”.
3 En_Broadcast_LAN2 Disabled - -
messages through Ethernet port B;
messages through Ethernet port B.
9 4 En_Broadcast_LAN3
Disabled
Disabled - -
“Enabled”.
messages through Ethernet port C;
messages through Ethernet port C.
Disabled
5 En_Broadcast_LAN4 Disabled - - used, the setting must be set as
Enabled
“Enabled”.
Disabled: the device does not send UDP

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9 Settings

messages through Ethernet port D;
messages through Ethernet port D.
This setting is used to set the data format
for sending waveform list using IEC
60870-5-103.
DisturbData;
6 Format_Wave_Sent File - - DisturbData: Send the waveform list in
File
ASDU23 mode;
File: Send the waveform list in ASDU222
mode.
It is used to set the change detection
threshold for suddenly sending
7 Pcnt_Deadband_Net 0~100.00 1.00 % 0.01 measurement value to the SCADA via the
device's Ethernet port using IEC 60870-5-
103
It is used to set the time period for sending
the measurement value to SCADA via the
8 Period_Measmt_Net 0~65535 30 s 1
device's Ethernet port using IEC 60870-5-
103 or IEC 61850.
The logic setting to enable/disable the
Disabled
9 En_IEC103_TCP&UDP_Port Disabled - - TCP port and the UDP port in IEC 60870-
Enabled
5-103 protocol
9.1.3.5 Modbus Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  Modbus Settings

Disabled
1 En_Modbus_TCP_Port Disabled - - enable/disable the TCP port
Enabled
in Modbus protocol
9.1.3.6 GOOSE Communication Settings
Access path: MainMenu  Settings  Global Settings  Comm Settings  GOOSE Settings
9
The GOOSE receiving mode.
DoubleFrameChk: double frame
DoubleFrameChk
1 Opt_RecvMode_GOOSE SingleFrameChk - - check mode;
SingleFrameChk
SingleFrameChk: single frame
check mode;
Disabled Logic setting to enable/disable
2 En_NetA_GOOSE Enabled - -
Enabled GOOSE net A
3 En_DualNet_GOOSE Disabled Disabled - - Logic setting to enable/disable

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9 Settings

Enabled GOOSE double-net mode
Logic setting to enable/disable
GOOSE complex-net mode.
GOOSE complex-net mode: for
Disabled
4 En_ComplexNet_GOOSE Disabled - - the GOOSE receiving, some
Enabled
control blocks adopt dual-net
receiving and other control blocks
adopt single-net receiving.
9.1.4 Disturbance Fault Recording Settings

Access path: MainMenu  Settings  Global Settings  DFR Settings

Waveform recorded duration before the trigger
1 RecDur_PreTrigDFR 0~1 0.1 s 0.001
element operating
Waveform recorded duration after the fault
2 RecDur_PostFault 0~10 5 s 0.001
happens
The maximum waveform recorded duration
3 MaxRecDur_PostTrigDFR 0~10 10 s 0.001
after the trigger element operating
9.1.5 Label Settings

Access path: MainMenu  Settings  Global Settings  Label Settings
No. Symbol Default Description
Label setting of GOOSE communication link ** (**=00~63) of

1 Bx.Name_**_GCommLink GOOSE_Link00
the module located in slot No.x.
These settings are used to definite the label of each GOOSE communication link. The label of each
GOOSE communication link will influence the displayed contents of all reports, settings and
metering that related with each GOOSE communication link.
9.1.6 Clock Synchronization Settings

Access path: MainMenu  Settings  Global Settings  ClockSyn Settings
9 No
Settings Range Default Unit Step Remark
.
Conventional Select the time
1 Opt_TimeSyn SAS NoTimeSyn - - synchronization mode of the
NoTimeSyn device.
The local time zone also
2 OffsetHour_UTC -12~12 8 - 1 refered to as the hour offset
hour from UTC .
The offset minute of local time
3 OffsetMinute_UTC 0~60 0 - 1
from UTC.

Date: 2021-04-20
9 Settings
No
.
The IP address of the server
0.0.0.0~ when SNTP time
4 IP_Server_SNTP 0.0.0.0 - -
255.255.255.255 synchronization mode is
selected
The IP address of the standby
IP_StandbyServer_S 0.0.0.0~ server when SNTP time
5 0.0.0.0 - -
NTP 255.255.255.255 synchronization mode is
selected
When the setting
[OptTimeSyn] is configured as
“Conventional”, if it is required
to receive the SNTP message
as the backup clock
synchronization source while
hardware-based clock is lost
(i.e.: IRIG-B, IEEE 1588 or
PPS), please configure the
setting [En_ConvModeSNTP]
as “Enabled”. In this condition,
Disabled
6 En_ConvModeSNTP Disabled - - the alarm signal
Enabled
“Alm_TimeSyn” will still be
issued, so as to indicate the
failure of the “Conventional”
clock synchronization.
If the SNTP backup clock
synchronization source is not
required for the
“Conventional” mode, please
configure the setting
[En_ConvModeSNTP] as
“Disabled”.
7 DST.En
Disabled
Disabled - -
The logic setting is used to
enable or disable Daylight
9
Enabled
Saving Time (DST)
It is used to set the minute
offset of DST, i.e. the
8 DST.OffsetMinute 0~255 60 - 1
difference between DST time
and local time
Jan, Feb, Mar,
DST.MonthInYear_St Apr, May, Jun, It is used to set the start month
9 Mar - -
art Jul, Aug, Sep, of DST.
Oct, Nov, Dec

Date: 2021-04-20
9 Settings
No
.
DST.WeekInMonth_S 1st, 2nd, 3nd, 4th, It is used to set the start week
10 1st - -
tart Last of DST.
Sunday, Monday,
Tuesday,
DST.DayInWeek_Star It is used to set the start day of
11 Wednesday, Sunday - -
t DST.
Thursday, Friday,
Saturday
It is used to set the start hour
12 DST.HourInDay_Start 0~23 3 - 1
of DST.
Jan, Feb, Mar,
DST.MonthInYear_En Apr, May, Jun, It is used to set the end month
13 Oct - -
d Jul, Aug, Sep, of DST.
Oct, Nov, Dec
DST.WeekInMonth_E 1st, 2nd, 3nd, 4th, It is used to set the end week
14 1st - -
nd Last of DST.
Sunday, Monday,
Tuesday,
It is used to set the end day of
15 DST.DayInWeek_End Wednesday, Sunday - -
DST.
Thursday, Friday,
Saturday
It is used to set the end hour of
16 DST.HourInDay_End 0~23 9 - 1
DST.
1. [Opt_TimeSyn]
There are three selections for clock synchronization of the device, each selection includes different
time clock synchronization signals shown in following table.
Item Description
IRIG-B (RS-485): IRIG-B via RS-485 differential level.
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B (Fiber): IRIG-B via optical-fibre interface.
Conventional
PPS (Fiber): Pulse per second (PPS) via optical-fibre interface.
9 IEEE1588 (Fiber): Clock message via IEEE1588.
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SNTP(BC): Broadcast SNTP mode via Ethernet network.
SAS
IEC103: Clock messages through IEC103 protocol.
MODBUS: Clock messages through MODBUS protocol.
If time synchronization function is not needed for the device, this option can be
NoTimeSyn
selected.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there

Date: 2021-04-20
9 Settings
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically with
the alarm signal [Alm_TimeSyn] being issued simultaneously.
2) When “NoTimeSyn” mode is selected, the device will not send time synchronization alarm
signal.
The clock message via IEC103 protocol is INVALID when the device
receives the IRIG-B signal through RC-485 port.
9.1.7 OutMap Settings
Access path: MainMenu  Settings  Global Settings  OutMap Settings
No. Name Range Unit Default Description

OutMapxxx 00000000~ Tripping logic setting of programmable trip
1 - 0
(xxx=001, 002…032) FFFFFFFF output map xxx
t_Dwell_xxx_OutMap The pulse width setting of programmable
2 0.000~0.500 s 0.060
(xxx=001, 002…032) trip output map xxx
9.1.8 Supervision Settings

Access path: MainMenu  Settings  Global Settings  Superv Settings

The voltage threshold for VT
1 VTS.U_Set 50 10~ 100 0.01 V
circuit supervision
The current upper limit setting
2 VTS.I_UpLmt 0.1 (0.1~20)In 0.01 A
for VT circuit supervision
The current lower limit setting
3 VTS.I_LowLmt 0.04 (0 ~ 20)In 0.01 A
for VT circuit supervision
Delay pickup setting for the
4 VTS.t_DPU 1.500 0.2~30 0.001 s
alarm of VT circuit supervision
Delay drop off setting for the
5 VTS.t_DDO 10.000 0.2~30 0.001 s
alarm of VT circuit supervision
6 VTS.En Enabled
Disabled;
Enabled
- -
Logic setting for alarm function
9
9.2 Protection Settings
9.2.1 Distance Protection Settings
Access path: MainMenu  Settings  Protection Settings  DistProt Settings

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9 Settings

1 21Lx.En_Hm2_Blk Enabled - -
Enabled harmonic blocking function of
distance protection
The second harmonic
coefficient setting, which is
2 21Lx.HMB.K_Hm2 0.1 ~ 1 0.2 - 0.001 ueds for the second harmonic
blocking function of distance
protection
comprehensive harmonic
Disabled;
3 21Lx.En_Hm_Restrain Disabled; - - component which is used to
Enabled
adaptively adjust the operating
boundary of the impedance
relay.
Phase angle of positive-
4 21Lx.phi1_Reach 60~85 75 ° 0.1 sequence impedance for zone
Forward
Direction option for zone x of
5 21Lx.DirMode Reverse Forward - -
distance protection
Forward&Reverse
The reactance setting of zone
6 21Lx.X_Set 0.5 ~ 600 5 Ω 0.001
The resistance setting of zone
7 21Lx.R_Set 0.5 ~ 300 5 Ω 0.001
The time delay setting of zone
8 21Lx.t_Op 0 ~ 100 0.1 s 0.001
Disabled;
9 21Lx.En Enabled - - enabling/disabling zone x of
Enabled
distance protection
9.2.2 Phase Overcurrent Protection Settings

9 Access path: MainMenu  Settings  Protection Settings  OC Settings

The low voltage
blocking setting of the
1 50/51P.VCE.Up 10~100 70 V 0.001 voltage control element
protection

Date: 2021-04-20
9 Settings

The percent setting of
the harmonic control
2 50/51P.HMB.K_Hm2 0.1~1 0.2 - 0.001
element of phase
releasing the harmonic
3 50/51P.HMB.I_Rls 2~150 20 A 0.001 control element of
phase overcurrent
protection
The current setting of
4 50/51Px.I_Set 0.05~200 15 A 0.001 stage x of phase
The operating time
5 50/51Px.t_Op 0 ~100 0.1 s 0.001
phase overcurrent
protection
The drop-out time
6 50/51Px.t_DropOut 0 ~100 0 s 0.001
phase overcurrent
protection
of stage x of phase
phase overcurrent
Disabled;
7 50/51Px.En_Volt_Blk Disabled - - protection is not
Enabled
controlled by the
Enabled: stage x of
phase overcurrent
by the voltage control
9
element

Date: 2021-04-20
9 Settings

harmonic control
element of stage x of
phase overcurrent
protection
phase overcurrent
Disabled;
8 50/51Px.En_Hm_Blk Disabled - - protection is not
Enabled
controlled by the
harmonic control
element
Enabled: stage x of
phase overcurrent
by the harmonic control
element
9 50/51Px.En Enabled - -
Enabled stage 1 of phase
Enabling stage x of
phase overcurrent
Trp; protection operate to
10 50/51Px.Opt_Trp/Alm Trp - -
Alm trip or alarm.
ANSIE;
ANSIV;
ANSIN;
ANSIM;
ANSIDefTime;
9
ANSILTE; The setting for selecting
ANSILTV; the inverse-time
ANSILT; operation characteristic
11 50/51Px.Opt_Curve IECDefTime - -
IECN; curve of stage x of
IECV; phase overcurrent
IEC; protection.
IECE;
IECST;
IECLT;
IECDefTime;
UserDefine

Date: 2021-04-20
9 Settings

The setting for selecting
the inverse-time drop-
out characteristic curve
of stage x of phase
Inst; overcurrent protection
12 50/51Px.Opt_Curve_DropOut DefTime; Inst - - Inst: instantaneous
IDMT drop-out
DefTime: definite-time
drop-out
IDMT: inverse-time
drop-out
The time multiplier
13 50/51Px.TMS 0.04~ 20 1 - 0.001
phase overcurrent
protection
The minimum operating
time setting of stage x
14 50/51Px.tmin 0 ~10 0.02 s 0.001
protection
The constant “k” of the
customized inverse-
time operation
15 50/51Px.K 0.001~120 0.14 - 0.0001
protection
The constant “α” of the
customized inverse-
time operation
16 50/51Px.Alpha 0.01 ~3 0.02 - 0.0001
protection
The constant “C” of the
customized
time
inverse-
operation
9
17 50/51Px.C 0 ~1 0 - 0.0001
protection
9.2.3 DPFC Overcurrent Protection Settings
Access path: MainMenu  Settings  Protection Settings  OCD Settings

Date: 2021-04-20
9 Settings

1 50/51D.En_Hm2_Blk Disabled - -
Enabled harmonic blocking function of DPFC
The second harmonic coefficient
setting, which is ueds for the second
2 50/51D.HMB.K_Hm2 0.1~1 0.2 - 0.001
harmonic blocking function of DPFC
Disabled; enabling/disabling the harmonic
3 50/51D.En_Hm_Restrain Disabled - -
Enabled suppression function of DPFC
The DPFC current setting of DPFC
4 50/51D.I_Set 0.05~200 15 A 0.001
The time delay setting of DPFC
5 50/51D.t_Op 0 ~ 100 0.1 s 0.001
Disabled;
6 50/51D.En Enabled - - enabling/disabling the DPFC
Enabled
9.2.4 Undervoltage Protection Settings
Access path: MainMenu  Settings  Protection Settings  UV Settings

The voltage setting of
1 27Px.U_Set 5~120 80 V 0.001 stage x of phase
The drop-out coefficient
2 27Px.K_DropOut 1~1.2 1.03 - 0.001 of stage x of phase
The operating time setting
3 27Px.t_Op 0.1 ~100 1 s 0.001 of stage x of phase
9 The drop-out time setting
4 27Px.t_DropOut 0 ~100 0 s 0.001 of stage x of phase
5 27Px.En Enabled - -
Enabled stage x of phase

Date: 2021-04-20
9 Settings

Enabling stage x of phase
Trp;
6 27Px.Opt_Trp/Alm Trp - - operate to trip or alarm.
Alm
9.2.5 Breaker Failure Protection Settings
Access path: MainMenu  Settings  Protection Settings  BFP Settings

The phase current setting of breaker
1 50BF.I_Set 0.05~200 1.000 A 0.001
failure protection
The re-trip time delay of breaker failure
2 50BF.t_ReTrp 0~20 0.050 s 0.001
protection
The first time delay of breaker failure
3 50BF.t1_Op 0~20 0.100 s 0.001
protection
The second time delay of breaker failure
4 50BF.t2_Op 0~20 0.200 s 0.001
protection
Disabled Enabling/disabling breaker failure
5 50BF.En Enabled - -
Enabled protection
Disabled Enabling/disabling re-trip function of
6 50BF.En_ReTrp Enabled - -
Disabled Enabling/disabling the first time delay of
Disabled Enabling/disabling the second time delay
Enabled of breaker failure protection
Enabling/disabling phase overcurrent
Disabled
9 50BF.En_Ip Disabled - - element of breaker failure protection via
Enabled
three-phases initiating signal
Enabling/disabling breaker failure
50BF.En_CB_Ctr Disabled
10 Disabled - - protection be initiated by normally closed
l Enabled
contact of circuit breaker
11
50BF.En_Alm_Ini
t
Disabled
Enabled
Disabled - -
Enabling/disabling abnormality check of
breaker failure initiating signal
9
9.2.6 Switch-on-to-Fault ProtectionSettings
Access path: MainMenu  Settings  Protection Settings  SOTF Settings

Date: 2021-04-20
9 Settings

Logic setting for selecting
the manual closing SOTF
ManClsBI
trigger mode:
1 SOTF.Opt_Mode_ManCls CBPos CBPos - -
circuit breaker position,
ManClsBI/CBPos
manual closing input, or
either.
The initiating time for the
2 SOTF.t_En 0.2~100 3 s 0.001
SOTF protection
3 50PSOTF.I_Set 0.05~200 1 A 0.001 overcurrent SOTF
protection
Time delay for phase
4 50PSOTF.t_Op 0~100 0.1 s 0.001 overcurrent SOTF
protection
Disabled
5 50PSOTF.En Enabled - - overcurrent SOTF
Enabled
protection
Enabling/disabling
Disabled second harmonic blocking
6 50PSOTF.En_Hm2_Blk Enabled - -
Enabled for phase overcurrent
SOTF protection
undervoltage supervision
Disabled
7 50PSOTF.En_Volt_Blk Enabled - - logic for phase
Enabled
overcurrent SOTF
protection
Time delay for distance
8 21SOTF.t_Op 0~100 0.1 s 0.001
SOTF protection
Disabled Enabling/disabling
9 21SOTFx.En Enabled - -
Enabled distance SOTF protection
Enabling/disabling
Disabled
10 21SOTFx.En_Hm2_Blk Disabled - - distance SOTF protection
Enabled
9 blocked by harmonic
Disabled
11 21LSOTFx.En_Hm_Restrain Disabled - - harmonic suppression
Enabled
function of distance SOTF
protection
9.2.7 Automatic Reclosure Settings

Access path: MainMenu  Settings  Protection Settings  AR Settings

Date: 2021-04-20
9 Settings
Uni
t
Maximum number of reclosing
1 79.Num 1~4 1 - 1
attempts
The live voltage check setting of
2 79.U_LvChk 10~100 70 V 0.001
reclosing
3 79.t_Dd_S1 0~600 0.600 s 0.001 Dead time of first shot reclosing
4 79.t_Dd_S2 0~600 0.600 s 0.001 Dead time of second shot reclosing
5 79.t_Dd_S3 0~600 0.600 s 0.001 Dead time of third shot reclosing
6 79.t_Dd_S4 0~600 0.600 s 0.001 Dead time of fourth shot reclosing
Time delay of circuit breaker in

7 79.t_CBClsd 0~600 5.000 s 0.001
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
signal [79.CB_Healthy] is de-
8 79.t_CBReady 0~600 5.000 s 0.001
energized and if it is not energized
within this time delay, AR will be
blocked.
Maximum wait time for
9 79.t_Wait_Chk 0~600 10.000 s 0.001
synchronism check
10 79.t_Reclaim 0~600 15.000 s 0.001 Reclaim time of AR
Drop-out time delay of blocking AR,

when blocking signal for AR
11 79.t_DDO_Blk 0~600 5.000 s 0.001
disappears, AR blocking condition
drops out after this time delay
Time delay of excessive trip signal
12 79.t_PersistTrp 0~600 0.200 s 0.001
to block AR
Time delay allow for CB status
13 79.t_Fail 0~600 0.200 s 0.001 change to conform reclosing
successful
14 79.t_PW 0~600 0.120 s 0.001 Pulse width of AR closing signal
15 79.En_FailCheck
Disabled
Disabled - -
Enabling/disabling confirm whether
AR is successful by checking CB
9
Enabled
state
Disabled Enabling/disabling adjust the
16 79.En_CutPulse Disabled - -
Enabled length of reclosing pulse
Disabled
17 79.En Enabled - - Enabling/disabling auto-reclosing
Enabled
Disabled Enabling/disabling AR be initiated
18 79.En_CBInit Disabled - -
Enabled by open state of circuit breaker

Date: 2021-04-20
9 Settings
9.2.8 Fault Location Settings
Access path: MainMenu  Settings  Protection Settings  Line Settings

Disabled The logic setting for enabling/disabling
1 FL.En Disabled - -
Enabled fault location function
The logic setting for enabling/disabling
Disabled the kilometer post display, if it is
2 FL.En_kmPost Disabled - -
Enabled enabled, the measurement result of
fault location shows the kilometer post.
3 FL.kmPost_Substation 0~9999 100 km 0.001 The kilometer post of the substation
The setting for selecting the kilometer
4 FL.Opt_Dir_kmPost 0~1 0 - 1
post direction.
The line length from the traction
5 FL.LineLength 0 ~ 100 10 km 0.001
substation to the feeder
6 FL.Num_Point 1 ~ 12 1 - 1 The segment point number
7 FL.X_01 0 ~ 600 5 Ω 0.001 The reactance value of the 1st point
8 FL.Location_01 0 ~ 100 10 km 0.001 The location of the 1st point
9 ……
10 FL.X_12 0 ~ 600 5 Ω 0.001 The reactance value of the 12th point
11 FL.Location_12 0 ~ 100 10 km 0.001 The location of the 12th point
9.2.9 ATS Settings
Access path: MainMenu  Settings  Protection Settings  ATS Settings

Disabled; The logic setting for enabling/disabling ATS
1 ATS.En Disabled - -
Enabled function
Time delay allow for CB status change to
2 ATS.t_Fail 0.200 0~600 0.001 s
conform closing successful
9.3 Measurement and Control Settings
9
In this section, the "XXXX" stands for bay indication. By default, it could be
BayMMXU, BusMMXU, etc. and it is configurable through the configuration
tool PCS-Studio.
9.3.1 Function Settings
Access path: Main Menu  Settings  Meas Control Settings  Function Settings

Date: 2021-04-20
9 Settings
No. Setting Default Range Step Unit Remark
1 ZeroDrift_U 0.20 0.00~1.00 0.01 %

Threshold to limit the zero-drift influence of voltage,
current or power due to temperature or other
2 ZeroDrift_I 0.20 0.00~1.00 0.01 % environmental factors. A measured value less than
this setting will be regarded as a zero drift and
ignored.
3 ZeroDrift_PQ 0.50 0.00~1.00 0.01 %
9.3.2 Double Point Status Settings
Access path: Main Menu  Settings  Meas Control Settings  DPS Settings

Date: 2021-04-20
9 Settings

Delay Pick Up (DPU) time, i.e. debounce
1 CB.DPS.t_DPU 500 0~60000 1 ms
time, for DPS of the circuit breaker
Disabled or Logic setting for DPS alarm of the circuit
2 CB.DPS.En_Alm Disabled - -
Enabled breaker
Operation time delay of DPS alarm of
3 CB.DPS.t_Alm 500 0~60000 1 ms
the circuit breaker
4 DS01.DPS.t_DPU 500 0~60000 1 ms
time, for DPS of disconnector switch 01
Disabled or Logic setting for DPS alarm of
5 DS01.DPS.En_Alm Disabled - -
Enabled disconnector switch 01
6 DS01.DPS.t_Alm 500 0~60000 1 ms
disconnector switch 01
7 DS02.DPS.t_DPU 500 0~60000 1 ms
9 DS02.DPS.t_Alm 500 0~60000 1 ms
10 DS03.DPS.t_DPU 500 0~60000 1 ms
12 DS03.DPS.t_Alm 500 0~60000 1 ms
13 DS04.DPS.t_DPU 500 0~60000 1 ms
15 DS04.DPS.t_Alm 500 0~60000 1 ms
16 DS05.DPS.t_DPU 500 0~60000 1 ms
9 17 DS05.DPS.En_Alm Disabled
Disabled or
- -
Logic setting for DPS alarm of
18 DS05.DPS.t_Alm 500 0~60000 1 ms
19 DS06.DPS.t_DPU 500 0~60000 1 ms
21 DS06.DPS.t_Alm 500 0~60000 1 ms

Date: 2021-04-20
9 Settings

22 DS07.DPS.t_DPU 500 0~60000 1 ms
24 DS07.DPS.t_Alm 500 0~60000 1 ms
25 DS08.DPS.t_DPU 500 0~60000 1 ms
27 DS08.DPS.t_Alm 500 0~60000 1 ms
28 DS09.DPS.t_DPU 500 0~60000 1 ms
30 DS09.DPS.t_Alm 500 0~60000 1 ms
9.3.3 Control Settings
Access path: Main Menu  Settings  Meas Control Settings  Control Settings

Pulse Width (PW), i.e. holding time, for opening
1 CB.t_PW_Opn 500 0~60000 1 ms
output of the circuit breaker
Pulse Width (PW), i.e. holding time, for closing
2 CB.t_PW_Cls 500 0~60000 1 ms
output of the circuit breaker
Pulse Width (PW), i.e. holding time, for direct
3 DS01.t_PW_Opn 500 0~60000 1 ms
opening output of disconnector switch 01
4 DS01.t_PW_Cls 500 0~60000 1 ms
closing output of disconnector switch 01
5 DS02.t_PW_Opn 500 0~60000 1 ms
6 DS02.t_PW_Cls 500 0~60000 1 ms

9
7 DS03.t_PW_Opn 500 0~60000 1 ms
8 DS03.t_PW_Cls 500 0~60000 1 ms
9 DS04.t_PW_Opn 500 0~60000 1 ms
10 DS04.t_PW_Cls 500 0~60000 1 ms
11 DS05.t_PW_Opn 500 0~60000 1 ms Pulse Width (PW), i.e. holding time, for direct

Date: 2021-04-20
9 Settings

12 DS05.t_PW_Cls 500 0~60000 1 ms
13 DS06.t_PW_Opn 500 0~60000 1 ms
14 DS06.t_PW_Cls 500 0~60000 1 ms
15 DS07.t_PW_Opn 500 0~60000 1 ms
16 DS07.t_PW_Cls 500 0~60000 1 ms
17 DS08.t_PW_Opn 500 0~60000 1 ms
18 DS08.t_PW_Cls 500 0~60000 1 ms
19 DS09.t_PW_Opn 500 0~60000 1 ms
20 DS09.t_PW_Cls 500 0~60000 1 ms
9.3.4 Interlocking Logic Settings
Access path: Main Menu  Settings  Meas Control Settings  Interlock Settings

Disabled or
1 CB.En_CILO_Opn Disabled - - control of opening output of the circuit
Enabled
breaker.
Disabled or
2 CB.En_CILO_Cls Disabled - - control of closing output of the circuit
Enabled
breaker.
Disabled or
3 DS01.En_CILO_Opn Disabled - - control of direct opening output of
Enabled
9 disconnector switch 01.

Disabled or
4 DS01.En_CILO_Cls Disabled - - control of direct closing output of
Enabled
disconnector switch 01.
Disabled or
Enabled
Disabled or
Enabled
7 DS03.En_CILO_Opn Disabled Disabled or - - Logic setting for interlocking logic

Date: 2021-04-20
9 Settings

Enabled control of direct opening output of
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
Disabled or
Enabled
18 DS08.En_CILO_Cls Disabled
Disabled or
- -
control of direct closing output of
9
Enabled
Disabled or
Enabled
Disabled or
Enabled

Date: 2021-04-20
9 Settings
9.4 Logic Links
Logic link is a special logic setting which can be configured through local HMI or remote PC.
These logic links provide a convenient way for the operator to put the function in service or out of
service remotely away from an unattended substation.
9.4.1 Function Links

Access path: MainMenu  Settings  Logic Links  Function Links
No. Settings Range Default Remark
1 Link_** Disabled; Enabled Enabled Function link setting ** (**=01~08)
9.4.2 GOOSE Sending Links

Access path: MainMenu  Settings  Logic Links  GOOSE Send Links
@Bx.Name_**_GCommLink.G Disabled GOOSE sending link ** is enabled or disabled

1 Enabled
Link_Send Enabled (**=00~63)
@Bx.Name_**_GCommLink is the set value of the label setting of [Bx.Name_**_GCommLink].
9.4.3 GOOSE Receiving Links

Access path: MainMenu  Settings  Logic Links  GOOSE Recv Links
@Bx.Name_**_GCommLink.G Disabled GOOSE receiving link ** is enabled or disabled

1 Enabled
Link_Recv Enabled (**=00~63)
Enabling/disabling the allowance for the acceptance

of GOOSE messages
Disabled Disabled: not receiving the GOOSE message
2 GLink_RecvSim Disabled
Enabled (simulation=1)
Enabled: receiving the GOOSE message
(simulation=1)
9 @Bx.Name_**_GCommLink is the set value of the label setting of [Bx.Name_**_GCommLink].

Date: 2021-04-20
Appendix A Glossary
Appendix A Glossary
The abbreviations adopted in this manual are listed as below.
A BOM Binary Output Module
"a" Contact is breaker auxiliary contact (ANSI C

Standard Device Number 52A) that closes
when the breaker is closed and opens when C37.94 IEEE/ANSI protocol used when
the breaker is open. sending binary signals between IEDs
AC Alternating current CB Circuit breaker
A/D converter Analog-to-digital converter CID Configured IED Description
AI Analog input COMTRADE Standard Common Format for

Transient Data Exchange format for
ANSI American National Standards Institute
Disturbance recorder according to IEEE/ANSI
AR Autoreclosing C37.111, 1999 / IEC 60255-24
ASDU Application Service Data Unit – An CPU Central Processing Unit

ASDU can consist of one or more identical
CRC Cyclic Redundancy Check
information objects. A sequence of the same
information elements, for example measured CT Current Transformer
values, is identified by the address of the
CTS Current Circuit Supervision
information object. The address of the
information object defines the associated
D
address of the first information element of the
sequence. A consecutive number identifies the
DBDL Dead Bus Dead Line
subsequent information elements. The number
builds on this address in integral increments DBLL Dead Bus Live Line
(+1).
DC Direct Current
B DLLB Dead Line Live Bus
DNP Distributed Network Protocol as per IEEE

"b" Contact is breaker auxiliary contact (ANSI
Std 1815-2012
Standard Device Number 52B) that closes
when the breaker is open and opens when the DPFC Deviation of Power Frequency
breaker is closed. Component–In case of a fault occurred in the
power system, the fault component could be
BFP Breaker failure protection
analyzed into three parts: the power frequency
BI Binary Input components before the fault, the power
A
frequency variables during the fault and the
BO Binary Output
transient variables during the fault. DPFC is the
BIM Binary Input Module power frequency variable during the fault.
PCS-9611S Feeder Relay 1

Date: 2021-04-20
Appendix A Glossary
DSP Digital Signal Processor LCD Liquid Crystal Display
LED Light-emitting Diode

E
M
EHV Extra High Voltage
EMC Electromagnetic Compatibility MCB Miniature Circuit Breaker
MMS Manufacturing Message Specification

F
MOV Metal-oxide Varistor
FL Fault Location
P
FR Fault Recorder
PD Pole Discrepancy
G
PL Programmable Logic
G.703 Electrical and functional description for
PPS Pulse Per Second
digital lines used by local telephone companies.
Can be transported over balanced and PRP Parallel Redundancy Protocol
unbalanced lines
R
GIS Gas-insulated Switchgear
GOOSE Generic Object-Oriented Substation RMS Root Mean Square

Event
RSTP Rapid Spanning Tree Protocol
GPS Global Positioning System
RTD Resistance Temperature Detector
H RTU Remote Terminal Unit
HMI Human-machine Interface S

HSR High-availability Seamless Redundancy
SA Substation Automation
HV High-voltage
SCADA Supervision, Control And Data
HVDC High-voltage Direct Current Acquisition
SCD Substation Configuration Description

I
SCL Substation Configuration Description
ICD IED Capability Description Language
IEC International Electrotechnical Commission SLD Single-line Diagram
IED Intelligent Electronic Device SIR Source-to-line Impedance Ratio
IRIG-B InterRange Instrumentation Group SNMP Simple Network Management

A Time code format B Protocol–An Internet standard protocol and
serves for the administration of nodes in an IP
L network.
2 PCS-9611S Feeder Relay

Date: 2021-04-20
Appendix A Glossary
SNTP Simple Network Time Protocol – A T

protocol for the synchronization of clocks via
the Internet. With SNTP, client computers can TCS Trip Circuit Supervision
synchronize their clocks via the Internet with a
TCP/IP Transmission Control Protocol over
time server.
Internet Protocol
SOE Sequence of Events–An ordered, time-
stamped log of status changes at binary inputs U
(also referred to as state inputs). SOE is used
to restore or analyze the performance, or an UTC Coordinated Universal Time
electrical power system itself, over a certain
period of time. V
SOTF Switch-Onto-Fault
VT Voltage transformer
STP Rapid Spanning Tree Protocol
VTS Voltage Circuit Supervision
A list of function numbers used to represent electrical protection and control element. The device
function numbers used in this manual include the following:
21 Distance element 51 Definite-time or inverse-time overcurrent

element
25 Synchronism-check element
52 AC circuit breaker
27 Undervoltage element
79 Reclosing element
50 Instantaneous overcurrent element
These numbers are frequently used within a suffix letter to further designate their application. The
suffix letters used in this instruction manual include the following:
P Phase element D DPFC element
PCS-9611S Feeder Relay 3

Date: 2021-04-20

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About This Manual

Indicates an imminently hazardous situation that, if not avoided, will

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, could

result in death or serious injury.

Indicates a potentially hazardous situation that, if not avoided, may result

in minor or moderate injury or equipment damage.

Important information about the device, product handling or a certain

Instructions and Warnings

Disconnect or de-energize all external connections BEFORE opening this

PCS-9611S Feeder Relay I

cause electrical shock resulting in injury or death.

This device is shipped with default passwords. Default passwords should

DO NOT look into the fiber (laser) ports/connectors.

DO NOT perform any procedures or adjustments that this instruction

During installation, maintenance, or testing of the optical ports, ONLY use

II PCS-9611S Feeder Relay

Incorporated components, such as LEDs, transceivers, and laser emitters,

Equipment components are SENSITIVE to electrostatic discharge (ESD).

Insufficiently rated insulation can deteriorate under abnormal operating

SEVERE power and ground problems can occur on the communications

Use of controls or adjustments, or performance of procedures other than

The firmware may be upgraded to add new features or enhance/modify

PCS-9611S Feeder Relay III

Glossary also contains definitions of important terms.

 Menu path is connected with the arrow "→" and bold.

For example: the access path of protection settings is: MainMenu→Settings→Protection

 Settings not in the table should be placed in brackets.

For example: the system setting [Opt_SysFreq]

 Cross-references are presented in italics.

For example: press the button "ENT".

& & &

>=1 >=1 >=1

 Binary signal Input

IV PCS-9611S Feeder Relay

Optional definite-time or inverse-time characteristics

Fixed delay pickup (10ms), fixed delay drop-out (2ms)

Settable delay pickup, fixed delay drop-out

Fixed delay pickup, settable delay drop-out

Settable delay pickup, settable delay drop-out

PCS-9611S Feeder Relay V

VI PCS-9611S Feeder Relay

PCS-9611S Feeder Relay VII

Document Revision History

Current version: R1.00

Version Date Description of change

R1.00 R1.00 2021-04-20  Form the original manual.

VIII PCS-9611S Feeder Relay

1.1 Functions ......................................................................................................... 1-1

Figure 0-1 Functional diagram of PCS-9611S .......................................................................... 1-1

PCS-9611S Feeder Relay 1-a

1-b PCS-9611S Feeder Relay

The function diagram of this relay is shown in Figure 0-1.

27 21L 50/51P SOTF FL 83ATS AR

50BF 50/51D VTS FR

Figure 0-1 Functional diagram of PCS-9611S