PAMANTASAN NG CABUYAO

COLLEGE OF COMPUTING AND ENGINEERING

COURSE CODE: CPP 110

COURSE DESCRIPTION: INTRODUCTION TO HDL

COURSE INTENDED On the completion of the course, student is expected to be able to do the
LEARNING OUTCOMES: following:

1. The ability to code and simulate any digital function in HDL.

2. Understand library modeling, behavioral code and the differences
between them.
3. Understand the differences between simulator algorithms as well
as Logic verification using HDL software tool
4. Learn good coding techniques per current industrial practices

LEARNING MATERIAL FOR 3

WEEK NUMBER:

I. TITLE: Gate Level Modelling

II. OBJECTIVES: By the end of this module you should be able to:

1. Predict the output of a gate level Verilog model given its inputs
2. Describe how to correct a gate level Verilog model given its source
code, inputs and output
3. Write a Verilog gate-level model corresponding to a given simple
schematic
III. INTRODUCTION:
The purpose of this module is to introduce what Gate Level Modelling is.
Each Verilog model is of a particular "level." The level of a model
depends on statements and constructs it contains.
.

IV. CONTENTS:

Lesson Coverage:

- Gate Level Modelling

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GATE LEVEL MODELLING

Different Levels of Abstraction

Architectural / Algorithmic Level

Implement a design algorithm in high-level language constructs.

Register Transfer Level

Describes the flow of data between registers and how a design processes these data.

Gate Level

Describe the logic gates and the interconnections between them.

Switch (Transistor) Level

Describe the transistors and the interconnections between them.

The gate-level modeling describes the available built-in primitive gates and how these can be used to describe
hardware.

Multiple – Input Gates

(and, nand, or, nor. xor, xnor ) These logic gates have only one output and one or more inputs.

Syntax: multiple_input_gate_type[instance_name]
(OutputA,Input1,Input2,….,Input1);

Note: A value z at an input is handled like an x and the output can never be a z.

Multiple – Output Gates

(buf, not ) These gates have only one input and one or more outputs.

Syntax: multiple_output_gate_type[instance_name]
(Out1,Out2,…..,OutN, InputA);

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COLLEGE OF COMPUTING AND ENGINEERING

Tristate Gates

bufif0 , bufif1, notif0, notif1

These gates model three state drivers and have one output, one data input and one control input.

Note:
For a bufif0 gate, the output is z if control is 1, else data is transferred to output.
For a bufif1 gate, the output is z if control is 0.
For a notif0 gate, the output is z if control is 1, else output is the invert of the input data value.
For a notif1 gate, the output is z if control is 0.

Pull Gates

pullup , pulldown

These gates have only one output with no inputs.

Note:
A pullup gate places a 1 on its output.
A pulldown gate places a 0 on its output.

Syntax:

pull_gate_type[instance_name](OutA);

Examples:
Pullup PUP(Pwr) ;

MOS Switches

cmos, pmos, nmos, rcmos, rpmos, rnmos

These gates model unidirectional switches, that is, data flows from input to output and the data flow can be
turned off by appropriately setting the control input(s).

Note:

• The pmos( p-type MOS transistor), nmos(n-type MOS transistor), rnmos( r stands for resistive) and
rpmos switches have one output, one input, and one control input.

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• If control is 0 for nmos and rnmos switches and 1 for pmos and rpmos switches, the switch is turned off,
that is, output has a value z; if control is 1, data at input passes to output.

Syntax:
gate_type[instance_name](OutputA, InputB, ControlC);

Bidirectional switches

tran, rtran, tranif0, rtranif0, tranif1, rtranif1

These switches are bidirectional, that is, data flows both ways and there is no delay when data propagates
through the switches. The last four switches can be turned off by setting a control signal appropriately. The tran
and rtran switches cannot be turned off. If control is 1 for tranif0 and rtranif0, and 0 for tranif1 and rtranif1, the
bidirectional data flow is disabled.

Syntax : gate_type[instance_name](SignalA, SignalB, SignalC);

Gate Delays

The signal propagation delay from any gate input to the gate output can be specified using a gate delay using the
syntax:

gate_type [delay] [ instance_name] ( terminal list );

Example: and #3 g (a, b, c);

With the above statement the positive (0 to 1) transition at the output has a delay of 2 time steps while the
negative (1 to 0) transition has a delay of 1 time step

When no gate delay is specified, the default delay is zero . A gate delay can be comprised of up to three
values:

• Rise delay
• Fall delay
• Turn-off delay

Example

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1 bit multiplexer

sel in1 in2 out

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Gate Level Description

module mux2(out,in1,in2,sel);
output out;
input in1,in2,sel;

and a1(a1_o,in1,sel);
not n1(iv_sel,sel);
and a2(a2_o,in2,iv_sel);
or o1(out,a1_o,a2_o);
endmodule

Modelling Gate Level

Steps

• Develop the Boolean function of output

• Draw the circuit with logic gates/primitives
• Connect gates/primitives with net (usually wire)

HDL: Hardware Description Language

• Figure out architecture first, then write code.

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Test Methodology

Systematically verify the functionality of a model. Procedure of simulation:

• Detect syntax violations in source code

• Simulate behavior
• Monitor results

Stimulus

Hardware Design
Testbench
(Design Under Test)

Response

Example A B

Full Adder
Full
Co Ci
Adder

Truth Table

Ci A B Co S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

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Equation

Co = AB + BCi + CiA

Schematic Diagram module FA_co (co , a ,b ci);

A input a , b, ci;
out co;
B wire ab , bc,ca;
B
Co and g0 ( ab, a, b );
Ci and g1 ( bc, b, c );
and g2 ( ca, c, a );
Ci or g3 ( co, ab, bc, ca );
A
endmodule

Solution

Equation sum = a  b  ci

a module FA_sum ( sum, a, b, ci);

b
c sum input a, b, ci;
output sum, co;

xor g1 ( sum , a , b, ci );

endmodule

Full Adder Connection

full adder
Instance ins_c from FA_co
Instance ins_s from FA_sum carry out
a connection
b
module FA_gatelevel ( sum, a, b, ci); b
co
c
input a, b, ci; c
output sum, co; a

FA_co ins_c (co, a, b, ci ); sum

FA_sum ins_s (sum , a, b ,ci); connection
a
b sum
endmodule c

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 PAMANTASAN NG CABUYAO
COLLEGE OF COMPUTING AND ENGINEERING

Testbench

module TestBench;
reg a,b,ci;
wire sum,cout;

initial
begin
$display(“a b ci sum cout");
a = 1'b0; b = 1'b0;ci = 1'b0;
#8 $finish;
end

always #4 b = ~b;
always #2 a = ~a;
always #1 ci = ~ci;

FA_sum U1(sum,a,b,ci,cout);

initial
$monitor("%b %b %b %b %b“, a, b, ci, sum, cout);
endmodule

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 PAMANTASAN NG CABUYAO
COLLEGE OF COMPUTING AND ENGINEERING

V. REFERENCES: Roth, C.H. Jr. And John, L. K. (2018). Digital Systems Design Using VHDL (3rd
ed.). Texas, USA: Cengage Unlimited

Brown, S. and Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL

Design. (3rd ed.). New York, NY: McGraw-Hill

Online Readings and Guide

Hardware Description Language | VLSI Tutorial | Mepits

VHDL || Electronics Tutorial (electronics-tutorial.net)

Index of /ece232/pdf (umass.edu)

VI. ASSESSMENT TASK:

See Attached file given by the instructor

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