Technological University of the Philippines

Ayala Boulevard, Ermita, 0nila

College of Engineering
Electrical Engineering

EXPERIMENT 4

ACEE6L-M
Electronic Circuits: Devices and Analysis

Submitted By:
0naois, Ethan Zachary A.
BSEE2B

Date Submitted:
June 1, 2023

INSTRUCTOR:
Engr. Vil0 Pagtalunan
 EXPERIMENT NO. 9
JFET DC SOURCE

I. OBJECTIVE:

1. To determine the effect of drain to source voltage V DS an drain current ID.

2. To determine the effect of reverse gate to source bias voltage V GS and ID.

3. To determine and plot the JFET Transform curve.

4. To determine and plot the drain characteristic of a JFET.

II. DISCUSSION:

The field effect transistor (FET) is three terminal devices used for a variety of applications that
0tch, to a large extend. The pri0ry differences between two types of transistor is the fact BJT
transistors is a current controlled device while a JFET transistor is a voltage-controlled device as
shown in Fig 1.1.

ID

+
FET
= Fig.8.1
Voltage-Controlled
= Amplifiers

Controlled Voltage
(VGS)

For the JFET transistor the n-channel device will appear as prominent device. The basic
construction of the n-channel JFET is shown in Fig. 1.1.the type of the n-type channel is connected
through an ohmic contact to a terminal preferred to as the drain (d) while the lower end of the same
0terial is connected through an ohmic contact to a terminal preferred to as the source. (5) The two
P-type 0terials are connected together and to the gate. In essence, therefore, the drain and source
are connected to the ends of the n-type channel and gate to the two layers of p-type 0terials.
JFET DRAIN CHARACTERISTICS

The effect of drain-to-source voltage (VDS) on ID in an n-type, channel JFET 0ybe

determined experimentally by the current of Fig.1.2 V GG serves as the gate bias supply and VDD as
the drain-voltage source. the voltmeter M2 measures VDS. The milliammeter M1 measure ID as VDD
is varied.

S2
CV M1

S1
+ EVM VDD
CV M2

VGG

Fig. 1.2(a)

S2
M1

+ EVM M2
VDD

Fig. 1.2(b)

Fig. 1.3 Shoe the variation of ID with VDS for VGS=0, the condition when the gate is
effectively shorted to two sources. Fig 1.2 (b). As VDS is increased from 0V to VP, called pinch
off voltage, ID increases that can be attained without destroying the JFET, the value I drain current
re0ins relatively constant at the I. JFET is nor0lly operated on this interval VP to VDS 0x WHERE
NO change In ID occurs.
 Ic(mA)
(

9
IDSS

VF VDS(MAX)
Fig. 1.3 Drain characteristic of a JFET

Shorted to service another drain characteristic of a JFET when

gate is shorted to service another drain characteristic curve 0ybe
determines by reverse-biasing the gate. At some voltages, for this
condition ID will vary as shown in Fig 1.4. Other curve 0ybe determined
by setting Ic(mA) VGS at −1.0V, then at −1.5V, and so on. VGS = -2V
approxi0tely.

VGS=0.1V
IDSS
VGS=-0.5V
VGS=-1.0V
VGS=-1.5V
VGS=-2.0V

VDS
VP VPS(MA
X)
Fig. 1.4 Family of Drain Characteristics of
a JFET

TRANSFER CHARACTERISTIC
 Another curve, the transfer curve is useful in eval0ting the operating condition of a FET.
The curve is also plotted by using experimental circuit Fig. 1.6 (a) however, VDS is kept at some
constant value while VGS is varied, and ID is measured. The curve is

resembled in Fig 1.5 the transfer curve of Fig 1.5 is called a sq0re-law curve, because of sq0red
term in the eq0tion from which it is determined.

ID

=k
IDSS
VDS

VGS 0
-2 -1

Fig. 1.5 Transfer curve of JFET

III. 0TERIALS AND EQUIPMENT

Two Independent variable

Voltage dc source
EVM, 0-10 milliammeter
2n5484 (n-channel JFET) semiconductor
Two SPST switches

IV. PROCEDURES:

Gate shorted to source, VGS = 0, VDD = VDS

1. Connect the circuit of Fig. 1.6b. Power off.

2. Set the output of VDD at 0v. Switch power on and record data in table 1.9 the
drain current ID.
3. a) Increase the output of VDD =0.5V, measure and record ID corresponding to
VGS = 0V.
 b) Reset VDD to each value instead in the table, measure and record its VDD for
each value.
4. Open S1 power off.

Gate is reversed-biased

5. Modify the Fig. 1.6 to confirm than a fig. 1.6a switches open.
6. Set both output of VDD and VGG to 0V. Switches closed power turn on.
7. Adjust VGG so that VGS = -0.25V. Level 0intain for steps 8(a) and 8(b).
8. (a) Measure VDD for each value of VDS. Then measure and record ID in the table
1.9.
(b) Increase VDD for each value of VDS. Then measure and record ID in table
1.9.

S1
CV M1

+ EVM VDD
M2

VGG

Fig. 1.6
(a)

S1
M1

+ EVM M2
VDD
 Fig. 1.6
(b)
9. Reduce VDD =VDS = 0V, increase VGG and
VGS −0.8v 0intain this level for step 10.
10. Repeat step 8(a) and 8(b) for each value of VDD =VDS listed in table 1.9
11. Repeat step (9) and (10) for each value of VGS and VDS listed until drain,
Current cut-off is reached.
12. Power turn off

TRANSFER CHARACTERISTIC

13. Switches open. Set VDD =15V, VGG = -2.5V, VDD constant set 15V.
14. Power on. Close S1 and S2, measure and record ID for each VGS values
15. (a) On graphing paper, draw the drain characteristic using your data.
 V. DATA AND RESULTS

ID , 0

VGS, V

VDS 0 -0.25 -0.5 -0.75 -1.0 -1.25 -1.5 -1.75 -2.0 -2.5
,V

0 0 0 0 0 0 0 0 0 0 0

1.0 2.658 1.820 1.049 0.486 0.136 1.531 0.00 0 0.00 0 0.00 0 0.00 0
2.0 2.855 1.857 1.068 0.495 0.139 1.554 0.00 0 0.00 0 0.00 0 0.00 0
3.0 2.908 1.890 1.088 0.504 0.142 0.142 0.00 0 0.00 0 0.00 0 0.00 0
4.0 2.960 1.924 1.108 0.513 0.145 1.776 0.00 0 0.00 0 0.00 0 0.00 0
5.0 3.012 1.958 1.128 0.522 0.147 1.776 0.00 0 0.00 0 0.00 0 0.00 0
6.0 3.063 1.992 1.147 0.532 0.149 2.665 0.00 0 0.00 0 0.00 0 0.00 0
7.0 3.116 2.027 1.166 0.542 0.152 1.776 0.00 0 0.00 0 0.00 0 0.00 0

8.0 3.168 2.061 1.186 0.55 0.155 1.776 0.00 0 0.00 0 0.00 0 0.00 0
9.0 3.221 2.094 1.206 0.560 0.156 1.776 0.00 0 0.00 0 0.00 0 0.00 0
10.0 3.27 2.128 1.226 0.568 0.16 1.776 0.00 0 0.00 0 0.00 0 0.00 0
11.0 3.324 2.16 1.245 0.579 0.162 1.776 0.00 0 0.00 0 0.00 0 0.00 0
12.0 3.375 2.196 1.265 0.588 0.165 3.553 0.00 0 0.00 0 0.00 0 0.00 0
13.0 3.427 2.231 1.284 0.597 0.167 3.553 0.00 0 0.00 0 0.00 0 0.00 0
14.0 3.478 2.265 1.304 0.608 0.171 3.553 0.00 0 0.00 0 0.00 0 0.00 0
15.0 3.53 2.295 1.323 0.616 0.172 3.553 0.00 0 0.00 0 0.00 0 0.00 0
16.0 3.581 2.329 1.343 0.625 0.176 3.553 0.00 0 0.00 0 0.00 0 0.00 0
17.0 3.634 2.366 1.361 0.636 0.178 3.553 0.00 0 0.00 0 0.00 0 0.00 0
18.0 3.684 2.398 1.382 0.643 0.181 3.553 0.00 0 0.00 0 0.00 0 0.00 0

Table 1.9
 VDD = 0
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5
 VDD = 1V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5
 VDD = 2V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5
 VDD = 3V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5

VDD = 5V
VDD = 0
0 0.25
-0.5 -0.75

-1.0 -1.25

-1.5 -1.75
-2.0 -2.5

VDD = 5V
VDD = 0
0 0.25

-0.5 -0.75
-1.0 -1.25

-1.5 -1.75

-2.0 -2.5
 VDD = 6V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5

VDD = 7V
VDD = 0
0 0.25
-0.5 -0.75

-1.0 -1.25

-1.5 -1.75
-2.0 -2.5

VDD = 8V
VDD = 0
0 0.25

-0.5 -0.75
-1.0 -1.25

-1.5 -1.75

-2.0 -2.5
 VDD = 9V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25
-1.5 -1.75

-2.0 -2.5

VDD = 10V
VDD = 0
0 0.25
-0.5 -0.75

-1.0 -1.25

-1.5 -1.75

-2.0 -2.5
 VDD = 11V
VDD = 0
0 0.25

-0.5 -0.75

-1.0 -1.25

-1.5 -1.75
-2.0 -2.5
 VDD = 12V
VDD = 0
0V TO 0.75V

-1.0V to -1.75V
-2.0V to -2.5V

VDD = 13V
VDD = 0
0V TO 0.75V
-1.0V to -1.75V

-2.0V to -2.5V
 VDD = 14V
VDD = 0
0V TO 0.75V

-1.0V to -1.75V
-2.0V to -2.5V

VDD = 15V
VDD = 0
0V TO 0.75V
-1.0V to -1.75V

-2.0V to -2.5V
 VDD = 16V
VDD = 0
0V TO 0.75V

-1.0V to -1.75V
-2.0V to -2.5V

VDD = 17V
VDD = 0
0-0.75

-1.0 to -1.75
-2.0V to -2.5V
 VDD = 18V
VDD = 0
0V TO 0.75V

-1.0V to -1.75V
 -2.0V to -2.5V

GRAPHICAL REPRESENTATIONS
 VI. OBSERVATION:
Based on observation, the circuit includes a JFET transistor whose model is
2N5484, two voltmeters representing drain-source voltage and gate-source voltage, one
ammeter representing drain current, two variable sources indicating drain and gate voltage,
and one switch. The purpose here is to obtain the ID through observation by altering the
two sources that represent VGS and VDS in the given experiment. In Table 1.9, the ID in
VGS decreases and remains zero, whilst the ID in VDS increases. In a nutshell, they are
inversely proportional to one another. Because the current in ID in VGS is dropping, the
current will stop off and the voltage required to operate the transistor will increase. When
the power is turned off, the JFET behaves like an open circuit. The gate terminal must need
a doping opposite which the flow of electric charges through a JFET is regulated by
compressing the current-carrying channel.
VII. CONCLUSION
In conclusion, I learned how to calculate and depict the Junction Field Effect
Transistor by comparing the Drain-Source Voltage and Gate-Source Voltage. I also
comprehended the implications of drain-source voltage and gate-source voltage on the
drain current. The plot from the experiment shows that the curve between the drain-source
voltage and drain current is simply output characteristics, which are the same as the
collector characteristics in a Bipolar Junction Transistor. JFET can function by keeping the
VDS consistent and determining the ID for multiple values in VGS. By observing the
values of depleting current, the graph of gate-source voltage and drain current may be
generated in the drain characteristics.
The polarities of the gate-source and drain-source voltages are switched during
characterization. JGET's P channel functions similarly to an N channel, however, it
transports gaps rather than electrons.

VIII. GUIDE QUESTION:

1. Determine JFET for BJT.

The junction-field-effect transistor is made up of three parts. Terminals that
can be utilized as gate sources and drains controlled switches or amplifiers. Current
travels through a semiconducting terminal between the source and drain in a JFET.
Furthermore, the bipolar junction transistor differs from the JFET in that it is
a electrical device controlled by current, whereas junction-gate field-effect A
transistor is a type of electrical device that is controlled by voltage. JFET provides
superior thermal performance. BJT has greater stability.
2. Explain the procedure you would use to verify experimentally that there is
nom gate current in the range over which a JFET is nor0lly operated.
When reverse biased, no current flows and the voltage at VDS is zero.
Because the depletion region is too large, it is insufficient to drive those gates.
Because the transistor is reverse-biased, there is no gate current in the range.

3. From your graph, identify VP. (a) what helps you identify VP? Defined.
According to my graph, the pinch-of voltage is at 2V of the VDS, indicating
that the VDS is at ID has no voltage change at its maximum value. VP denotes the
straight-line after the current has reached saturation and the JFET has failed.

4. From your graph, identify IDSS (b) what helps you identify IDSS? Defined.
The drain saturation current at gate-source voltage is denoted by IDSS. It is
depicted in the graph as an increasing slope that becomes a straight line.
because it draws current.

5. Referring to your data, and your drain characteristic, compare the level of
ID for each value of VGS, what conclusion can you draw?
According to my observations, ID is dropping to VGS, where the Gate-
source voltage is negative, and the depletion area is located will increase because
it is inversely proportional to each other. Leakage current might also flow to the
source terminal.

6. Which is more effective on controlling ID, VDS or VGS? Explain, referring

to your data.
The experiment concluded that VGS is more successful in controlling ID as
the resistance or depletion region grows. In a reverse bias state, we can raise VDS
as the current decreases. It will depend on the value of VGS that you changed in
VDS.
7. What values of VGS cut off ID?
According to my graph, the value of Vgs that causes Id to equal zero is 1.5
V, and in multisim, 1.5 V of Vgs has a modest amount of current that is about
equal to zero.
8. Solve for the transfer characteristic 0the0tically, compare with your obtained
transfer characteristics. Which is more accurate to use? Why?

The output current IC and input regulating current IB of the BJT transistor
are related by beta, which was assumed to be constant for the analysis. I C and IB
have a straight-line relationship where you can get a twofold increase by doubling
the levels of I B and I C. Unfortunately, the output and input values of a JFET do
not have a linear connection. An equation defines the link between ID and VGS.
It's worth noting how carefully VGS and VP negative indicators are dealt with.
Without even a single hint, the The outcome would be completely inaccurate.