A New Ramp Stress Reliability Assessment on Pulse

Energy Based OTS Switching Operation

P. C. Chang, P. J. Liao, C. H. Wu, Y. C. Chang, D. H. Hou, E. Ambrosi, H. Y. Lee, J. H. Lee, and X. Y. Bao Taiwan
Semiconductor Manufacturing Company, Ltd., Hsinchu, Taiwan
E-mail: pcchango@tsmc.com
Abstract—With the increasing demand of Ovonic Threshold unit with selected voltage bias to keep constant energy ramp
Switching (OTS) endurance performance, reliability rate. Device failure is determined based on the failure criteria
acceleration model becomes imperative to speed up lifetime of off-state current (Ioff) beyond 10 µA under 0.5V DC
assessment. In this work, we develop a new ramp stress monitoring condition.
methodology to perform fast measurement with the proof of (a)
consistent lifetime and comparable distribution slope with
respect to conventional time-consuming endurance tests. We
have successfully proved material and polarity dependence of
2023 IEEE International Reliability Physics Symposium (IRPS) | 978-1-6654-5672-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/IRPS48203.2023.10118352

device endurance in GeCTe (GCT) based alloys thanks to this

new method. This has been proved to largely reduce reliability
evaluation time and provide a real time die-level reliability
acceleration model for endurance prediction.

Index Terms-- Selector, GeCTe, Endurance, Lifetime, Ramp

stress method, Time-saving reliability test, Polarity dependence
effect (b)

I. INTRODUCTION
In the development of high-density memory, Ovonic
Threshold Switching (OTS) Selector plays an important role
to replace transistor as selector device in the memory array
[1, 2]. However, many reliability issues from integration
process and physical mechanisms have not yet been studied,
owning to long time-consuming protocols required to Fig. 1. (a) TEM and schematic image of selector device. (b)
measure sample reliability behavior. Ramp voltage testing is Pulse sequences of endurance and ramp stress method. After
commonly used on transistor in logic technology with the first fire (FF), the stress powers in endurance are constant and
advantage of time saving and uniformity monitoring [3-5]. in ramp stress method are experimentally increasing,
Here, a new ramp-stress based acceleration method is followed by switching (SW) and Ioff measurements for the
investigated carefully from device relaxation and degradation monitoring of the device status.
upon endurance test on OTS material [6, 7]. The pulse energy
based ramping technique is demonstrated to get reliable A. Cycling degradation and relaxation effect in Endurance
endurance lifetime and acceleration slope. As demonstration,
the effect of material composition and other physical Switching characteristics of OTS selector are shown in
mechanisms on reliability performance can be quickly Fig. 2, in which the selector is woke-up by FF and followed
verified. In this way, we can greatly shorten the testing time by forming a conductive filament composed of internal
to accelerate the evolution of OTS development. defects to provide switchable function. In the filament model

II. EXPERIMENTAL
Figure 1a shows the schematic and TEM image of
GeCTe-based (GCT) chalcogenide selector device with
Tungsten used for both top and bottom electrodes, and one
load resistor connected in series with the OTS device. In this
study, the devices are programed with B1500A system for
lifetime testing. The procedures to collect the endurance
characteristics are illustrated in Fig. 1b, based on the
sequence of a First Fire (FF) pulse, followed by the cycling
pulses and switching monitoring (SW, triangular pulses with
rise/fall time =10 μs) periodically. On the other hand, the Fig. 2. Typical switching characteristics and schematic
ramp stress procedure is programmed by SMU measurement diagrams of selector model during First Fire and switch
operation.

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 (a)
(b)
Fig. 3. (a) Switching characteristics of selector device after
different numbers of cycling operation. Cycling failure
coincides with the loss of selector behavior as shown after
109 cycles. (b) Ioff as a function of cycling number under
pulse-energy of 0.3 to 1.9 mW. Abrupt Ioff increase is
observed after endurance failure with Ioff >10 μA.
(a)
(b)
(c)
(d)
Fig. 4. (a) After cycling, different delay time are interspersed
between 1st and 2nd switching (SW) monitor pulse. (b, c)
Switching characteristics of operated selector (after 10 and
108 cycling) in 1st (dash) and 2nd (solid) SW with 100 s delay
time. (d) VTH as a function of delay time after different
number of cycling operations.
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of OTS [6, 7], fast and slow defects exhibit different response
rate to applied voltage and dominate the switching behavior.
The endurance failure is associated to cycling degradation
behaviors. Fig. 3a-b shows the switching characteristics of
selector upon endurance cycling. Decreased VTH and
increased Ioff are observed after cycling with endurance
lifetime obeying to a pulse energy dependent power-law
relationship [7]. The root cause of endurance failure is
ascribed to the accumulation of slow defects under
continuous switching operations [8]. Endurance failure is
determined when selector loses switching capability together
with an Ioff higher than 10 μA. On the other hand, the
progress of slow defect localization from turn-off state to
fresh state is addressed as relaxation behavior [8, 9].
Relaxation effect is strongly correlated with selector filament
status [6]. Fig. 4 shows the evolution of switching
characteristics after 100 s of delay time and the monotonic
VTH recovery along relaxation time after 10 and 108 cycling.
It is significant to notice that the relaxation rate is slowed
down, and that VTH drift slope is reduced from 46 to 17
mV/dec at increasing endurance cycling operations. This
suggests that the filament change could be mitigated after
more defects cumulation, leading to an improved stability
with less localized defects in the enlarged filaments after high
endurance cycles number.
In Fig. 5a-b we report the results of the endurance test
performed with different delay times and pulse widths [7].
Result proves negligible recovery effect in Fig. 5a with
comparable lifetime performance as changing delay time in
experiment. Also, the change of pulse width in Fig. 5b is
(a)
(b)
(c)
Fig. 5. Lifetime as a function of (a) delay time and (b) pulse-
width during pulses cycling [7]. (c) Lifetime measured in AC
(1 MHz) and DC operation as a function of pulse energy in
power-law equation. The inset shows the Ioff increasing
during the stress applied.
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 helpful to understand frequency independent endurance
performance. Accordingly, DC constant stress instead of
endurance switching is implemented to assess OTS reliability
in Fig. 5c. Comparable endurance lifetime with consistent
current evolution upon stress is presented under DC and 1
MHz AC cycling operation.
B. Ramp stress method for OTS lifetime prediction
Ramp stress measurement is usually used to quickly
assess the reliability of HK lifetime [3-5]. The proposed ramp
stress method was shown in Fig. 6a to accelerate device
breakdown by increasing bias intensity in each stress period.
The pulse stress energy can be easily calculated from the bias
voltage, the pulse duration and current intensity applied in
each stress interval. In Fig. 6b, devices show the increased Ioff
(monitored under DC bias of 0.5 V) after stress and they lose
the switching capability when the failure criterion of Ioff
larger than 10 µA is reached. Hence, we could define the
critical pulse power PBD as device failure and collect the PBD
distribution for following characterization. Based on the
transitions of equivalent energy in different pulse power and
stress time, corresponding lifetime (teff) at each stress (Pi)
follows the relation ti ∙ Pin = teff ∙ Prefn [3-5] as shown in Fig. 6c,
where ti is the time interval at stress level, and n is the
acceleration factor in endurance power-law model. The
extraction of the equivalent device lifetime of a standard
endurance test for a power usage condition (Pref) can be
expressed as ∑i ∆ti ∙ (Pi/Pref)n by cumulating teff at each step
(a)
(c)
Fig. 6. (a) Test programs of endurance and ramp stress
method. By integral equivalent time, lifetime is calculated in
different stress operation. (b) The PBD distribution, which is
defined as the critical pulse power to device failure. (c)
Projected lifetime distributions in endurance and ramp stress
method (time cumulation from effective time during stress)
measurement.
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[3-5]. Resolution comparison of ramp stress methods with
conventional endurance was shown in Fig. 6c, which
demonstrates consistent lifetime and Weibull slope. As
demonstrated for different materials in Fig. 7, increased PBD
and projected lifetime can be applied to differentiate process
improvement by ramp stress method.
Converting the sum into an integral and performing the
lifetime leads to the transformation given by Pref /(RR ∙ (n+1))
∙ (PBD /Pref)n+1 [3-5], where RR is ramp rate (∆P/ti). Within
different RR operation, which is programed in different stress
time (ti) in Fig. 8a, the acceleration factor n could be
estimated without endurance results. Under the tunable ramp
power stress method in Fig. 8b-c, different degradation rates
are shown in various RR with controlled ti, and lower RR
makes breakdown happening earlier. From the relation
between RR and PBD, the acceleration behavior with respect
to RR can be derived from the power law model as
(PBD1)n+1/RR1 = (PBD2)n+1/RR2 [3-5], and a slope of n ~3.7 is
(b)
Fig. 7. Medium PBD and projected lifetime by ramp stress
method and endurance on different materials. The inset
shows the projected lifetime distributions at 0.1 mW with
extracted n from endurance.
(a) (b)
(d)
(c)
Fig. 8. (a) Controlling program of tunable ramp power stress
method (constant ramp rate, RR). (b, c) Increasing Ioff and
corresponding effective time in ramp power stress. (d) PBD as
function of RR shows a slope of n ~3.7.
3A.3-3
 extracted as reported in Fig. 8d. With n obtained from the (a) (b)
method, the projected lifetime and its power dependence are
benchmarked with endurance results and shown to be
comparable as reported in Fig. 9. According to these results,
the ramp stress method not only considers undistorted
measurement resolution, but also reduces the testing time to
improve the feasibility of wafer-level monitoring. For
application, it helps to speed up the development of the
material engineering and shows the potential to study other
influences on reliability.
Considering the polarity characteristics and operation of
the used memory, the possible different behavior of the
selector once submitted to positive or negative bias could be
an issue for reliability [10]. In Fig. 10a-b, the polarity (c)
independent Ioff - VTH characteristics are observed after
endurance stress cycling, which are supposed to feature the
same switching and cycling degradation mechanism.
However, negative bias displays severe degradation with a
reduction of 400 times of the expected lifetime, as shown in
Fig. 10c. It can be explained by the polarity dependency of
the effective stressed area owing to OTS mushroom device
structure. For the lifetime assessment by ramp stress method,
identical lifetime behavior and acceleration factor are shown
in Fig. 10c-d with endurance study. This supports aligned
reliability modeling to investigate physical property. On the
contrary, for a pulse energy close to the operating situation,
longer measurement times are required to evaluate the (d)
process improvement, as shown in Fig. 11. Although the DC
measurement in this paper can reduce the measurement time
by about half, it still takes huge time in the corresponding
experiments of high cycling. Thanks to our ramp stress
method, the lifetime prediction can be done in only one
minus of measurement, which greatly reduces the test time
and accelerates the development of OTS.
Fig. 10. (a, b) Switching characteristics and Ioff - VTH
correlation in positive and negative bias operations with
increasing numbers of cycles. (c) Lifetime as function of
pulse power obtained by standard endurance test and by ramp
stress measurement under polarity bias operation. Ramp
stress projections are assumed with n from the slope of PBD -
RR dependance in (d).

Fig. 9. Lifetime and its power dependence in endurance

measurement and ramp stress method (prediction with n from
tunable ramp power stress method in Fig. 8).

Fig. 11. Testing time of endurance performances by AC

cycling stress, DC constant stress, and Ramp stress
measurement.

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 I. CONCLUSIONS [9] D. Ielmini, S. Lavizzari, D. Sharma and A. L. Lacaitag,
“Physical interpretation, modeling and impact on phase
In this paper, by studying the degradation and recovery
behavior on OTS, negligible frequency effect reveals that change memory (PCM) reliability of resistance drift due
total cumulative equivalent time dominates endurance to chalcogenide structural relaxation, “IEEE
performance. Based on the results, DC and ramp stress International Electron Devices Meeting (IEDM), 2007.
method are proposed to evaluate the device lifetime. In our [10] T. Ravsher, R. Degraeve, D. Garbin, A. Fantini, S.
demonstration, ramp stress not only shows the capability for Clima, G. L. Donadio, S. Kundu, H. Hody, W. Devulder,
lifetime forecast within undistorted resolution on different J. V. Houdt, V. Afanas’ev, R. Delhougne, and G. S.
material compositions and geometric structure effect, but also Kar,” Polarity-dependent threshold voltage shift in
saves lot of time for measurement and assessment. The
ovonic threshold switches: Challenges and
proposed method helps the feasibility of wafer-level
opportunities,” IEEE International Electron Devices
monitoring and speeds up the development of high-density
memory. Meeting (IEDM), 2021.

REFERENCES
[1] R. Aluguri and T. Y. Tseng, “Notice of Violation of
IEEE Publication Principles: Overview of Selector
Devices for 3-D Stackable Cross Point RRAM Arrays,”
IEEE Journal of the Electron Devices Society, 4, pp.
294-306, 2016.
[2] S. Kim, X. Liu, J. Park, S. Jung, W. Lee, J. Woo, J. Shin,
G. Choi, C. Cho, S. Park, D. Lee, E. J. Cha, B. H. Lee,
H. D. Lee, S. G. Kim, S. Chung, and H. Hwang,
“Ultrathin (<10nm) Nb2O5/NbO2 Hybrid Memory with
Both Memory and Selector Characteristics for High
Density 3D Vertically Stackable RRAM Applications,
“Symposium on VLSI Technology, 2012.
[3] JEDEC standard, “Procedure for Characterizing Time
Dependent Dielectric Breakdown of Ultra-Thin Gate
Dielectrics,” JESD92.
[4] JEDEC standard, “Procedure for Wafer-Level Testing
of Thin Dielectrics,” JESD35A
[5] JEDEC standard, “Procedure for the Evaluation of Low-
k/Metal Inter/Intra-Level Dielectric Integrity,” JEP159A
[6] F. Hatem, Z. Chai, W. Zhang, A. Fantini, R. Degraeve,
S. Clima, D. Garbin, J. Robertson, Y. Guo, J. F. Zhang,
J. Marsland, P. Freitas, L. Goux, and G. S. Kar,
“Endurance improvement of more than five orders in
GexSe1-x OTS selectors by using a novel refreshing
program scheme, “IEEE International Electron Devices
Meeting (IEDM), 2019.
[7] P. C. Chang, P. J. Liao, D. W. Heh, C. Lee, D. H. Hou,
E. Ambrosi, C. H. Wu, H. Y. Lee, J. H. Lee, and X. Y.
Bao, “Investigation of First Fire Effect on VTH Stability
and Endurance in GeCTe Selector, “IEEE International
Reliability Physics Symposium (IRPS), 2022.
[8] R. Degraeve, T. Ravsher, S. Kabuyanagi, A. Fantini, S.
Clima, D. Garbin, and G. S. Kar, “Modeling and
spectroscopy of ovonic threshold switching defects,
“IEEE International Reliability Physics Symposium
(IRPS), 2021.

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