Verilog code of D-Flipflop reset:

module reset1(
input d,
input z,
input clk,
input reset1,
output reg q_async_lowrst,
output reg q_sync_lowrst,
output reg q_async_highrst,
output reg q_sync_highrst);
always @(posedge z or negedge reset1)
begin
if(!reset1) q_async_lowrst <= 1'b0;
else q_async_lowrst <= d;
end
always @(posedge z)
begin
if(!reset1) q_sync_lowrst <= 1'b0;
else q_sync_lowrst <= d;
end
always @(posedge z or posedge reset1)
begin
if(reset1) q_async_highrst <= 1'b0;
else q_async_highrst <= d;
end
always @(posedge z)
begin
if(reset1) q_sync_highrst <= 1'b0;
else q_sync_highrst <= d;
end
endmodule

Testbench:
module reset_tb1();
reg d;
reg clock;
reg reset1;
reg a;
wire z;
wire Q_async_lowrst;
wire Q_sync_lowrst;
wire Q_async_highrst;
wire Q_sync_highrst;
assign z= clock & a;
reset1 dut(.d(d), .z(z), .clk(clock), .reset1 (reset1), .q_async_lowrst(Q_async_lowrst),
.q_sync_lowrst(Q_sync_lowrst), .q_async_highrst(Q_async_highrst),
.q_sync_highrst(Q_sync_highrst));

initial begin
clock=0;
#1 clock=1;
forever #5 clock = ~clock;
end
initial begin
a=1;
#320 a=0;
#200 a=1;end

initial begin
d = 1; reset1 =1;
#53 reset1 =0;
#161 reset1 =1;

#90 reset1 = 0;
#90 reset1 = 1;
#50 reset1 = 0;
#160 reset1 = 1;
#160 reset1 = 0;
#60 $finish;
end
endmodule

Output:

Verilog code for counter:

module counter(
input clk,
input rst,
output reg [2:0]out_mod5,
output reg [2:0]out_3bit,
output reg [3:0] out_4biteven,
output reg [3:0] out_4bitodd,
output reg [3:0] out_4bit_evenodd);
always @(posedge clk or negedge rst) //Mod5 counter
begin
if (!rst)
out_mod5 <= 3'b0 ;
else if (out_mod5 == 3'b100)
out_mod5 <= 0;
else
out_mod5 <= out_mod5 + 1;
end

always @(posedge clk or negedge rst) //0-7 counter

begin
if(!rst)
out_3bit <= 3'b0;
else
out_3bit <= out_3bit + 1;
end

always @(posedge clk or negedge rst) //4bit even counter

begin
if(!rst)
out_4biteven <= 4'b0;
else
out_4biteven <= out_4biteven + 2;
end

always @(posedge clk or negedge rst) //4bit odd counter

begin
if(!rst)
out_4bitodd <= 4'b0001;
else
out_4bitodd <= out_4bitodd + 4'b0010;
end

always @(posedge clk or negedge rst) //4bit even_odd counter

begin
if(!rst)
out_4bit_evenodd <= 4'b0;
else if (out_4bit_evenodd == 4'b1110)
out_4bit_evenodd <= 4'b0001;
else if (out_4bit_evenodd == 4'b1111)
out_4bit_evenodd <= 4'b0000;
else
out_4bit_evenodd <= out_4bit_evenodd + 2'b10;
end

endmodule

Testbench:
module counter_tb ();
reg clock;
reg reset;
wire [2:0] counter_mod5;
wire [2:0] counter_3bit;
wire [3:0] counter_4biteven;
wire [3:0] counter_4bitodd;
wire [3:0] counter_4bit_evenodd;
counter DUT(.clk(clock), .rst(reset),
.out_mod5(counter_mod5), .out_3bit(counter_3bit),
.out_4biteven(counter_4biteven), .out_4bitodd(counter_4bitodd),
.out_4bit_evenodd(counter_4bit_evenodd));

always #5 clock = ~clock;

initial begin
clock = 1'b0;
reset = 1'b0;
#20 reset = 1'b1;
#200 $finish;
end
endmodule

Output:

RTL Example for blocking assignment:

module blocking(input D,
input clk,
input rst,
output reg Q1,
output reg Q2,
output reg Q3);
always@(posedge clk or negedge rst)
begin
if (!rst) begin
Q1=1'b0; Q2= 1'b0; Q3=1'b0; end
else begin
 Q1=D; Q2=Q1; Q3=Q2; end
end
endmodule

RTL Example for nonblocking assignment:

module nonblocking(input D,
input clk,
input rst,
output reg Q1,
output reg Q2,
output reg Q3);
always@(posedge clk or negedge rst)
begin
if (!rst) begin
Q1<=1'b0; Q2<=1'b0; Q3<=1'b0; end
else begin
Q1<=D; Q2<=Q1; Q3<=Q2; end
end
endmodule

Testbench:
module block_nonblock_tb();
reg d;
reg clock;
reg reset;
wire q1_block,q2_block,q3_block;
wire q1_nonblock,q2_nonblock,q3_nonblock;
blocking DUT1(.D(d),.clk(clock), .rst(reset),.Q1(q1_block),.Q2(q2_block),.Q3(q3_block));
nonblocking DUT2(.D(d),.clk(clock),
.rst(reset),.Q1(q1_nonblock),.Q2(q2_nonblock),.Q3(q3_nonblock));

always #5 clock = ~clock;

initial begin
clock = 1'b0;
d = 1'b1;
reset <= 1'b0;
#20 reset <= 1'b1;
#60 d = 1'b0;
#62 d = 1'b1;
#60 d = 1'b0;
#100 $finish;
end
endmodule
module comb_seq_logic(input a,
input b,
input s0,
input s1,
output Y1);
assign Y1= s0?(s1?b:Y1):a;
endmodule

module comb_seq_logic(input a,
input b,
input rst,
input clk,
output reg Y2);
always@(posedge clk or negedge rst)
begin
if (!rst) Y2<=1'b0;
else Y2<=a&b;
end
endmodule
module comb_seq_logic(input [1:0]s,
input a,
input b,
input c,
input e,
input f,
output reg Y3);
always @(*)
case(s)
2'd0:Y3=a;
2'd1:Y3=b;
2'd2:Y3=c;
2'd3:Y3=e&f;
endcase
endmodule

module comb_seq_logic(input a,
input b,
input c,
input d,
output Y4);
assign Y4= ((a&b)&c)|d;
endmodule
module comb_seq_logic(input a,
input s,
input clk,
input rst,
output reg Y5);
wire y;
assign y=s?a:Y5;
always@(posedge clk or negedge rst)
begin
if (!rst)
Y5<=1'b0;
else begin
Y5<= y;
end
end
endmodule

module comb_seq_logic(input a,
input b,
input c,
input d,
output Y6);
assign Y6 = (a&b)^(c|d);
endmodule
module comb_seq_logic(input [1:0]s,
input a,
input b,
input c,
input d,
input e,
input f,
input g,
input h,
input clk,
input rst,
output reg Y7);
reg x;
always @(*)
begin
case(s)
2'd0:x=a&b;
2'd1:x=c|d;
2'd2:x=e^f;
2'd3:x=(~(g&h));
endcase
end
always@(posedge clk or negedge rst)
begin
if (!rst)
Y7<=1'b0;
 else
Y7<=x;
end
endmodule

module comb_seq_logic(input a,
input b,
input clk,
input rst,
output reg Y8);
reg Q1,Q2;
always@(posedge clk or negedge rst)
begin
if (!rst) begin
Q1<=1'b0;
Q2<=1'b0;
Y8<=1'b0;
end
else begin
Q1<=a;
Q2<=b;
 Y8<=Q1&Q2;
end
end
endmodule

module comb_seq_logic(input a,
input clk,
input rst,
output Y9);
reg Q;
always@(posedge clk or negedge rst)
begin
if (!rst)
Q<=1'b0;
else
Q<=a;
end
assign Y9=((~Q)&a);
endmodule
module comb_seq_logic(input a,
input b,
input clk,
input rst,
output reg Y10);
always@(posedge clk or negedge rst)
begin
if (!rst)
Y10<=1'b0;
else
Y10<=Y10?(a|b):(a&b);
end
endmodule

module comb_seq_logic(input a,
input b,
input clk,
input rst,
 output reg Y11);
wire y;
reg Q1,Q2;

always@(posedge clk or negedge rst)

begin
if (!rst) begin
Q1<=1'b0;
Q2<=1'b0;
Y11<=1'b0;
end
else begin
Q1<=a;
Q2<=a&b;
Y11<=y;
end
end
assign y=Q2?Y11:Q1;
endmodule

Verilog code for operators:

module logic_op(input [3:0]a,
input [3:0]b,
output [3:0]bitwise_and,
output logic_and,
output [3:0]bitwise_or,
output logic_or);
assign bitwise_and = a&b;
assign logic_and = a&&b;
assign bitwise_or = a|b;
assign logic_or = a||b;
endmodule

Testbench:
module logical_op_tb();
reg [3:0]A;
reg [3:0]B;
wire [3:0]bitwise_and;
wire logic_and;
wire [3:0]bitwise_or;
wire logic_or;
integer i,j;
logic_op
DUT(.a(A),.b(B),.bitwise_and(bitwise_and),.logic_and(logic_and),.bitwise_or(bitwise_or),.logic_or(log
ic_or));
initial
begin
 A=4'd0;
B=4'd0;
logic_operators;
end
task logic_operators;
begin
for(i=0;i<16;i=i+1)
begin
A=i;
for(j=0;j<16;j=j+1) begin
B=j;
#15;
end
end
end
endtask
initial begin
$monitor("bitwise_and = %b, logic_and = %b, bitwise_or = %b, logic_or =
%b",bitwise_and,logic_and,bitwise_or,logic_or);
end
endmodule

Hardware:
Verilog code:
module dff(input d,
input clk,
input async_reset,
output posedge_det,
output negedge_det);
reg Q;
always @(posedge clk or negedge async_reset)
begin
if(!async_reset)
Q <= 1'b0;
else
Q <= d;
end
assign posedge_det = d&(~Q);

always @(posedge clk or negedge async_reset)

begin
if(!async_reset)
Q <= 1'b0;
else
Q <= d;
end
assign negedge_det = (~d)&Q;
endmodule

Testbench:
module dff_tb();
reg D;
reg clock;
reg reset;
wire Posedge_det;
wire Negedge_det;
dff DUT(.d(D), .clk(clock), .async_reset(reset), .posedge_det(Posedge_det),
.negedge_det(Negedge_det));
always #5 clock = ~clock;
initial
begin
clock = 1'b0;
reset =0;
D = 0;
#10 reset =1;
repeat(5)
begin
@(posedge clock);
D=0;
end
repeat(20)
begin
@(posedge clock);
D=1;
end
D=0;
#50 $finish;
end
endmodule

Testbench:
module dff_tb();
reg D;
reg clock;
reg reset;
wire Posedge_det;
wire Negedge_det;
integer i;
dff_posedge DUT(.d(D), .clk(clock), .async_reset(reset), .posedge_det(Posedge_det),
.negedge_det(Negedge_det));
always #5 clock = ~clock;
initial
begin
clock = 1'b0;
reset =0;
operators2(5);
end
task operators2;
input [5:0]x;
begin
for(i=0;i<x;i=i+1)
begin
D = 0;
#10 reset =1;
repeat(5)
begin
@(posedge clock);
D=0;
end
repeat(20)
begin
@(posedge clock);
D=1;
end
D=0;
end
#50 $finish;
end
endtask
endmodule

Verilog code of sequence detector:

module sequence_detector(sequence_in,clock,reset,detector_out);
input clock;
input reset;
input sequence_in;
output reg detector_out;
parameter s0=3'b000,
s1=3'b001,
s2=3'b011,
s3=3'b010,
s4=3'b110;
reg [2:0] current_state, next_state;
always @(posedge clock or negedge reset)
begin
if(!reset)
current_state <= s0;
else
current_state <= next_state;
end
always @(current_state,sequence_in)
begin
 case(current_state)
s0:begin
if(sequence_in==1)
next_state = s1;
else
next_state = s0;
end
s1:begin
if(sequence_in==0)
next_state = s2;
else
next_state = s1;
end
s2:begin
if(sequence_in==0)
next_state = s0;
else
next_state = s3;
end
s3:begin
if(sequence_in==0)
next_state = s2;
else
next_state = s4;
end
s4:begin
if(sequence_in==0)
next_state = s2;
else
next_state = s1;
end
default:next_state = s0;
endcase
end
always @(current_state)
begin
case(current_state)
s0: detector_out = 0;
s1: detector_out = 0;
s2: detector_out = 0;
s3: detector_out = 0;
s4: detector_out = 1;
default: detector_out = 0;
endcase
end
endmodule

Testbench:
module sequence_detector_tb();
reg sequence_in;
 reg clock;
reg reset;
wire detector_out;
integer i;
sequence_detector dut (
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out)
);
always #5 clock = ~clock;
initial
begin
clock = 1'b0;
reset =1'b0;
sequence_in = 0;
seqdet(100);
end
task seqdet;
input [6:0]x;
begin
for(i=0;i<x;i=i+1)
begin
#10 reset =1'b1;
@(posedge clock);
sequence_in=$random;
end
#50 $finish;
end
endtask
endmodule

Simulation result:

Verilog code of MSB Detector:

module msb_detector(en,i,y
input en;
input [15:0]i;
output reg [4:0]y;
always @(en,i)
begin
casex(i)
16'b1xxx_xxxx_xxxx_xxxx: y = 5'd16;
16'b1xx_xxxx_xxxx_xxxx: y = 5'd15;
 16'b1x_xxxx_xxxx_xxxx: y = 5'd14;
16'b1_xxxx_xxxx_xxxx: y = 5'd13;
16'b1xxx_xxxx_xxxx: y = 5'd12;
16'b1xx_xxxx_xxxx: y = 5'd11;
16'b1x_xxxx_xxxx: y = 5'd10;
16'b1_xxxx_xxxx: y = 5'd9;
16'b1xxx_xxxx: y = 5'd8;
16'b1xx_xxxx: y = 5'd7;
16'b1x_xxxx: y = 5'd6;
16'b1_xxxx: y = 5'd5;
16'b1xxx: y = 5'd4;
16'b1xx: y = 5'd3;
16'b1x: y = 5'd2;
16'b1: y = 5'd1;
default: y=5'd0;
endcase
end
endmodule

Testbench:
module msbdetector_tb;
reg [15:0]i;
reg en;
wire [4:0]y;
integer I;
msb_detector dut(en,i,y);
initial
begin
en = 1;
i = 0;
seqdet(100);
end
task seqdet;
input [6:0]x;
begin
for(I=0;I<x;I=I+1)
begin
#10
i=$random;
$monitor("i=%b y=%d",i,y);
end
#50 $finish;
end
endtask
endmodule
Verilog code for Multiplier:
module multiplier(
input wire clk, // Clock input
input wire reset, // Reset input
input wire [2:0]shift_in, // Data input to shift in
output wire [3:0] shift_out // Data output );
reg [3:0] reg_data; // 4-bit register

always @(posedge clk or negedge reset) begin

if (!reset) begin
reg_data <= 4'b0000; // Reset the register to 0000
end else begin
reg_data <= {shift_in[2:0],1'b0}; // Shift right and load new data
end
end

assign shift_out = reg_data;

endmodule

Testbench:
module multiplier_tb;
reg clk;
reg reset;
reg [2:0]shift_in;
wire [3:0] shift_out;

multiplier dut (
.clk(clk),
.reset(reset),
.shift_in(shift_in),
.shift_out(shift_out) );
always #5 clk = ~clk;
initial begin
 clk = 0;
#1 clk = 1;
reset = 1;
shift_in = 3'b0;
#10 reset = 1;
shift_in = 3'b110;
$monitor("in=%b out=%d",shift_in,shift_out);
#30 $finish;
end
endmodule

Simulation result:

Verilog code for conditional counter:

module counter_all(
input clk,
input rst,
input [1:0]x,
output [4:0]counter_out);
reg [4:0] counter = 5'b0;

always @(posedge clk or negedge rst)

begin
if (!rst)
counter <= 5'b0 ;
else
counter <= counter + 1;
end
assign counter_out = x[1]?(x[0]?counter:counter[3:0]):(x[0]?counter[2:0]:counter[1:0]);

endmodule

module counterall_tb ();

reg clock;
reg reset;
 reg [1:0]x;
wire [4:0]Counter_Out;
counter_all DUT(.clk(clock), .rst(reset),
.x(x), .counter_out(Counter_Out));

always #5 clock = ~clock;

initial begin
clock = 1'b0;
reset = 1'b0;
x = 2'b00;
#20 reset <= 1'b1;
x = 2'b00;
#100 x = 2'b01;
#100 x = 2'b10;
#100 x = 2'b11;
#50 $finish;
end

endmodule

10_11_2023

1)

Verilog code(serial in serial out shift register):

module output_high1(input clk,
input rst,serial_input, output reg serial_output);
reg [3:0]w;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
w <= 4'b0000; serial_output <= 4'b0;
end
else
begin
if(serial_input) begin
 w <= {w[2:0],serial_input};
serial_output <= serial_input ^ w[1];end
else begin
w <= {w[2:0],serial_input};
serial_output <= serial_input & w[1]; end
end

end
endmodule

Testbench:
module outputhigh_tb1();
reg clk,rst,serial_input;
wire serial_output;
output_high1 DUT(clk,rst,serial_input,serial_output);
always #5 clk = ~clk;
initial
begin
clk = 1'b1;
rst=0;
serial_input=0;
#10 rst<=1'b1;
#20 serial_input=1'b1;
#80 serial_input=1'b0;
#80 serial_input=1'b1;
#80 serial_input=1'b0;
#80 serial_input=1'b1;
#50 $finish;
end
endmodule

Simulation result:

Verilog code(Model 2):

module output_high1(input clk,
input reset,
input d_in,
output data_out);
reg Q;
reg Q1;
wire posedge_det;
always @(posedge clk or negedge reset)
begin
if(!reset)
Q <= 1'b0;
 else
Q <= d_in;
end
assign posedge_det = d_in&(~Q);

always @(posedge clk or negedge reset)

begin
if(!reset)
Q1 <= 1'b0;
else
Q1 <= posedge_det;
end
assign data_out = posedge_det | Q1;
endmodule

Testbench:
module outputhigh_tb1();
reg D;
reg clock;
reg rst;
wire Data_out;
output_high1 DUT(.clk(clock), .reset(rst), .d_in(D), .data_out(Data_out));

always #5 clock = ~clock;

initial
begin
clock = 1'b0;
rst =0;
D = 0;
#10 rst =1;
repeat(5)
begin
@(posedge clock);
D=0;
end
repeat(20)
begin
@(posedge clock);
D=1;
end
D=0;
#50 $finish;
end
endmodule
2)

Verilog code(011 sequence detector):

module sequence_det2(input clock,
input reset,
input sequence_in,
output reg detector_out);

parameter s0=3'b00, s1=3'b01, s2=3'b10, s3=3'b11;

reg [1:0] current_state, next_state;

always @(posedge clock or negedge reset)

begin
if(!reset)
current_state <= s0;
else
current_state <= next_state;
end

always @(current_state,sequence_in)
begin
case(current_state)
s0:begin
if(sequence_in==0) begin
 next_state = s1; detector_out = 0; end
else begin
next_state = s0; detector_out = 0; end
end
s1:begin
if(sequence_in==1)begin
next_state = s2; detector_out = 0; end
else begin
next_state = s1; detector_out = 0; end
end
s2:begin
if(sequence_in==1) begin
next_state = s0; detector_out = 1; end
else begin
next_state = s1; detector_out = 0; end
end
default:next_state = s0;
endcase
end
endmodule

Testbench:
module sequence_det_tb2();
reg sequence_in;
reg clock;
reg reset;
wire detector_out;
sequence_det2 dut (.sequence_in(sequence_in), .clock(clock),
.reset(reset), .detector_out(detector_out));

always #5 clock = ~clock;

initial begin
clock = 1;
sequence_in = 0;
reset = 0;
#10; reset <= 1;
#10; sequence_in = 1;
#50; sequence_in = 0;
#50; sequence_in = 1;
#50; sequence_in = 0;
#50 $finish;
end
endmodule
3)

Verilog code(3bit down counter):

module counter3(
input clk,
input rst,
output reg [2:0]count_out);
wire out_1,out_2,out_3;
always @(posedge clk or negedge rst)
begin
if (!rst)
count_out = 3'b0 ;
else
count_out = count_out - 1;
end
assign out_1 = count_out[0];
assign out_2 = count_out[1];
assign out_3 = count_out[2];
endmodule

Testbench:
module counter_tb3 ();
reg clock;
reg reset;
wire [2:0] count_out;
counter3 DUT(.clk(clock), .rst(reset),
.count_out(count_out));

always #5 clock = ~clock;

initial begin
clock = 1'b0;
reset = 1'b0;
#20 reset = 1'b1;
 #200 $finish;
end

endmodule

Simulation result:

input [1:0]a;
input x;
output reg Y;
assign Y = s?a[1]:a[0]
endmodule

Complilation errors:

module multiplier_73(input [3:0]a,

output [7:0]mul_2,
output [7:0]mul_3,
output [7:0]mul_4,
output [7:0]mul_5,
output [7:0]mul_6,
output [7:0]mul_7,
output [7:0]mul_9,
output reg [7:0]mul_17,
output [11:0]mul_73);

assign mul_2 = {a,1'b0};

assign mul_3 = {a,1'b0}+a;
assign mul_4 = {a,2'b0};
assign mul_5 = {a,2'b0}+a;
assign mul_6 = {a,2'b0}+{a,1'b0};
assign mul_7 = {a,2'b0}+{a,1'b0}+a;
assign mul_9 = {a,3'b0}+a;
assign mul_17 = {a,4'b0}+a;
assign mul_73 = {a,6'd0}+{a,3'b0}+a
endmodule

Testbench:
module multiplier_tb_73();
reg A;
wire [7:0]Mul_2;
wire [7:0]Mul_3;
wire [7:0]Mul_4;
wire [7:0]Mul_5;
wire [7:0]Mul_6;
wire [7:0]Mul_7;
wire [7:0]Mul_9;
wire [7:0]Mul_17;
wire [10:0]Mul_73;
integer i;
multiplier_73 dut(.a(A), .mul_2(Mul_2), .mul_3(Mul_3), .mul_4(Mul_4),
.mul_5(Mul_5),
.mul_6(Mul_6),.mul_7(Mul_7),.mul_9(Mul_9),.mul_17(Mul_17),.mul_73(Mul_73));
initial
begin
for(i=0;i<16;i=i+1)
begin
A=i;
#10;
end
$finish;
end
initial
$monitor("Input a=%b, Output muliplier_output =%b",A,Mul_2);
endmodule

3)reg [3:0]B;

4) //integer i;

5) multiplier_73 dut(.a(A), .mul_3(Mul_2), .mul_3(Mul_3), .mul_4(Mul_4), mul_5(Mul_5),

.mul_6(Mul_6),.mul_7(Mul_7),.mul_9(Mul_9),.mul_17(Mul_17),.mul_73(Mul_73));
Simulation error:

1) multiplier_7 dut(.a(A), .mul_2(Mul_2), .mul_3(Mul_3), .mul_4(Mul_4), mul_5(Mul_5),

.mul_6(Mul_6),.mul_7(Mul_7),.mul_9(Mul_9),.mul_17(Mul_17),.mul_73(Mul_73));

2) multiplier_73 dut(.a(A), .mul_555(Mul_2), .mul_3(Mul_3), .mul_4(Mul_4), mul_5(Mul_5),

.mul_6(Mul_6),.mul_7(Mul_7),.mul_9(Mul_9),.mul_17(Mul_17),.mul_73(Mul_73));

3) vsim -novopt multiplier_tb_

4)multiplier_73 dut(.a(A),.mul_3(Mul_3), .mul_4(Mul_4), .mul_5(Mul_5), .mul_6(Mul_6),

.mul_7(Mul_7),.mul_9(Mul_9),.mul_17(Mul_17),.mul_73(Mul_73));
Fatal error:
Fatal errors in Verilog typically indicate severe issues in your Verilog code that prevent successful
compilation or simulation.
- Mismatched port declarations
- Undeclared signals or modules
- File path issues
Verilog code:
module shiftregister(input wire clk,
input wire reset,
input [7:0]d,
output reg [31:0]data_out);
reg [7:0]out1;
reg [7:0]out2;
reg [7:0]out3;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
out1 <= 8'b0;
out2 <= 8'b0;
out3 <= 8'b0;
data_out<= 32'b0;
end
else
begin
out1 <= d;
out2 <= out1;
out3 <= out2;
data_out <= {d,out1,out2,out3};
end
end
endmodule

Testbench:
module shiftregister_tb();
reg CLK;
reg RESET;
reg [7:0]D;
wire [31:0]DATA_OUT;
shiftregister dut(.clk(CLK),
.reset(RESET),
.d(D),
.data_out(DATA_OUT));
always #5 CLK = ~CLK;
initial begin
CLK = 1'b0;
RESET=0;
D=8'hA;
#10 RESET<=1'b1;
#10 D=8'hB;
#10 D=8'hC;
#10 D=8'hD;
#10 D=8'hE;
#10 D=8'hF;
#10 D=8'h11;
#10 D=8'h22;
#50 $finish;
end
endmodule
Simulation output: