Controlled Processing Unit

Certainly, here are detailed notes based on the provided text:

**Chapter 8: Central Processing Unit (CPU)**

**1. Introduction**
- The CPU (Central Processing Unit) is the core component of a computer responsible for
data-processing operations.
- It consists of three major parts:
1. **Register Set:** Stores intermediate data used during instruction execution.
2. **Arithmetic Logic Unit (ALU):** Performs microoperations required for executing
instructions.
3. **Control Unit:** Supervises information transfer among registers and instructs the
ALU on operations to perform.

**2. Functions of the CPU**

- The CPU performs various functions determined by the type of instructions it executes.
- **Computer architecture** encompasses the computer's structure and behavior as
perceived by the programmer using machine language instructions.
- Elements of computer architecture include instruction formats, addressing modes,
instruction set, and CPU register organization.
- Two prominent computer architectures:
1. **Reduced Instruction Set Computer (RISC):** Emphasizes a smaller, simpler set of
instructions that execute quickly.
2. **Complex Instruction Set Computer (CISC):** Offers a larger, more complex
instruction set, often used for more diverse tasks.

**3. Memory Usage and Architectures**

- Two architectures based on memory usage:
1. **Nonembedded:** Programs and data share the same memory system (Stored
Program Computer - SPC).
2. **Embedded:** Programs and data are stored in separate memory systems (Harvard
architecture), doubling memory bandwidth.
- Examples:
- Nonembedded: Desktop systems, such as personal computers.
- Embedded: Microcontroller-based systems, digital signal processor-based (DSP)
systems.

**4. CPU Design and User's Perspective**

- The CPU's instruction set is a common boundary between the computer designer and the
programmer.
- For designers, the instruction set specifies how the CPU should be constructed.
- Programming in machine or assembly language requires knowledge of:
- Register set
- Memory structure
- Data types supported by instructions
 - Function of each instruction

**5. CPU Organization and Architecture**

- Describes how registers communicate with the ALU through buses.
- Explains the operation of the memory stack.
- Introduces various instruction formats, addressing modes for data retrieval, and typical
instructions used in computers.
- Discusses the concept of Reduced Instruction Set Computer (RISC).

These notes provide an overview of the content covered in Chapter 8, focusing on the CPU,
its components, functions, architectures, and their relevance to both designers and
programmers.

Here are detailed notes based on the provided text from Section 8-2 about General Register
Organization:

**General Register Organization**

1. **Memory vs. Registers**

- In programming examples, it's evident that memory locations are used for storing various
values like pointers, counters, return addresses, temporary results, and partial products
during operations like multiplication.
- Accessing memory locations is time-consuming as it's one of the slowest operations in a
computer.
- Storing intermediate values in processor registers is more efficient and convenient.

2. **Register Communication**
- When a CPU includes a large number of registers, it's efficient to connect them through a
common bus system.
- Registers communicate with each other not only for direct data transfers but also while
performing various microoperations.

3. **Bus Organization**
- A typical bus organization for seven CPU registers is depicted in Figure 8-2.
- Each register's output is connected to two multiplexers (MUX) to form two buses,
referred to as A and B.
- The multiplexers are controlled by selection lines that choose between the register's
content or input data for the specific bus.
- The A and B buses serve as inputs to a common Arithmetic Logic Unit (ALU).

4. **ALU Operation**
- The operation selected in the ALU determines the arithmetic or logic microoperation to
be performed.
- The result of the microoperation is available as output data and also feeds into the inputs
of all the registers.

5. **Register Selection**
 - To determine which register receives information from the output bus, a decoder is
employed.
- The decoder activates one of the register load inputs, establishing a transfer path
between the output bus's data and the selected destination register.

6. **Control Unit**
- The CPU's control unit manages the flow of information through the registers and ALU by
selecting various components in the system.
- For example, to perform an operation like `R1 ← R2 * R3`, the control unit must provide
binary selection variables to:
- MUX A selector (SELA): To place the content of R2 into bus A.
- MUX B selector (SELB): To place the content of R3 into bus B.
- ALU operation selector (OPR): To specify the arithmetic operation (multiplication in this
case).
- Decoder destination selector (SELD): To transfer the content of the output bus into R1.

7. **Timing and Response**

- The control unit generates the necessary control signals at the beginning of a clock cycle.
- During one clock cycle, data from source registers propagate through multiplexers, the
ALU, the output bus, and into the inputs of the destination register.
- On the next clock transition, the binary information from the output bus is transferred
into the designated destination register.
- To achieve fast response times, the ALU is constructed using high-speed circuits, and
buses are implemented with multiplexers or three-state gates.

These notes provide an in-depth understanding of the general register organization within a
CPU and how data is managed and processed within the CPU's architecture.
Certainly, here are detailed notes based on the provided text regarding control words and
examples of microoperations:

**Control Word and Microoperations**

1. **Control Word Definition**

- In the CPU, a 14-bit control word specifies a microoperation.
- The control word consists of four fields:
- SELA (3 bits): Selects a source register for the A input of the ALU.
- SELB (3 bits): Selects a register for the B input of the ALU.
- SELD (3 bits): Selects a destination register using the decoder.
- OPR (5 bits): Selects one of the operations in the ALU.
- The control word determines a specific microoperation when applied to the selection
inputs.

2. **Encoding of Register Selection Fields**

- A table (Table 8-1) specifies the binary codes for register selections based on the 3-bit
binary code in each field.
- Registers are selected by matching the decimal number equivalent to the binary code.
3. **Encoding of ALU Operations**
- ALU operations are specified by a 5-bit field (OPR).
- Each operation is designated by a symbolic name, and the encoding is provided in a table
(Table 8-2).

4. **Examples of Microoperations**
- Microoperations can be defined using control words.
- For example, to perform `R1 ← R2 - R3`, the control word is constructed as follows:
- SELA: R2, SELB: R3, SELD: R1, OPR: SUB
- Control Word: 010 011 001 00101

5. **Microoperations with Different Requirements**

- Some microoperations, like increment and transfer, do not use the B input of the ALU. In
such cases, the B field is marked with a dash.
- Unused fields are assigned 000 in the binary control word.
- Direct transfer from input to output is achieved with a control word of all 0’s (making the
B field 000).

6. **Clearing a Register**
- A register can be cleared to 0 using an exclusive-OR operation because x XOR x equals 0.

7. **Generating Microoperations Efficiently**

- To generate control words with many bits efficiently, they can be stored in a memory
unit, often referred to as a control memory.
- Consecutive control words from memory can initiate a sequence of microoperations,
known as microprogrammed control.

8. **Microprogrammed Control Unit**

- A microprogrammed control unit allows for control words to be read from a control
memory.
- This approach enables the initiation of a desired sequence of microoperations in the CPU.

These notes provide a detailed understanding of control words and how they are used to
specify microoperations in a CPU, along with examples of microoperations and efficient
control word generation techniques using control memory.
Certainly, here are detailed notes based on the provided text regarding stack organization in
CPUs:

**Stack Organization in CPUs**

1. **Introduction to Stack**
- A stack, in the context of computer CPUs, is a storage device that follows the Last-In,
First-Out (LIFO) principle.
- It stores information in such a way that the last item added is the first one to be
retrieved.
- This concept can be likened to a stack of trays where the last tray placed on top is the
first to be removed.
2. **Stack Pointer (SP)**
- A stack in digital computers is essentially a memory unit with an associated stack pointer
(SP).
- The stack pointer is a register that points to the top item in the stack.
- Unlike physical trays in a real-world stack, the registers in a CPU stack are always
available for reading or writing, and it's the content of the words that are inserted or
deleted.

3. **Stack Operations**
- The two primary operations on a stack are:
- **Push**: To insert an item on top of the stack.
- **Pop**: To remove the top item from the stack.
- These operations are simulated by incrementing or decrementing the stack pointer
register.

4. **Register Stack**
- A stack can be organized as a collection of memory words or registers.
- In a register stack, the stack pointer (SP) holds the address of the top item in the stack.
- For example, if item C is on top of the stack, SP contains the address 3.
- Popping an item involves reading the word at the current SP address and decrementing
SP.
- Pushing an item involves incrementing SP and writing a word to the new SP address.

5. **Stack Limits and Status Registers**

- In a finite register stack, SP has a limited range of values.
- SP cannot exceed the maximum address value (e.g., 63 in a 64-word stack).
- Registers like FULL and EMPTY can be used to indicate when the stack is full or empty.
- FULL is set to 1 when the stack is full, and EMPTY is set to 1 when it's empty.
- These status registers help avoid erroneous operations.

6. **Memory Stack**
- A stack can also be implemented in a portion of computer memory.
- In this case, a CPU register (e.g., SP) points to the top of the stack within the memory
segment.
- Push and pop operations involve memory reads and writes using the stack pointer and a
data register (DR).
- Most computers lack hardware checks for stack overflow or underflow, so these limits
can be checked manually using registers.

7. **Microoperations for Push and Pop**

- Push operation: Decrement SP, write data from DR to the top of the stack.
- Pop operation: Read data from the top of the stack to DR, increment SP.

8. **Stack Growth Direction**

- The direction of stack growth depends on the CPU's design.
 - In some CPUs, the stack grows by decreasing memory addresses (e.g., from 4000 to
3999).
- In others, it may grow by increasing addresses (e.g., from 1 to 2).
- The direction determines whether SP is incremented or decremented during push and
pop operations.

9. **Stack Pointer Initialization**

- The stack pointer is initially loaded with the bottom address of the stack in memory.
- Subsequent push and pop operations automatically update the stack pointer.
- This eliminates the need to specify addresses explicitly when referring to the stack.

These detailed notes provide a comprehensive understanding of stack organization in CPUs,

including stack operations, memory stack implementation, and considerations for managing
stack limits and growth directions.
Certainly, here are detailed notes based on the provided text regarding Reverse Polish
Notation (RPN) and its utilization in evaluating arithmetic expressions:

**Reverse Polish Notation (RPN)**

1. **Introduction to RPN**
- Reverse Polish Notation (RPN) is a mathematical notation that places the operator after
the operands.
- It is also known as postfix notation and is particularly useful for evaluating arithmetic
expressions using stack-based processing.

2. **Comparison with Infix Notation**

- Common arithmetic expressions are typically written in infix notation, with operators
placed between operands (e.g., A * B + C).
- RPN is a more computer-friendly representation where operators follow operands (e.g.,
AB* C+).

3. **Advantages of RPN**
- RPN simplifies the evaluation of expressions because it doesn't require scanning back and
forth.
- It naturally lends itself to stack manipulation, making it efficient for computers to
compute complex expressions.

4. **Evaluating RPN Expressions**

- To evaluate an RPN expression, start scanning it from left to right.
- When an operator is encountered, perform the operation with the two operands
immediately to the left of the operator.
- Replace the operands and the operator with the result of the operation.
- Continue this process until there are no more operators left.

5. **Example of RPN Evaluation**

- For the RPN expression AB* CD* +, where A = 3, B = 4, C = 5, and D = 6:
- First, perform A * B, replacing A, B, and * with the product.
 - Then, perform C * D, resulting in (A * B)(C * D).
- Finally, perform the addition of the two products, giving the final result of 42.

6. **RPN Use Cases**

- RPN is efficient for evaluating arithmetic expressions in calculators and some computers.
- It's particularly suitable for complex calculations and chain calculations where multiple
operations are performed in sequence.
- RPN allows for simplified and efficient implementation when used with stack-organized
CPUs.

7. **Conversion to RPN**
- The conversion of an infix expression to RPN takes into account the order of operations
(operator precedence) to ensure correct evaluation.
- Parentheses are not needed in RPN because the order of operations is explicit in the
notation.
- For example, (3 * 4) + (5 * 6) in RPN would be converted to 34 * 56 * +.

8. **RPN in Computer Programming**

- Many compilers convert arithmetic expressions into RPN as it simplifies translation into
machine code instructions.
- RPN-based CPUs can efficiently evaluate these expressions, making them suitable for
specific applications.

These detailed notes provide a comprehensive understanding of Reverse Polish Notation

(RPN), its advantages, evaluation process, and its applications in computing, particularly in
stack-organized CPUs.
Certainly, here are detailed notes based on the provided text regarding instruction formats
in computer architecture:

**Instruction Formats in Computer Architecture**

1. **Introduction to Instruction Formats**

- Reference manuals for computer systems describe their physical and logical structure.
- These manuals detail the CPU's internal construction, available processor registers, their
capabilities, and instructions.
- They specify the binary code format for instructions and provide precise definitions for
each instruction.

2. **Components of Instruction Formats**

- Instruction formats are typically depicted as rectangular boxes representing bits as they
appear in memory words or control registers.
- Instructions are divided into fields, with common fields including:
- Operation code field (opcode): Specifies the operation to be executed.
- Address field: Designates a memory address or processor register.
- Mode field: Specifies how operands or effective addresses are determined.
- Special fields may be used, such as shift count fields for shift-type instructions.
3. **Operation Code Field**
- The operation code field contains bits defining processor operations, like addition,
subtraction, complementing, and shifting.
- Common computer instructions include operations like ADD, SUB, MUL, and DIV.

4. **Address Field**
- The address field specifies either memory addresses or processor registers for data
manipulation.
- Register addresses are binary numbers defining one of the CPU's registers, typically with
k bits, allowing 2^k registers.
- For example, a CPU with 16 registers might use four bits for register addresses.

5. **Types of CPU Organizations**

- CPUs are typically organized into three categories:
1. **Single Accumulator Organization**: All operations involve an implied accumulator
register, using one address field for instructions.
2. **General Register Organization**: Multiple registers are available, and instructions
may use two or three register address fields.
3. **Stack Organization**: Stack-based CPUs use PUSH and POP instructions for stack
manipulation, reducing address fields in arithmetic operations.

6. **Hybrid CPU Organizations**

- Some CPUs combine features from different organizational structures.
- For example, the Intel 8080 microprocessor includes both general register and
accumulator characteristics, along with stack operations.

7. **Influence of Address Fields on Programs**

- The number of address fields in instruction formats impacts program length and
efficiency.
- Three-address instructions lead to concise programs for arithmetic expressions but
require more encoding bits.
- Two-address instructions balance program length and encoding efficiency.
- One-address instructions use an implied accumulator for data manipulation.
- Zero-address instructions are found in stack-organized computers, using reverse Polish
notation for expression evaluation.

8. **RISC (Reduced Instruction Set Computer) Instructions**

- RISC architectures prioritize simplicity and efficiency.
- RISC processors often use load and store instructions for memory access and perform
most operations within registers.
- Computational instructions in RISC often use three registers for addressing.

These detailed notes provide a comprehensive understanding of instruction formats in

computer architecture, including the types of CPU organizations, the influence of address
fields on programming, and the characteristics of RISC instruction sets.
Certainly, here are detailed notes about the various types of instruction formats in
computer architecture, including three-address, two-address, one-address, zero-address
instructions, and RISC instructions:

**Three-Address Instructions:**
- Three-address instruction formats allow each address field to specify either a processor
register or a memory operand.
- Example program in assembly language to evaluate `X * (A * B) * (C * D)`:
```
- The computer in this example has two processor registers, R1 and R2.
- Three-address formats result in concise programs for arithmetic expressions but may
require more bits for encoding instructions.
- Cyber 170 is an example of a computer that uses three-address instructions.

**Two-Address Instructions:**
- Two-address instructions are the most common in commercial computers.
- Each address field can specify either a processor register or a memory word.
- Example program for `X * (A * B) * (C * D)`:
```
- The `MOV` instruction transfers data between memory and processor registers.
- The first symbol in each instruction serves as both the source and destination.

**One-Address Instructions:**
- One-address instructions use an implied accumulator (AC) register for data manipulation.
- In this example, we neglect the need for a second register and assume the AC contains the
result.
- Example program for `X * (A * B) * (C * D)`:
- All operations are performed between the AC register and memory operands.
- A temporary memory location (T) is used to store intermediate results.

**Zero-Address Instructions:**
- Stack-organized computers do not use an address field for ADD and MUL instructions.
- PUSH and POP instructions need an address field to specify stack operands.
- Example program for `X * (A * B) * (C * D)` in a stack-organized computer:
- Expressions in stack computers are often evaluated using reverse Polish notation.
- Zero-address computers derive their name from the absence of an address field in
computational instructions.

**RISC (Reduced Instruction Set Computer) Instructions:**

- RISC architectures prioritize simplicity and efficiency.
- RISC processors primarily use load and store instructions for memory access.
- Most operations are executed within registers without memory references.
- Example program for `X * (A * B) * (C * D)` in a RISC-type CPU:
- Load instructions transfer operands from memory to CPU registers.
- Add and multiply operations are performed within registers.
- The result is stored in memory using store instructions.
These detailed notes provide a comprehensive understanding of various instruction formats
used in computer architecture, their advantages, disadvantages, and examples of programs
for different types of instruction formats.
Certainly, here are detailed notes based on the provided text regarding addressing modes in
computer instruction sets:

**Implied Mode**:
- In implied mode, the operands are specified implicitly in the definition of the instruction.
- For example, the instruction "complement accumulator" is an implied-mode instruction
because the operand (the accumulator) is implied in the instruction's definition.
- Many register reference instructions using an accumulator are implied-mode instructions.

**Immediate Mode**:
- In immediate mode, the operand is specified directly within the instruction itself.
- The instruction includes an operand field containing the actual value to be used with the
operation defined in the instruction.
- Immediate-mode instructions are useful for initializing registers with constant values.

**Register Mode**:
- In register mode, the operands are stored in registers within the CPU.
- The specific register to be used is selected from a register field in the instruction.
- A k-bit field can specify any one of 2^k registers.

**Register Indirect Mode**:

- In this mode, the instruction specifies a CPU register, the contents of which give the
address of the operand in memory.
- The selected register contains the address of the operand, not the operand itself.
- Before using a register indirect mode instruction, the programmer must ensure that the
memory address of the operand is placed in the processor register using a previous
instruction.

**Autoincrement or Autodecrement Mode**:

- Similar to register indirect mode, but the register is incremented or decremented after (or
before) accessing memory.
- This mode is particularly useful when accessing a table of data in memory where the
register needs to be adjusted after each access.
- Some computers incorporate a special mode that automatically handles the increment or
decrement of the register after data access.

**Relative Address Mode**:

- In this mode, the content of the program counter is added to the address part of the
instruction to obtain the effective address.
- The address part of the instruction is typically a signed number, and the result represents
an address relative to the next instruction's address.
- Relative addressing is often used with branch-type instructions to specify branch addresses
within proximity of the current instruction.
**Indexed Addressing Mode**:
- In this mode, the content of an index register is added to the address part of the
instruction to compute the effective address.
- The index register holds an index value, and the instruction defines the starting address of
a data array in memory. Each operand in the array is stored relative to the start address.

**Base Register Addressing Mode**:

- Similar to indexed addressing but uses a base register instead of an index register.
- The address field in the instruction provides a displacement relative to the base address
held in the base register.
- This mode is useful for program relocation in memory, allowing instructions to remain
constant while only updating the base register for memory segment changes.

These addressing modes provide flexibility in how operands are accessed in instructions and
are essential for various computational and control tasks in computer systems.
NUMERICAL EXAMPLE: DONE