Ky Thuat So

Digital system design
Robotic & Vision Lab RoVis

Digital Systems
Digital vs. Analog Waveforms
+5 +5
1 0 1
V V
Time Time
–5 –5
Digital: Analog:
only assumes discrete values values vary over a broad range
continuously

Binary Digits and Logic Levels
• In binary, a single number is called a bit (for binary digit).A bit can have the
value of either a 0 or a 1, depending on if the voltage is HIGH or LOW.
VH(max)
HIGH
VH(min)
Invalid
VL(max)
LOW
VL(min)

Decimal base 10
Binary base 2

Hexadecimal base 16

From decimal to binary

Decimal to hexadecimal
Surplus
Surplus
Surplus

Binary to Hexadecimal
Hexadecimal to Binary

Binary characteristics
Transform

2. Mathemmatic of binary:
a. Add :
1 1 1
0 + 0 = 0
0 + 1 = 1 1 0 1 1 1
1 + 0 = 1 1 0 1
1 + 1 = 0 nhôù 1 1 1 1 0 0
b. Subtract:
-1 -1 -1
0 - 0 = 0
0 - 1 = 1 möôïn 1 1 1 0 1 0
1 - 0 = 1 1 1 1
1 - 1 = 0 1 0 0 1 1
13
c. Multiply: 1 0 1 1
1 0 0 1
1 0 1 1
0 0 0 0
0 0 0 0
1 0 1 1
1 1 0 0 0 1 1
d. Divide:
1 0 0 1 0 0 0 1 1 0 1 1
1 0 1 1
1 1 0 1
1 1 1 0
1 0 1 1
1 1 0 1
1 0 1 1
1 0
Sign Value
- The left-most bit in a signed binary number is the sign bit,
which tells you whether the number is positive or negative.
- A 0 sign bit indicates a positive number, and a 1 sign bit
indicates a negative number.
+ 13 : 01101
- 13 : 11101
+ 25 : 0 0011001
- 25 : 1 0011001

1’s Complement
• Method: Invert the ones and zeros
• 1110 = 00001011
• -1110 = 11110100
• 0 in MSB implies positive

• 1 in MSB implies negative

Two’s Complement
• Method: Take the one’s complement and add 1
• 1110 = 00001011
• -1110 = 11110100 one’s comp
• -1110 = 11110101 two’s comp

Signed Binary Arithmetic:
- Like signed decimal Arithmetic .
- The calculation and result must have similar number of
bits
- If result are not in the bit range, should increase the
number of bits of the calculation)
-6 : 1010 -2 : 1110
+ +
+3 : 0011 -5 : 1011
-3 : 1101 -7 : 1001
+4 : 0100 00100
+
+5 : 0101 00101
-7 : 1 0 0 1 (Wrong) 0 1 0 0 1 : + 9 (Correct)
-6 : 1010 +2 : 0010
- -
-2 : 1110 -5 : 1011
-4 : 1100 +7 : 0111
-7 : 1001 11001
-
+5 : 0101 00101
+ 4 : 0 1 0 0 (Kq sai) 1 0 1 0 0 : - 12 (Kq ñuùng)

22
Maõ kyù töï ASCII:

Seven Segment Displays
This presentation will demonstrate how
• A seven-segment display can be used to display the decimal
numbers 0-9 and some alpha characters.
• A common anode seven-segment display works.
• A common cathode seven-segment display works.
• To select the resistor value for a seven-segment display.
Retro
LED Watch
(Circa 1970s)

a
f g b
e c
f g b
e c

Truth Tables for logic operators
Truth table: tabular form that uniguely represents the relationship

between the input variables of a function and its output
2-Input AND 2-Input OR

A B F=A•B A B F=A+B
0 0 0 0 0 0 NOT
0 1 0 0 1 1 A F=A’
1 0 0 1 0 1 0 1
1 1 1 1 1 1 1 0

Truth Tables (cont.)
• Q: Let a function F() depend on n variables. How

many rows are there in the truth table of F() ?
n n
 A: 2 rows, since there are 2 possible binary
patterns/combinations for the n variables

Boolean Function
• Function formed from binary variable and binary equation: NOT,
AND, OR
• EX:

Simplify the following Boolean expression:

Simplify the following Boolean expression:

Simplify the expression

Canonical Forms (Unique)
• Any Boolean function F( ) can be expressed as a unique

sum of minterms and a unique product of maxterms
(under a fixed variable ordering).
• In other words, every function F() has two canonical
forms:
• Canonical Sum-Of-Products (sum of minterms)
• Canonical Product-Of-Sums (product of maxterms)
Boolean Algebra

2018/8/4 PJF - 48
Canonical Forms (cont.)
• Canonical Sum-Of-Products:
The minterms included are those mj such that F( ) = 1
in row j of the truth table for F( ).
• Canonical Product-Of-Sums:
The maxterms included are those Mj such that F( ) = 0
in row j of the truth table for F( ).
Boolean Algebra

2018/8/4 PJF - 49
Caùc tích chuaån (minterm) vaø toång chuaån (Maxterm):
- Minterm: In a Boolean function, a product term in which all
the variables appear is called a minterm of the function.
- Maxterm: A sum term that contains all the variables in
complemented or un-complemented form is called a
maxterm
x y z minterm Maxterm
0 0 0 m0 = x y z M0 = x + y + z
0 0 1 m1 = x y z M1 = x + y + z
0 1 0 m2 = x y z M2 = x + y + z
0 1 1 m3 = x y z M3 = x + y + z
1 0 0 m4 = x y z M4 = x + y + z
1 0 1 m5 = x y z M5 = x + y + z
1 1 0 m6 = x y z M6 = x + y + z
1 1 1 m7 = x y z M7 = x + y + z

Minterms and Maxterms for n variable functions

Example
x y z F F(x, y, z) = x y z + x y z + x y z + x y z + x y z
0 0 0 0 = m1 + m2 + m5 + m6 + m7
0 0 1 1
0 1 0 1
=  m(1, 2, 5, 6, 7)
0 1 1 0 =  (1, 2, 5, 6, 7)
1 0 0 0
1 0 1 1 F(x, y, z) = (x + y + z) (x + y + z) (x + y + z)
1 1 0 1 = M0 . M3 . M4
1 1 1 1
=  M(0, 3, 4) =  (0, 3, 4)
b. Daïng chính taéc 2:

* Don’t care value (X):
Don’t care value can be 0 or 1.
x y z F
0 0 0 X F (x, y, z) =  (1, 2, 5, 6) + d (0, 7)
0 0 1 1
0 1 0 1 =  (3, 4) . D (0, 7)
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 X

Circuit Implementation of a Logic Expression with Gates
Logic Diagram with Gates
Logic Function A X
B
X = A + BC B
C BC
Logic Diagram with Gates
Logic Function A A+B

B
X = (A + B)C B X
C

 Determine the final output waveform X for the circuit, with
input waveforms A, B, and C as shown

Reduce the combinational logic circuit

 Write down the output expression
 Simplify the equation

 In a certain chemical-processing plant, a liquid chemical is used
in a manufacturing process. The chemical is stored in three
different tanks.
 A level sensor in each tank produces a HIGH voltage when the
level of chemical in the tank drops below a specified point.
 - Design a circuit that monitors the chemical level in each tank
and indicates when the level in any two of the tanks drops
below the specified point.

Suppose the cash room at a store has access restricted to certain employees, each of whom has a
key, which produces a logic 1 at particular inputs to an unlocking circuit.
Only the store manager (M) can enter alone. The assistant manager (A) and the cashier (C) also
have access, but only when accompanied by each other, or by the store manager. Design a
combinational logic circuit that will allow access by producing a logic 1 when the above conditions
are met.
X = M + M•C + A•C + A•M + A•C•M

Decoders
• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a
number of outputs ‘m’, where m= 2n
• Only one of the outputs is enabled at a time. The output enabled is the one
specified by the binary number formed at the inputs of the decoder.
• On the circuit below, the inputs of the decoder are connected on three switches,
forming the number 5 [(101)2], thus only LED #5 will be ON
1 1 1 0 1 2 3 4 5 6 7
0 0 0
0 1 0 1 0 1
3/8 DEC.
Y0
Y1
A0
Y2
A1 Y3
Y4
A2
Y5
Y6
Y7

IC 74LS138

2 to 4 Line Decoder:
2-to-4 Line Decoder
2/4 DEC A1 A0 Y0 Y1 Y2 Y3 Y0 = A1 A 0 Y0
Y0 0 0 1 0 0 0 Y1 = A 1 A 0 A1
A1 Y1
Y1 0 1 0 1 0 0 Y2 = A1 A 0
A0 Y2 Y2
1 0 0 0 1 0 Y3 = A1 A 0
A0
Y3 1 1 0 0 0 1 Logic Y3
Expressions
Logic Symbol Truth Table Logic Circuit
2-to-4 Line Decoder with Enable Input

2/4 DEC E A1 A0 Y0 Y1 Y2 Y3 Y0 = E A1 A 0
A1 Y0
A1 Y0 0 X X 0 0 0 0
Y1 = E A 1 A 0
Y1
A0 Y1 1 0 0 1 0 0 0
E
Y2 = E A1 A 0
Y2 1 0 1 0 1 0 0 Y2
E Y3 1 1 0 0 0 1 0 Y3 = E A1 A 0 A0
Y3
1 1 1 0 0 0 1 Logic
Logic Symbol Truth Table Expressions Logic Circuit

Exercise - solution
Implement the function F using a 2-to-4 decoder

and two tri-state buffers
F=C(AB+A’B’) = ABC + A’B’C
B 1 0 B’C A F
1
2
C 0 3 BC

Exercise
Can you also implement F using a 2-to-4 decoder

with enable input and an OR gate?
F=C(AB+A’B’)

Exercise - solution
1. Using a 2-to-4 decoder with enable input and
an OR gate:
F=C(AB+A’B’) = ABC + A’B’C

EN
A’B’
A 1 0
1 F
2
B 0 3 AB
EN

Exercise: Controller for rear lights of a car
• Word description of the problem: Design a

circuit that controls the rear lights of a car: Left
and Right rear lights.
• Assume that is a single lamp in each of the
rear lights.

Example (continued): Specification
• The inputs to the controller are:
Name Description
LT Left turn signal: causes blinking of left side light
RT Right turn signal
EM Emergency flasher: both lights blink
BR Break is applied: both lights are on
BL Internal signal of 1Hz frequency
• Outputs signals:
Name Description
Left Power control for the left rear light
Right Power control for the right rear light

Example (continued): Specification 2
• The break BR overrides the emergency EM

signal
• The Left turn LR and Right turn RT overrides
the break signals BR.
• Implement the two power control signals as:

• Minimized SOP
• Decoder with NOR gates
• Multiplexer

Example (cont): Formulation
Left LT BR EM BL Left RT BR EM BL Right

0 0 0 0
Right 0 0 0 0
Light 0 0
0 0 0 1 0 Light 0 0 0 1 0
0 0 1 0 0 0 0 1 0 0
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 0 1 0 1 1
0 1 1 0 1 0 1 1 0 1
0 1 1 1 1 0 1 1 1 1
1 0 0 0 0 1 0 0 0 0
1 0 0 1 1 1 0 0 1 1
1 0 1 0 0 1 0 1 0 0
1 0 1 1 1 1 0 1 1 1
1 1 0 0 0 1 1 0 0 0
1 1 0 1 1 1 1 0 1 1
1 1 1 0 0 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1
Example (cont): Mapping (SOP)
LT BR EM BL Left
0 0 0 0 0
0 0 0 1 0 K-map:
0 0 1 0 0 Left EM
0 0 1 1 1
0 1 0 0 1 0 0 1 0
0 1 0 1 1
1 1 1 1
0 1 1 0 1 BR
0 1 1 1 1 0 1 1 0
1 0 0 0 0 LT
1 0 0 1 1
0 1 1 0
1 0 1 0 0 BL
1 0 1 1 1
1 1 0 0 0 Left= LT.BL + LT’.BR + EM.BL
1 1 0 1 1 Same for Right:
1 1 1 0 0 Right= RT.BL + RT’.BR + EM.BL
1 1 1 1 1
Example (cont): Encoder with NOR
• Left signal: implement the complement
Left’= m(0,1,2,8,10,12,14)
0
1
2
Left
3
LT 4
3 5
BR 2 6
EM 7
1 8
BL 0 9
10
11
12
13
14
15

Karnaugh Maps (K maps)

What are Karnaugh1 maps?
• Karnaugh maps provide an alternative way of simplifying

logic circuits.
• Instead of using Boolean algebra simplification
techniques, you can transfer logic values from a Boolean
statement or a truth table into a Karnaugh map.
• The arrangement of 0 and 1 within the map helps you to
visualize the logic relationships between the variables
and leads directly to a simplified Boolean statement.
1Named for the American electrical engineer Maurice Karnaugh.

Karnaugh maps
• The Karnaugh map is completed by entering a ‘1‘(or

‘0’) in each of the appropriate cells.
• Within the map, adjacent cells containing 1 (or 0) are
grouped together in twos, fours, or eights.

2-variable Karnaugh
F A F A
0 1 0 1
B B
0 1 1 0 F (A, B) =  (0, 2) + d(3) =
 (1) . D(3)
1 X 1 0 X
3-variable Karnaugh
F AB F AB
C 00 01 11 10 C 00 01 11 10
0 X 1 1 0 X 0
1 X 1 1 X 0 0
F (A, B, C) =  (2, 4, 7) + d(0, 1) =  (3, 5, 6) . D(0, 1)

4-variable Karnaugh F AB
CD 00 01 11 10
00
01
11
5-variable Karnaugh 10
F BCA 0 1
DE
00 01 11 10 10 11 01 00
00
01
11
10
Example
2-variable Karnaugh maps are trivial but can be used to introduce
the methods you need to learn. The map for a 2-input OR gate
looks like this:
A
0 1
B
A
Y 0 1
B
A
1 1 1
A B Y
0 0 0
B
0 1 1
1 0 1
A+B
1 1 1

minterm
The types of structures

that are either minterms or
are generated by repeated
application of the
minimization theorem on a
three variable map are
shown at right.
Groups of 1, 2, 4, 8 are
possible. group of 2 terms
group of 4 terms

2018/8/4 PJF - 85
Boolean
Algebra
Double connection (2 nearby blocks are 1 or 0):
- we will have the multiply function that omits one variable. The
omitted variable is the variable that have different number
- Or we will have the sum function that omits one variable. The
omitted variable is the variable that have different number
F AB F AB
C 00 01 11 10 C 00 01 11 10
0 1 1 0 0
1 1 0
BC A +B

F AB F AB
C 00 01 11 10 C 00 01 11 10
0 1 1 0
1 1 1 1 0 0 0 0
B C
Four-connection (4 nearby blocks are 1 or 0):

- we will have the multiply function that omits 2 variables. The
omitted variables are the variable that have different number
- Or we will have the sum function that omits 2 variables. The

F AB F AB
CD 00 01 11 10 CD 00 01 11 10
00 00 0 0
01 1 1 1 1 01 0 0
11 1 1 1 1 11 0 0
10 10 0 0
D B
Eight-connection (8 nearby blocks are 1 or 0):
- we will have the multiply function that omits 3 variables. The
- Or we will have the sum function that omits 3 variables. The
Two nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 00 0
01 01
11 11
10 10 0
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 00
01 01
11 11 0
10 1 1 10
0

Four nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 1 1 00
01 CD 01 1 1
11 11 1 1
AD
10 10
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 AD 00
01 01 1 1
BD
11 11 1 1
10 1 1 10

Four nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 0 0 0 0 C D 00
01 01 0 0
11
A D 11 0 0
10 10
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 0 0 A D 00
01 01 0 0
B D 0
11 11 0
10 0 0 10

Four nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 00 0 0
CD
01 0 0 0 0 01 0 0
11 A  C 11
10 10
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 0 0 00 0 0
01
B  C 01 0 0
11 B D 11
10 0 0 10

Four nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 00 1 1
CD
01 1 1 1 1 01 1 1
11 A C 11
10 10
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 00 1 1
01 B C 01 1 1
11
BD 11
10 1 1 10

Eight nearby blocks
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 1 1 00 0 0
C
01 1 1 1 1 01 0 0
A
11 11 0 0
10 10 0 0
F F
AB AB
00 01 11 10 00 01 11 10
CD CD
00 1 1 1 1 00
01 01 0 0 0 0
D D
11 11 0 0 0 0
10 1 1 1 1 10

Steps to simplify S.O.P:
- Write number 1 into Karnaugh blocks

- Connect block have number 1. Make sure two nearby
blocks are connected at least one time. One connection
produce one multiply result
- The final result is the sum of multiply result above
F(A, B, C) =  (0, 1, 3, 5, 6) = A B + A C + B C + A B C
F AB
C 00 01 11 10 ABC
0 1 1
AB 1 1 1 1
BC
AC

97
98
Simplify function
F AB
00 01 11 10
CD
00 1 1
01 1
11 1 1
10 1 1
F ( A, B, C , D )  A B C D  A B  BC
F(A, B, C, D)   (0,1,4,5,6,7,14,15)
F
AB
00 01 11 10
CD
00 1 1
01 1 1
Redundant
11 1 1
connection
10 1 1
F(A, B, C, D)  A C  BC
Example
AC
A B C Y
0 0 0 1 AB
C 00 01 11 10
0 0 1 1
0 1 0 0 0 1 1 1
0 1 1 0
1 0 0 1 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0 B
B  AC
Exercise
Given the truth table, find the simplified SOP and POS form.
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Don't Care Conditions
• There may be a combination of input values which

• will never occur
• if they do occur, the output is of no concern.
• The function value for such combinations is called a don't
care.
• They are denoted with x or –. Each x may be arbitrarily
assigned the value 0 or 1 in an implementation.
• Don’t cares can be used to further simplify a function

Boolean 2018/8/4 PJF - 105
Algebra
Minimization using Don’t Cares
• Treat don't cares as if they are 1s to generate PIs.

• Delete PI's that cover only don't care minterms.
• Treat the covering of remaining don't care
minterms as optional in the selection process (i.e.
they may be, but need not be, covered).

Boolean 2018/8/4 PJF - 106
Algebra
Don’t care term
* Boolean simplyfication with don’t care term: can consider
this block is either 1 or 0
AB
CD 00 01 11 10
X
00
01
X 1
11 X X
10 X X
AD
F(A, B, C, D) =  (0, 4, 8, 10) + d (2, 12, 15)
= BD +CD
F AB
CD 00 01 11 10
00 1 1 X 1 CD
01
11 X
10 X 1
BD

108
F(A, B, C, D) =  (0, 2, 3, 4, 6, 10, 14) . D (8, 9, 11, 12, 13)
= D (B + C)
F AB
CD 00 01 11 10
00 0 0 X X D
01 X X
11 0 X
(B + C)
10 0 0 0 0

Example
cd
• Simplify the function f(a,b,c,d) ab 00 01 11 10
whose K-map is shown at the right. 00 0 1 0 1
01 1 1 0 1
• f = a’c’d+ab’+cd’+a’bc’ 11 0 0 x x
or 10 1 1 x x
• f = a’c’d+ab’+cd’+a’bd’
0 1 0 1 0 1 0 1
1 1 0 1 1 1 0 1
0 0 x x 0 0 x x
1 1 x x 1 1 x x

Boolean 2018/8/4
Algebra
Another Example cd
ab
x 1 0 0
1 x 0 x
• Simplify the function g(a,b,c,d) 1 x x 1
whose K-map is shown at right. 0 x x 0
• g = a’c’+ ab
or
• g = a’c’+b’d x 1 0 0
x 1 0 0
1 x 0 x
1 x 0 x
1 x x 1
1 x x 1
0 x x 0
0 x x 0

Boolean 2018/8/4
Algebra
112
Internal structure of a 2-to-1 multiplexer.
 The design of a 2-to-1 multiplexer is shown below.

 If S=0 then the output “Y” has the same value as the input “I0”
 If S=1 then the output “Y” has the same value as the input “I1”
2/1 MUX S I1 I0 Y
I0
I0 0 0 0 0
Y I1I0
I1 0 0 1 1 S 00 01 11 10 1/2 Dec.
S 0 1 0 0 0 0 1 1 0 S Y
Logic Symbol 0 1 1 1 1 0 0 1 1
1 0 0 0
S Y 1 0 1 0 I1
Y = S I0 + S I1
0 I0 1 1 0 1
1 I1 1 1 1 1
Logic Expression Logic Circuit
Logic Function Truth Table

 7400 Series TTL Logic Chips
 The 7400 NAND Chip: pin layout
The equivalent logic layout
1 14
00
Vcc = +5V 1
3
2
2 13
3 12 4
6
5
4 11
9
5 10 8
10
6 9
12
7 8 11
Gnd 13
7400

 7400 Series Implementation
 Implementing f = x1x2 + x2'x3 using 7400 series ICs

Movie Clips

Exercise
 Design the control circuit using three variables: PWM, Direction, Brake
a) Logic Algebra
b) K-Map
 Design the control circuit for a gaming using 4 inputs
 Circuit works only reset switch is 1. When reset switch is 0 all led will be OFF
 One led is ON if input to resistor is 1.
 Just One led is ON when all player push button.
VCC
VCC R1
R2 R3
Play er1
R1
Q1 D1
Play er2
R1
Q2 D2
Play er3
R1 D3
Q3
Reset
1 2

Sequential Logic Circuits
 So far we have only considered circuits where the

output is purely a function of the inputs
 With sequential circuits the output is a function of the

values of past and present inputs

Sequential circuit concepts
The addition of a memory device to a combinational circuit

allows the output to be fed back into the input:
Input(s) Output(s)
circuit
memory

R=0 and S=0 will hold value

Application of the SR Latch
• An important application of SR latches is for recording short

lived events
• e.g. pressing an alarm bell in a hospital
bed1
R Q light
RS
Latch
1 S
bed1
button bed2
R Q light
bed2 RS
button Latch
1 S warning
bell
1 master
reset

COUNTER
 Counter is constructed from
two connected FlipFlop
• Sequential counter have 1 clock (CK) input and many outputs. The
Output are the Flipflop output
• When feeding one pulse clock, the status (number)

of the counter will change
Status diagram of the counter

There are two type of counters
 Asynchronous counter (Bộ điếm nối tiếp): output of previous FF is the pulse input o
the current FF
 Count Up: counter increase 1 when have one pulse input
 Count Down: counter decrease 1 when have one pulse input
 Synchronous (Bộ đếm song song) : the input pulse (CK) of all FF are connected to
each other. When pulse occurs all status of FF will change
 Using to design an arbitrary counter loop (counter do not have order)

• Count Down
• Count Up

Count Up
Q0(LSB) Q1 Q2(MSB)
1 T Q 1 T Q 1 T Q
CK CK Q CK Q CK Q
CK
Q0
(LSB)
Q1
Q2
(MSB)
Count Down
Q0(LSB) Q1 Q2(MSB)
1 J Q 1 J Q 1 J Q
CK CK CK CK
1 K Q 1 K Q 1 K Q
CK
Q0
(LSB)
Q1
Q2
(MSB)
Count Up

Count down

555 operation

Design a counter (m 2n):
- Identify the undesired status of the loop (the stopping number)
- Using this status to activate the preset and clear input to reset the
status of the counter to the initial value
EX: Using T-FF pulse down edge and one preset input, to design
the counter up m = 5, and initial value is 0.
Q2 Q1 Q0 Z Z is the reset signal
0 0 0 0 Z Q2Q1
0 0 1 0 Q0 00 01 11 10
0 1 0 0
0 1 1 0
0 X
1 0 0 0 1 X 1
1 0 1 1
1 1 0 X Z = Q 2 Q0
1 1 1 X

Q0(LSB) Q1 Q2(MSB)
0 0 0
1 T Pr Q 1 T Pr Q 1 T Pr Q
CK Ck Q Ck Q Ck Q
Cl Cl Cl
CK
Q0
(LSB)
Q1
Q2
(MSB)
EX: Using JK-FF Pulse down edge and one Q2 Q1 Q0
Preset, Clear active low; to design counter 0 1 0
0 0 1
down m = 5 and initial value is 2. 0 0 0
1 1 1
Z is reset signal: Z = Q2 Q1 (tích cöïc thaáp) 1 1 0
1 0 1
Q0(LSB) Q1 Q2(MSB)
1 1
Pr Pr Pr
1 J Q 1 J Q 1 J Q
CK CK CK
CK
1 K Q 1 K Q 1 K Q
Cl Cl Cl
1
Redraw the Wave form of this example
Boä ñeám song song (Synchronous Counter): :
 The input pulse (CK) of all FF are connected to each other. When
pulse occurs all status of FF will change
 Do not need to consider the activated condition of Pulse (up or
down). Consider the current status and next status
 Design a arbitrary counter loop
* SR-FF * JK-FF
* D-FF:
Q Q+ S R J K
D = Q+
0 0 0 X 0 X
* T-FF: 0 1 1 0 1 X
1 0 0 1 X 1
T = Q  Q+ 1 1 X 0 X 0

Step to design
 - Calculate number of FF need to be used

 - Draw the table to illustrate the relation between current and next
status
Current status Next status FF input
Qn-1 … Q1 Q0 Q+n-1 … Q+1 Q+0
0 … 0 0
1 … 1 1
 Find the value of FF that will change the current to next value based
on FF table
 Simplify the equation.

EX: Using T-FF active up edge, design the counter: Q2Q1Q0
: 010, 101, 110, 001, 000, 111, 100, 011, 010, …
T2 Q2Q1
Current Next FF Q0 00 01 11 10
Q2 Q1 Q0 Q + 2 Q+ 1 Q+ 0 T2 T1 T0 0 1 1 1 1
0 0 0 1 1 1 1 1 1
0 0 1 0 0 0 0 0 1 1
0 1 0 1 0 1 1 1 1
0 1 1 0 1 0 0 0 1 T1 Q2Q1
1 0 0 0 1 1 1 1 1 Q0 00 01 11 10
1 0 1 1 1 0 0 1 1 0 1 1 1 1
1 1 0 0 0 1 1 1 1
1 1 1 1 0 0 0 1 1 1 1 1
T2 = Q0 T1 = Q0 + Q2 T0 = 1
T2 = Q0 T 1 = Q0 + Q 2 T0 = 1
Q2(MSB) Q1 Q0(LSB)
T2 Q T1 Q 1 T0 Q
2 1 0
CK2 CK1 CK0

CK Q Q Q
2 1 0

Exercise: Step motor controller

171
http://www.eeweb.com/blog/extreme_circuits/quiz-circuit

172
Incomplete counter(m < 2n):
 There are two method to solve the undesired value in the loop
 Method 1: undesired value will be assign a value. Needing to start the
initial value for the counter. The initial value is one of the desired
value
Current Next
EX: Design counter D-FF active up
Q2 Q 1 Q0 Q+ 2 Q + 1 Q+ 0
edge, Pr and Cl active up edge
0 0 0 1 0 0
Q 2Q 1Q 0 0 0 1 X X X
0 1 0 1 1 0
000
0 1 1 0 1 0
1 0 0 0 1 1
110 100 1 0 1 X X X
1 1 0 0 0 0
1 1 1 X X X
010 011 D2 D1 D0
D2 = Q 2 Q0 D1 = Q 2  Q1 D0 = Q 2 Q1
Q2(MSB) Q1 Q0(LSB)
0 0
D2 Pr Q D1 Pr Q D0 Pr Q
2 1 0
Ck2 Ck1 Ck0

CK Cl Cl Cl
Q Q Q
0 2 1 0
RS
Method 2: assign an undesired value one value in the loop
Q 2Q 1Q 0
001 000
101 110 100
111 010 011
Current Next FF
Q2 Q1 Q0 Q + 2 Q+ 1 Q+ 0 T2 T1 T0 T 2 = Q0 + Q 2 Q 1
0 0 0 1 0 0 1 0 0
0 0 1 1 1 0 1 1 1
0 1 0 1 1 0 1 0 0 T1 = Q2  (Q1 Q0)
0 1 1 0 1 0 0 0 1
1 0 0 0 1 1 1 1 1
1 0 1 1 0 0 0 0 1 T 0 = Q0 + Q 2 Q 1
1 1 0 0 0 0 1 1 0
1 1 1 1 0 0 0 1 1
Current FF input Next value

4-bit Serial-in to Parallel-out Shift Register

4-bit Serial-in to Serial-out Shift Register
this type of Shift Register also acts as a temporary storage device or as a time
delay device for the data, with the amount of time delay being controlled by
the number of stages in the register, 4, 8, 16 etc or by varying the application
of the clock pulses. Commonly available IC’s include the 74HC595 8-bit
Serial-in to Serial-out Shift Register all with 3-state outputs.

4-bit Parallel-in to Serial-out Shift Register
As this type of shift register converts parallel data, such as an 8-bit data
word into serial format, it can be used to multiplex many different input
lines into a single serial DATA stream which can be sent directly to a
computer or transmitted over a communications line. Commonly
available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift
Registers.
Parallel-in to Parallel-out (PIPO) Shift Register
This type of shift register also acts as a temporary storage device or as a

time delay device similar to the SISO configuration above
Digital Design Process

• Design Loop for Digital Hardware
• The basic design loop:
• Initial design takes

creativity and
experience
• CAD tools are used

for simulation and to
work out details

• The Entire Development Process
• Design is only one part
• Verification and testing

are also important – this
is called design verification
• Errors may not be uncovered

until after the prototype is made
• Errors may not be uncovered

until after “release”!
• Pentium bug

• Simulation Phase
• Functional simulation
• Test the circuit to determine if it correctly performs all the
functions that are required
• Timing simulation
• Test the circuit to determine if it meets the timing requirements
• Correct functionality does not necessarily lead to fast speed
• The physical design / layout will affect the timing

• Inherent gate delays
• Physical wiring leaves metal traces that have resistance

• CAD Tools
• There are a number of commonly used industry standard

CAD tools
• CAD = Computer Aided Design
• Altera, Cadence, Mentor Graphics, Synopsys, Synplicity, Xilinx
• Tools are used for multiple purposes

• Synthesis, timing simulation, functional simulation, layout
• Can even download the design onto a PCB

Analog Signal
Continuous—represented analogously as a value of a

continuously variable parameter
i) position of a needle on a meter

ii) rotational angle of a gear
iii) amount of water in a vessel
iv) electric charge on a capacitor

Analog-to-Digital Conversion
Terminology
analog-to-digital converter: ADC, A/D, A2D; converts an analog

signal to a digital signal
digital-to-analog converter: DAC, D/A, D2A
An embedded system’s surroundings typically involve many analog

signals.

Resolution
Let n = 2 Vmax 3=11

M = 2n
4 steps on the digital
scale
d0 = 0 = 0b00 2=10
dVmax - r = 3 = 0b11 (no

dVmax )
r, resolution: smallest 1=01
analog change resulting

from changing one bit
0V 0=00

ADC using successive approximation
• Given an analog input signal whose voltage should

range from 0 to 15 volts, and an 8-bit digital
encoding, calculate the correct encoding for 5 volts.
Then trace the successive-approximation approach
to find the correct encoding.
• Assume M = 2n – 1
a / Vmax = d / M
5 / 15 = d / (256 - 1)
d = 85 or binary 01010101

ADC Converter 5V

ADC converter using reference source

Digital To Analog (DAC)

Ky Thuat So

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