LTC5584

30MHz to 1.4GHz IQ
Demodulator with IIP2 and
DC Offset Control
Features Description
n I/Q Bandwidth of 530MHz or Higher The LTC®5584 is a direct conversion quadrature demodu-
n High IIP3: 31dBm at 450MHz, 28dBm at 900MHz lator optimized for high linearity receiver applications in
n High IIP2: 70dBm at 450MHz, 65dBm at 900MHz the 30MHz to 1.4GHz frequency range. It is also usable
n User Adjustable IIP2 to >80dBm in the 10MHz to 30MHz and 1.4GHz to 2GHz ranges with
n User Adjustable DC Offset Null reduced performance. It is suitable for communications
n High Input P1dB: 13.1dBm at 900MHz receivers where an RF signal is directly converted into I
n Image Rejection: 45dB at 900MHz and Q baseband signals with bandwidth of 530MHz or
n Noise Figure: 9.9dB at 450MHz higher. The LTC5584 incorporates balanced I and Q mix-
10dB at 900MHz ers, LO buffer amplifiers and a precision, high frequency
n Conversion Gain: 5.4dB at 450MHz quadrature phase shifter. In addition, the LTC5584 provides
5.7dB at 900MHz four analog control voltage interface pins for IIP2 and DC
n Shutdown Mode offset correction, greatly simplifying system calibration.
n Operating Temperature Range (T ): –40°C to 105°C
C The high linearity of the LTC5584 provides excellent spur-
n 24-Lead 4mm × 4mm QFN Package
free dynamic range for the receiver. This direct conversion
demodulator can eliminate the need for intermediate fre-
Applications quency (IF) signal processing, as well as the corresponding
n LTE/W-CDMA/TD-SCDMA Base Station Receivers requirements for image filtering and IF filtering. These
n Wideband DPD Receivers I/Q outputs can interface directly to channel-select filters
n Point-To-Point Broadband Radios (LPFs) or to baseband amplifiers.
n High Linearity Direct Conversion I/Q Receivers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n Image Rejection Receivers

Typical Application
Direct Conversion Receiver with IIP2 and DC Offset Calibration
5V
BPF LNA BPF RF VCC LPF VGA
INPUT RF+ I+
I– A/D IIP2 vs IP2I, IP2Q Trim Voltage
130
RF– I, –40°C Q, –40°C fRF = 450MHz
I, 25°C Q, 25°C
D/A 120 I, 85°C Q, 85°C
IP2 ADJUST I, 105°C Q, 105°C
IP2 AND DC 110
OFFSET CAL DC OFFSET

D/A 100
IIP2 (dBm)

LO 0°
LO INPUT LTC5584 90
90°
D/A 80
DC OFFSET
IP2 AND DC 70
OFFSET CAL IP2 ADJUST

D/A 60

LPF VGA 50
Q+ 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ENABLE EN IP2I, IP2Q (V)
Q– A/D
5584 TA01b

5584 TA01a

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LTC5584
Absolute Maximum Ratings Pin Configuration
(Note 1)
VCC Supply Voltage.................................... –0.3V to 5.5V TOP VIEW

CMI
REF
VCAP Voltage..................................................VCC ±0.05V

Q+
Q–
I+
I–
I–, I+, Q+, Q –, CMI, CMQ Voltage.........2.5V to VCC + 0.3V
24 23 22 21 20 19

IP2Q 1 18 CMQ
Voltage on Any Other Pin..................–0.3V to VCC + 0.3V
DCOQ 2 17 VCAP
LO+, LO –, RF+, RF – Input Power............................20dBm DCOI 3 16 LO–
25
RF+, RF – Input DC Voltage......................... –0.3V to 2.7V IP2I 4 GND 15 LO+
Maximum Junction Temperature (TJMAX).............. 150°C RF +
5 14 GND
Operating Temperature Range (TC) RF– 6 13 GND

(Note 3)................................................... –40°C to 105°C 7 8 9 10 11 12

Storage Temperature Range................... –65°C to 150°C

EN
GND
VBIAS
VCC
EDC
EIP2
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 150°C, θJC = 7°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC5584IUF#PBF LTC5584IUF#TRPBF 5584 24-Lead (4mm x 4mm) Plastic QFN –40°C to 105°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

Electrical Characteristics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fRF(RANGE) RF Input Frequency Range (Note 12) 30 to 1400 MHz
fLO(RANGE) LO Input Frequency Range (Note 12) 30 to 1400 MHz
PLO(RANGE) LO Input Power Range (Note 12) 0 to 10 dBm
fRF1 = 140MHz, fRF2 = 141MHz, fLO = 130MHz, L6 = 68nH, C19 = 8.0pF, L5 = 82nH
fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 95 to 190 MHz
fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 105 to 180 MHz
GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.7 dB
NF Noise Figure Double-Side Band (Note 4) 9.9 dB
NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 15.5 dB
IIP3 Input 3rd Order Intercept 33 dBm
IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 70 dBm
IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm
P1dB Input 1dB Compression 12 dBm
DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 1.5 mV
∆G I/Q Gain Mismatch 0.02 dB
∆φ I/Q Phase Mismatch 0.2 Deg

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 LTC5584
Electrical Characteristics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IRR Image Rejection Ratio (Note 10) 53 dB
LO-RF LO to RF Leakage –85 dBm
RF-LO RF to LO Isolation 74 dB
fRF1 = 450MHz, fRF2 = 451MHz, fLO = 440MHz, L6 = 15nH, C19 = 1.0pF, L5 = 12nH, C14 = 4.0pF
fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 300 to 600 MHz
fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 310 to 590 MHz
GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.4 dB
NF Noise Figure Double-Side Band (Note 4) 9.9 dB
NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 13.6 dB
IIP3 Input 3rd Order Intercept 31 dBm
IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 70 dBm
IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm
P1dB Input 1dB Compression 12.6 dBm
DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 2 mV
∆G I/Q Gain Mismatch 0.02 dB
∆φ I/Q Phase Mismatch 0.25 Deg
IRR Image Rejection Ratio (Note 10) 52 dB
LO-RF LO to RF Leakage –80 dBm
RF-LO RF to LO Isolation 70 dB
fRF1 = 900MHz, fRF2 = 901MHz, fLO = 940MHz, C17 = 1.5pF, L6 = 5.6nH, C13 = 2.2pF, L5 = 3.9nH
fRF(MATCH) RF Input Frequency Range Return Loss > 10dB 630 to 1200 MHz
fLO(MATCH) LO Input Frequency Range Return Loss > 10dB 470 to 1100 MHz
GV Voltage Conversion Gain Loaded with 100Ω Pull-Up (Note 8) 5.7 dB
NF Noise Figure Double-Side Band (Note 4) 10 dB
NFBLOCKING Noise Figure Under Blocking Conditions Double-Side Band, PRF = 0dBm (Note 7) 14.7 dB
IIP3 Input 3rd Order Intercept 28 dBm
IIP2 Input 2nd Order Intercept Unadjusted, EIP2 = 0V 65 dBm
IIP2OPT Optimized Input 2nd Order Intercept EIP2 = 5V, IP2I, IP2Q Adjusted for Minimum IM2 80 dBm
P1dB Input 1dB Compression 13.1 dBm
DCOFFSET DC Offset at I/Q Outputs Unadjusted, EDC = 0V (Note 13) 2.5 mV
∆G I/Q Gain Mismatch 0.01 dB
∆φ I/Q Phase Mismatch 0.7 Deg
IRR Image Rejection Ratio (Note 10) 45 dB
LO-RF LO to RF Leakage –75 dBm
RF-LO RF to LO Isolation 65 dB
Power Supply and Other Parameters
VCC Supply Voltage 4.75 5.0 5.25 V
ICC Supply Current EDC = EIP2 = VCC 180 200 220 mA
ICC(LOW) Supply Current EDC = EIP2 = 0V 174 194 214 mA
ICC(OFF) Shutdown Current EN < 0.3V 11 900 μA
tON Turn-On Time EN Transition from Logic Low to High (Note 14) 0.2 µs
tOFF Turn-Off Time EN Transition from Logic High to Low (Note 15) 0.8 µs
VEH EN, EDC, EIP2 Input High Voltage (On) 2.0 V
VEL EN, EDC, EIP2 Input Low Voltage (Off) 0.3 V

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LTC5584
Electrical Characteristics TC = 25°C, VCC = 5V, EN = 5V, EDC = EIP2 = 0V, REF = IP2I = IP2Q = DCOI = DCOQ
= 0.5V, PRF = –5dBm (–5dBm/tone for 2-tone IIP2 and IIP3 tests), PLO = 6dBm, unless otherwise noted. (Notes 2, 3, 5, 6, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IENH EN Pin Input Current EN = 5.0V 52 μA
IEDCH EDC Pin Input Current EDC = 5.0V 33 μA
IEIP2H EIP2 Pin Input Current EIP2 = 5.0V 50 μA
VREF REF Pin Voltage With REF Pin Unloaded 0.5 V
VREF(RANGE) REF Pin Voltage Range When Driven with External Source 0.4 to 0.7 V
ZREF REF Input Impedance (Note 11) 2||1 kΩ||pF
DCOI, DCOQ, IP2I, IP2Q Pin Voltage Unloaded 0.5 V
DCOI, DCOQ, IP2I, IP2Q Voltage Range When Driven with External Source 0 to 2VREF V
DCOI, DCOQ, IP2I, IP2Q Impedance (Note 11) 8||1 kΩ||pF
DCOI, DCOQ, IP2I, IP2Q Settling Time For Step Input, Output with 90% of Final Value 20 ns
DC Offset Adjustment Range DCOI, DCOQ Swept from 0V to 1V, EDC = 5V ±20 mV
DC Offset Drift Over Temperature Unadjusted, EDC = 0V 20 μV/°C
VCM I+, I–, Q+, Q– Common Mode Voltage VCC – 1.5 V
ZOUT I+, I–, Q+, Q– Output Impedance Single Ended 100||6 Ω||pF
BWBB I+, I–, Q+, Q– Output Bandwidth 100Ω External Pull-Up, –3dB Corner Frequency 530 MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Tests are performed with the test circuit of Figure 1.
Note 3: The LTC5584 is guaranteed to be functional over the –40°C to
105°C case temperature operating range.
Note 4: DSB noise figure is measured at the baseband frequency of 15MHz
with a small-signal noise source without any filtering on the RF input and
no other RF signal applied.
Note 5: Performance at the RF frequencies listed is measured with external
RF and LO impedance matching, as shown in the table of Figure 1.
Note 6: The complementary outputs (I+, I– and Q+, Q–) are combined
using a 180° phase-shift combiner.
Note 7: Noise figure under blocking conditions (NFBLOCKING) is measured
at an output noise frequency of 60MHz with an RF input blocking signal at
fLO + 1MHz. Both RF and LO input signals are appropriately filtered, as well
as the baseband output. NFBLOCKING measured at fLO of 160MHz, 460MHz
and 885MHz.
Note 8: Voltage conversion gain is calculated from the average measured
power conversion gain of the I and Q outputs using the test circuit shown
in Figure 1. Power conversion gain is measured with a 100Ω differential
load impedance on the I and Q outputs.
Note 9: Baseband outputs have a 100Ω external pull-up resistor to VCC as
shown in the test circuit shown in Figure 1.
Note 10: Image rejection is calculated from the measured gain error and
phase error using the method listed in the appendix.
Note 11: The DCOI, DCOQ, IP2I, IP2Q pins have an 8k internal resistor to
ground. The REF pin has a 2k internal resistor to ground. If unconnected,
these pins will float up to 500mV through internal current sources. A low
output resistance voltage source is recommended for driving these pins.
Note 12: This is the recommended operating range, operation outside the
listed range is possible with degraded performance to some parameters.
Note 13: DC offset measured differentially between I+ and I– and between
Q+ and Q–. The reported value is the mean of the absolute values of the
characterization data distribution.
Note 14: Baseband amplitude is within 10% of final value.
Note 15: Baseband amplitude is at least 30dB down from its on state.

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DC Performance Characteristics EN = 5V, EDC = 0V and EIP2 = 0V. Test circuit shown in Figure 1
Supply Current vs Supply Voltage REF Voltage vs Temperature
260 550
TC = –40°C VCC = 4.75V
250 TC = 25°C 545
VCC = 5V
240 TC = 85°C 540 VCC = 5.25V
TC = 105°C
SUPPLY CURRENT (mA)

230 535

REF VOLTAGE (mV)

220 530
210 525
200 520
190 515
180 510
170 505
160 500
4.75 5 5.25 –40 –20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C)
5585 G01 5584 G02

Typical Performance Characteristics 140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.

IIP3 and P1dB vs Supply Voltage

IIP3 and P1dB vs Temperature (TC) (VCC) IIP3 vs LO Power
50 50 50
I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C
I, 25°C Q, 25°C I, 5.0V Q, 5.0V I, 6dBm Q, 6dBm
45 I, 85°C Q, 85°C 45 I, 5.25V Q, 5.25V 45 I, 10dBm Q, 10dBm
I, 105°C Q, 105°C
40 40 40
IIP3 IIP3
IIP3, P1dB (dBm)

IIP3, P1dB (dBm)

35 35 35
IIP3 (dBm)

30 30 30

25 25 25

20 20 20

15 15 P1dB 15
P1dB
10 10 10
80 100 120 140 160 180 200 80 100 120 140 160 180 200 80 100 120 140 160 180 200
LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G03 5584 G04 5584 G05

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LTC5584
Typical Performance Characteristics 140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.

Uncalibrated IIP2 vs Temperature

2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power
50 130 130
TC = 25°C Q I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
fRF1 = 140MHz I I, 25°C Q, 25°C I, 6dBm Q, 6dBm
120 I, 85°C Q, 85°C 120 I, 10dBm Q, 10dBm
45 fRF2 = 141MHz
fLO = 130MHz I, 105°C Q, 105°C
110 110
40

IIP2 (dBm)

IIP2 (dBm)
IIP3 (dBm)

100 100
35
90 90
30
80 80

25 70 70

20 60 60
–10 –8 –6 –4 –2 0 2 4 80 100 120 140 160 180 200 80 100 120 140 160 180 200
RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G06 5584 G07 5584 G08

2x2 Half-IF IIP2

IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing
130 110 110
I, –40°C Q, –40°C fRF = 140MHz TC = 25°C I (UNCALIBRATED) TC = 25°C Q
I, 25°C Q, 25°C EIP2 = 5V fRF1 = 140MHz I (NULLED AT 1MHz) fLO = 140MHz I
120 I, 85°C Q, 85°C Q (UNCALIBRATED)
100 fLO = 130MHz 100
I, 105°C Q, 105°C Q (NULLED AT 1MHz)
110
90 90
100
IIP2 (dBm)

IIP2 (dBm)

IIP2 (dBm)

90 80 80

80
70 70
70
60 60
60 ZFSCJ-2-1 ZFSCJ-2-1
BB COMBINER BB COMBINER
50 50 50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1 10 100 1000 1 10 100 1000
IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO SPACING (MHz)
5585 G09 5584 G10 5584 G11

Noise Figure and Conversion Noise Figure and Conversion Noise Figure vs RF Power and
Gain vs Temperature (TC) Gain vs LO Power IP2I, IP2Q Trim Voltage
20 20 20
I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, –20dBm Q, –20dBm
18 I, 25°C Q, 25°C 18 I, 6dBm Q, 6dBm 19 I, 0dBm Q, 0dBm
I, 85°C Q, 85°C I, 10dBm Q, 10dBm
16 I, 105°C Q, 105°C 16 18
DSB NOISE FIGURE (dB)

14 14 17
NF, GAIN (dB)

NF, GAIN (dB)

12 NF 12 16
NF
10 10 15 TC = 25°C
fRF = 160MHz
8 8 14 fLO = 159MHz
GAIN GAIN fNOISE = 60MHz
6 6 13 EIP2 = 5V
4 4 12
2 2 11
0 0 10
80 100 120 140 160 180 200 80 100 120 140 160 180 200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LO FREQUENCY (MHz) LO FREQUENCY (MHz) IP2I, IP2Q TRIM VOLTAGE (V)
5584 G12 5584 G13 5584 G14

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 LTC5584
Typical Performance Characteristics 140MHz application. VCC = 5V, EN = 5V, EDC = 0V,
EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 130MHz, fRF1 = 140MHz, fRF2 = 141MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm,
DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted.
Test circuit with RF and LO ports impedance matched as in Figure 1.

Noise Figure vs RF Input Power DC Offset vs Temperature (TC) DC Offset vs LO Power

24 10 10
PLO = 0dBm I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
23 9 9
PLO = 6dBm I, 25°C Q, 25°C I, 6dBm Q, 6dBm
22 PLO = 10dBm 8 I, 85°C Q, 85°C 8 I, 10dBm Q, 10dBm
21 T = 25°C 7 I, 105°C Q, 105°C 7
C
20 fLO = 159MHz 6 6
DSB NOISE FIGURE (dB)

19 fRF = 160MHz 5 5

DC OFFSET (mV)

DC OFFSET (mV)
18 fNOISE = 60MHz 4 4
17 3 3
16 2 2
15 1 1
14 0 0
13 –1 –1
12 –2 –2
11 –3 –3
10 –4 –4
9 –5 –5
–20 –15 –10 –5 0 5 10 80 100 120 140 160 180 200 80 100 120 140 160 180 200
RF INPUT POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G15 5584 G16 5584 G17

DC Offset vs DCOI, DCOQ Control

Voltage DC Offset Distribution, I-Side DC Offset Distribution, Q-Side
40 90 90
f = 140MHz I, –40°C Q, –40°C TC = –40°C fLO = 100MHz TC = –40°C fLO = 100MHz
35 LO I, 25°C Q, 25°C TC = 25°C
EDC = 5V TC = 25°C
30 I, 85°C Q, 85°C TC = 85°C TC = 85°C
PERCENTAGE DISTRIBUTION (%)

PERCENTAGE DISTRIBUTION (%)

I, 105°C Q, 105°C 40 40
25 TC = 105°C TC = 105°C
20
DC OFFSET (mV)

15 30 30
10
5
0 20 20
–5
–10
10 10
–15
–20
–25 0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 –2.5 –1.5 –0.5 0.5 1.5 2.5 –2.5 –1.5 –0.5 0.5 1.5 2.5
DCOI, DCOQ (V) DC OFFSET (mV) DC OFFSET (mV)
5584 G18 5584 G19 5584 G20

LO to RF Leakage and RF to LO
Isolation Image Rejection vs Temperature
–30 100
L-R, –40°C R-L, –40°C TC = –40°C
L-R, 25°C R-L, 25°C TC = 25°C
–40 L-R, 85°C R-L, 85°C 90
LEAKAGE (dBm), –ISOLATION (dB)

TC = 85°C
L-R, 105°C R-L, 105°C
80 TC = 105°C
IMAGE REJECTION (dB)

–50
70
–60
60
–70
50
–80
40
–90 30

–100 20
80 100 120 140 160 180 200 80 100 120 140 160 180 200
LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G21 5584 G22

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LTC5584
Typical Performance Characteristics 450MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC
Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test
circuit with RF and LO ports impedance matched as in Figure 1.

IIP3 and P1dB vs Supply Voltage

IIP3 and P1dB vs Temperature (TC) (VCC) IIP3 vs LO Power
50 50 50
I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C
I, 25°C Q, 25°C I, 5.0V Q, 5.0V I, 6dBm Q, 6dBm
45 I, 85°C Q, 85°C 45 45
I, 5.25V Q, 5.25V I, 10dBm Q, 10dBm
I, 105°C Q, 105°C
40 40 40

IIP3, P1dB (dBm)

IIP3, P1dB (dBm)

35 35 IIP3 35

IIP3 (dBm)
IIP3
30 30 30

25 25 25

20 20 20

15 P1dB 15 P1dB 15

10 10 10
200 300 400 500 600 700 200 300 400 500 600 700 200 300 400 500 600 700
LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G23 5584 G24 5584 G25

Uncalibrated IIP2 vs Temperature

2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power
50 130 130
TC = 25°C Q I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
fRF1 = 450MHz I I, 25°C Q, 25°C I, 6dBm Q, 6dBm
45 fRF2 = 451MHz 120 I, 85°C Q, 85°C 120 I, 10dBm Q, 10dBm
fLO = 440MHz I, 105°C Q, 105°C
110 110
40
IIP2 (dBm)

IIP2 (dBm)
IIP3 (dBm)

100 100
35
90 90
30
80 80

25 70 70

20 60 60
–10 –8 –6 –4 –2 0 2 4 200 300 400 500 600 700 200 300 400 500 600 700
RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G26 5584 G27 5584 G28

2x2 Half-IF IIP2

IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing
130 110 110
I, –40°C Q, –40°C fRF = 450MHz TC = 25°C I (UNCALIBRATED) TC = 25°C Q
I, 25°C Q, 25°C EIP2 = 5V fRF1 = 450MHz I (NULLED AT 1MHz) fLO = 450MHz I
120 I, 85°C Q, 85°C Q (UNCALIBRATED)
100 fLO = 440MHz 100
I, 105°C Q, 105°C Q (NULLED AT 1MHz)
110
90 90
100
IIP2 (dBm)

IIP2 (dBm)

IIP2 (dBm)

90 80 80

80
70 70
70
60 60
60 ZFSCJ-2-1 ZFSCJ-2-1
BB COMBINER BB COMBINER
50 50 50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1 10 100 1000 1 10 100 1000
IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO SPACING (MHz)
5584 G29 5584 G30 5584 G31

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 LTC5584
Typical Performance Characteristics 450MHz application. VCC = 5V, EN = 5V, EDC = 0V,
REF = 0.5V, EIP2 = 0V, TC = 25°C, PLO = 6dBm, fLO = 440MHz, fRF1 = 450MHz, fRF2 = 451MHz, fBB = 10MHz, PRF1 = PRF2 = –5dBm, DC
Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement unless otherwise noted. Test
circuit with RF and LO ports impedance matched as in Figure 1.

Noise Figure and Conversion Noise Figure and Conversion

Noise Figure vs RF Input Power Gain vs Temperature (TC) Gain vs LO Power
20 20
23 PLO = 0dBm I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
PLO = 6dBm 18 I, 25°C Q, 25°C 18 I, 6dBm Q, 6dBm
PLO = 10dBm I, 85°C Q, 85°C I, 10dBm Q, 10dBm
21 TC = 25°C 16 I, 105°C Q, 105°C 16
DSB NOISE FIGURE (dB)

fLO = 460MHz 14 14
19 fRF = 461MHz

NF, GAIN (dB)

NF, GAIN (dB)
fNOISE = 60MHz 12 NF 12
17 NF
10 10
15 8 8
GAIN GAIN
6 6
13
4 4
11
2 2
9 0 0
–20 –15 –10 –5 0 5 10 200 300 400 500 600 700 200 300 400 500 600 700
RF INPUT POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G32 5584 G33 5584 G34

DC Offset vs DCOI, DCOQ Control

DC Offset vs Temperature (TC) Voltage DC Offset vs LO Power
10.0 40 10.0
I, –40°C Q, –40°C I, –40°C Q, –40°C fLO = 450MHz I, 0dBm Q, 0dBm TC = 25°C
35 I, 25°C Q, 25°C
I, 25°C Q, 25°C EDC = 5V I, 6dBm Q, 6dBm
7.5 I, 85°C Q, 85°C 30 I, 85°C Q, 85°C 7.5 I, 10dBm Q, 10dBm
I, 105°C Q, 105°C 25 I, 105°C Q, 105°C

5.0 20 5.0
DC OFFSET (mV)

DC OFFSET (mV)
DC OFFSET (mV)

15
10
2.5 2.5
5
0
0 –5 0
–10
–2.5 –15 –2.5
–20
–5.0 –25 –5.0
200 300 400 500 600 700 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 200 300 400 500 600 700
LO FREQUENCY (MHz) DCOI, DCOQ (V) LO FREQUENCY (MHz)
5584 G35 5584 G36 5584 G37

LO to RF Leakage and RF to LO
Isolation Image Rejection vs Temperature
–30 100
L-R, –40°C R-L, –40°C TC = –40°C
L-R, 25°C R-L, 25°C TC = 25°C
–40 L-R, 85°C R-L, 85°C 90
LEAKAGE (dBm), –ISOLATION (dB)

TC = 85°C
L-R, 105°C R-L, 105°C
80 TC = 105°C
IMAGE REJECTION (dB)

–50
70
–60
60
–70
50
–80
40
–90 30

–100 20
200 300 400 500 600 700 200 300 400 500 600 700
LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G38 5584 G39

5584f

9
LTC5584
Typical Performance Characteristics 900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

IIP3 and P1dB vs Supply Voltage

IIP3 and P1dB vs Temperature (TC) (VCC) IIP3 vs LO Power
50 50 50
I, –40°C Q, –40°C I, 4.75V Q, 4.75V TC = 25°C I, 0dBm Q, 0dBm TC = 25°C
I, 25°C Q, 25°C I, 5.0V Q, 5.0V I, 6dBm Q, 6dBm
45 I, 85°C Q, 85°C 45 45
I, 5.25V Q, 5.25V I, 10dBm Q, 10dBm
I, 105°C Q, 105°C
40 40 40

IIP3, P1dB (dBm)

IIP3, P1dB (dBm)

35 35 35

IIP3 (dBm)
IIP3 IIP3
30 30 30

25 25 25

20 20 20

15 P1dB 15 P1dB 15

10 10 10
400 600 800 1000 1200 1400 400 600 800 1000 1200 1400 400 600 800 1000 1200 1400
LO FREQUENCY (MHz) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G40 5584 G41 5584 G42

Uncalibrated IIP2 vs Temperature

2-Tone IIP3 vs RF Power (TC) Uncalibrated IIP2 vs LO Power
50 120 120
TC = 25°C Q I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
fRF1 = 900MHz I I, 25°C Q, 25°C I, 6dBm Q, 6dBm
45 fRF2 = 901MHz 110 I, 85°C Q, 85°C 110 I, 10dBm Q, 10dBm
fLO = 890MHz I, 105°C Q, 105°C
100 100
40
IIP3 (dBm)

IIP2 (dBm)
IIP2 (dBm)

90 90
35
80 80
30
70 70

25 60 60

20 50 50
–10 –8 –6 –4 –2 0 2 4 400 600 800 1000 1200 1400 400 600 800 1000 1200 1400
RF POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G43 5584 G44 5584 G45

2x2 Half-IF IIP2

IIP2 vs IP2I, IP2Q Trim Voltage IIP2 vs RF Tone Spacing vs RF to LO Tone Spacing
130 110 110
I, –40°C Q, –40°C fRF = 900MHz TC = 25°C I (UNCALIBRATED) TC = 25°C Q
I, 25°C Q, 25°C EIP2 = 5V fRF1 = 900MHz I (NULLED AT 1MHz) fLO = 900MHz I
120 I, 85°C Q, 85°C Q (UNCALIBRATED)
100 fLO = 890MHz 100
I, 105°C Q, 105°C Q (NULLED AT 1MHz)
110
90 90
100
IIP2 (dBm)

IIP2 (dBm)

IIP2 (dBm)

90 80 80

80
70 70
70
60 60
60 ZFSCJ-2-1 ZFSCJ-2-1
BB COMBINER BB COMBINER
50 50 50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1 10 100 1000 1 10 100 1000
IP2I, IP2Q (V) RF TONE SPACING (MHz) RF TO LO SPACING (MHz)
5585 G46 5584 G47 5584 G48

5584f

10
 LTC5584
Typical Performance Characteristics 900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

Noise Figure and Conversion Noise Figure and Conversion

Noise Figure vs RF Input Power Gain vs Temperature (TC) Gain vs LO Power
20 20
23 PLO = 0dBm I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C
PLO = 6dBm 18 I, 25°C Q, 25°C 18 I, 6dBm Q, 6dBm
PLO = 10dBm I, 85°C Q, 85°C I, 10dBm Q, 10dBm
21 TC = 25°C 16 I, 105°C Q, 105°C 16
DSB NOISE FIGURE (dB)

fLO = 884MHz 14 14
19 fRF = 885MHz

NF, GAIN (dB)

NF
NF, GAIN (dB)
fNOISE = 60MHz 12 12
NF
17
10 10
15 8 8
GAIN GAIN
6 6
13
4 4
11
2 2
9 0 0
–20 –15 –10 –5 0 5 10 400 600 800 1000 1200 1400 400 600 800 1000 1200 1400
RF INPUT POWER (dBm) LO FREQUENCY (MHz) LO FREQUENCY (MHz)
5584 G49 5584 G50 5584 G51

DC Offset vs DCOI, DCOQ Control

DC Offset vs Temperature (TC) DC Offset vs LO Power Voltage
10.0 10.0 40
I, –40°C Q, –40°C I, 0dBm Q, 0dBm TC = 25°C I, –40°C Q, –40°C fLO = 900MHz
35 I, 25°C Q, 25°C
I, 25°C Q, 25°C I, 6dBm Q, 6dBm EDC = 5V
7.5 I, 85°C Q, 85°C 7.5 I, 10dBm Q, 10dBm 30 I, 85°C Q, 85°C
I, 105°C Q, 105°C 25 I, 105°C Q, 105°C
20
5.0 5.0
DC OFFSET (mV)
DC OFFSET (mV)

DC OFFSET (mV)

15
10
2.5 2.5
5
0
0 0 –5
–10
–2.5 –2.5 –15
–20
–5.0 –5.0 –25
400 600 800 1000 1200 1400 400 600 800 1000 1200 1400 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LO FREQUENCY (MHz) LO FREQUENCY (MHz) DCOI, DCOQ (V)
5584 G52 5584 G53 5584 G54

LO to RF Leakage and RF to LO
Isolation Image Rejection vs Temperature Conversion Gain Distribution
–30 100 70
L-R, –40°C R-L, –40°C TC = –40°C TC = –40°C
L-R, 25°C R-L, 25°C TC = 25°C TC = 25°C
–40 L-R, 85°C R-L, 85°C 90 60
LEAKAGE (dBm), –ISOLATION (dB)

TC = 85°C TC = 85°C
PERCENTAGE DISTRIBUTION (%)

L-R, 105°C R-L, 105°C TC = 105°C

80 TC = 105°C
IMAGE REJECTION (dB)

–50 50
70
–60 40
60
–70 30
50
–80 20
40
–90 30 10

–100 20 0
400 600 800 1000 1200 1400 400 600 800 1000 1200 1400 4.7 4.9 5.1 5.3 5.5 5.7 5.9
LO FREQUENCY (MHz) LO FREQUENCY (MHz) CONVERSION GAIN (dB)
5584 G55 5584 G56 5584 G57

5584f

11
LTC5584
Typical Performance Characteristics 900MHz application. VCC = 5V, EN = 5V,
EDC = 0V, EIP2 = 0V, REF = 0.5V, TC = 25°C, PLO = 6dBm, fLO = 890MHz, fRF1 = 900MHz, fRF2 = 901MHz, fBB = 10MHz,
PRF1 = PRF2 = –5dBm, DC Blocks and Mini-Circuits PSCJ-2-1 180° combiner at baseband outputs de-embedded from measurement
unless otherwise noted. Test circuit with RF and LO ports impedance matched as in Figure 1.

DSB Noise Figure Distribution,

IIP3 Distribution, I-Side IIP3 Distribution, Q-Side I-Side
80 80 70
TC = –40°C TC = –40°C TC = –40°C
70 TC = 25°C 70 TC = 25°C TC = 25°C
60 TC = 85°C
PERCENTAGE DISTRIBUTION (%)

PERCENTAGE DISTRIBUTION (%)

TC = 85°C TC = 85°C

PERCENTAGE DISTRIBUTION (%)

TC = 105°C TC = 105°C TC = 105°C
60 60
50
50 50
40
40 40
30
30 30
20
20 20

10 10 10

0 0 0
26.5 27 27.5 28 28.5 29 29.5 30 27 27.5 28 28.5 29 29.5 30 9 9.4 9.8 10.2 10.6 11
IIP3 (dBm) IIP3 (dBm) DSB NOISE FIGURE (dB)
5584 G58 5584 G59 5584 G60

DSB Noise Figure Distribution,

Q-Side IIP2 Distribution, I-Side IIP2 Distribution, Q-Side
70 100 100
TC = –40°C TC = 85°C TC = –40°C TC = –40°C
TC = 25°C TC = 105°C 90 TC = 25°C 90 TC = 25°C
60 TC = 85°C TC = 85°C

PERCENTAGE DISTRIBUTION (%)

PERCENTAGE DISTRIBUTION (%)

PERCENTAGE DISTRIBUTION (%)

80 80
TC = 105°C TC = 105°C
50 70 70
60 60
40
50 50
30 40
40

20 30 30
20 20
10
10 10
0 0 0
9 9.4 9.8 10.2 10.6 69 69.5 70 70.5 71 71.5 72 64.5 65.5 66.5 67.5 68.5 69.5
DSB NOISE FIGURE (dB) IIP2 (dBm) IIP2 (dBm)
5584 G61 5584 G62 5584 G63

Image Rejection Distribution

Gain Error Distribution Phase Error Distribution (Note 10)
70 70 50
TC = –40°C TC = –40°C TC = –40°C
TC = 25°C TC = 25°C TC = 25°C
60 TC = 85°C 60 TC = 85°C
PERCENTAGE DISTRIBUTION (%)

TC = 85°C
PERCENTAGE DISTRIBUTION (%)
PERCENTAGE DISTRIBUTION (%)

TC = 105°C 40 TC = 105°C
TC = 105°C
50 50
30
40 40

30 30
20
20 20
10
10 10

0 0 0
–0.04 –0.02 0 0.02 0.04 0.06 0.4 0.5 0.6 0.7 0.8 0.9 1.0 41 42 43 44 45 46 47 48
GAIN ERROR (dB) PHASE ERROR (DEGREES) IMAGE REJECTION (dB)
5584 G64 5584 G65 5584 G66

5584f

12

Pin Functions
IP2Q, IP2I (Pin 1, Pin 4): IIP2 Adjustment Analog Control
Voltage Input for Q and I Channel. A decoupling capacitor
is recommended on this pin. A low output resistance volt-
age source is recommended for driving these pins. These
pins should be left floating if unused.
DCOQ, DCOI (Pin 2, Pin 3): DC Offset Analog Control
Voltage Input for Q and I Channel. A decoupling capaci-
tor is recommended on this pin. A low output resistance
voltage source is recommended for driving these pins.
These pins should be left floating if unused.
RF+, RF– (Pin 5, Pin 6): RF Differential Inputs. An external
balun transformer with matching is used to obtain good
return loss across the RF input frequency range. The RF
pin should be DC-blocked with a 0.01µF coupling capacitor.
GND (Pins 8, 13, 14, Exposed Pad Pin 25): Ground.
These pins must be soldered to the RF ground plane
on the circuit board. The backside exposed pad ground
connection should have a low inductance connection and
good thermal contact to the printed circuit board ground
plane using many through-hole vias. See Figures 2 and 3.
EN (Pin 7): Enable Pin. When the voltage on the EN pin
is a logic high, the chip is completely turned on; the chip
is completely turned off for a logic low. An internal 200k
pull-down resistor ensures the chip remains disabled if
there is no connection to the pin (open-circuit condition).
VBIAS (Pin 9): This pin can be pulled to ground through
a resistor to lower the current consumption of the chip.
See Applications Information.
VCC (Pin 10): Positive Supply Pin. This pin should be
bypassed with shunt 0.01µF and 1µF capacitors.
LTC5584
EDC (Pin 11): DC Offset Adjustment Mode Enable Pin.
When the voltage on the EDC pin is a logic high, the DC
offset control circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
EIP2 (Pin 12): IP2 Offset Adjustment Mode Enable Pin.
When the voltage on the EIP2 pin is a logic high, the IP2
adjustment circuitry is enabled. The circuitry is disabled
for a logic low. An internal 200k pull-down resistor ensures
the circuitry remains disabled if there is no connection to
the pin (open-circuit condition).
LO+,LO– (Pin 15, Pin 16): LO Inputs. External matching
is required to obtain good return loss across the LO input
frequency range. Can be driven single ended or differen-
tially with an external transformer. The LO pins should be
DC-blocked with 0.01µF coupling capacitors.
VCAP, CMQ, CMI (Pin 17, Pin 18, Pin 19): Common Mode
Bypass Capacitor Pins. It is recommended that CMI and
CMQ be connected to VCAP through 0.1µF capacitors.
Nothing else should be connected to VCAP since it is con-
nected to VCC inside the chip.
I+, I–, Q+, Q– (Pin 23, Pin 22, Pin 21, Pin 20): Differential
Baseband Output Pins for the I Channel and Q Channel.
The DC bias point is VCC – 1.5V for each pin. These pins
must have an external 100Ω or an inductor pull-up to VCC.
REF (Pin 24): Voltage Reference Input for Analog Control
Voltage Pins. A decoupling capacitor is recommended
on this pin. A low output resistance voltage source is
recommended for driving this pin. This pin should be left
floating if unused.
5584f
13
LTC5584
Block Diagram
10 17
VCC VCAP CMI
19
RF+ I+
5 23
RF– I–
6 22

DCOI
IP2 AND DC 3
OFFSET CAL IP2I
4
EDC
LO+ 11
15 0°
EIP2
LO– 12
16 90° REF
24
IP2Q
IP2 AND DC 1
OFFSET CAL DCOQ
2

VBIAS
9
Q+
EN 21
7 BIAS Q–
20
CMQ
18
EXPOSED
GND GND GND PAD
8 13 14 25 5584 BD

5584f

14
 LTC5584
Test Circuit
RF
0.015" GND
0.062"
DC
0.015"
GND
NELCO N4000-13

C29 C21 C22 C30

R9 R11 R13 R14

I– OUT Q+ OUT

I+ OUT Q– OUT
C10
REF
C31 24 23 22 21 20 19
C11
REF
I+
I–
Q+
Q–
CMI
1 18
IP2Q IP2Q CMQ
2 17
DCOQ DCOQ VCAP
3 16
DCOI DCOI LO–
4 LTC5584IUF 15 C38
IP2I IP2I LO+ T1 L5
C32 C33 C34 C35 5 + 14 3 4
RF GND LO
6 13 C39 2
6 C13 C14
RF– GND
C40 25 1 • •
VBIAS

GND
GND

EIP2
EDC
VCC

L6 T2
EN

6 • • 1
RF
2 C41 7 8 9 10 11 12
C17 C19 4 EIP2
3 EDC
VCC
EN 4.75V TO 5.25V
C15 C16
5584 F01

RF MATCH LO MATCH
FREQUENCY RANGE C17 L6 C19 C13 L5 C14
140MHz 68nH 8.0pF 82nH
450MHz 15nH 1.0pF 12nH 4.0pF
900MHz 1.5pF 5.6nH 2.2pF 3.9nH

REF DES VALUE SIZE VENDOR REF DES VALUE SIZE VENDOR
C10, C11, C31-C35 0.1μF 0402 Murata L5, L6 See Table 0402 Murata
C15, C38-C41 0.01µF 0402 Murata R9, R11, R13, R14 100Ω 0402 Vishay
C13, C14, C17, C19 See Table 0402 Murata T1, T2 1:1 AT224-1 Mini-Circuits
TC1-1-13M+
C16, C21, C22, C29, C30 1μF 0402 Murata

Figure 1. Test Circuit Schematic

5584f

15
LTC5584
Test Circuit
Figure 2. Component Side of Evaluation Board
Applications Information
The LTC5584 is an IQ demodulator designed for high
dynamic range receiver applications. It consists of RF
transconductance amplifiers, I/Q mixers, quadrature LO
amplifiers, IIP2 and DC offset correction circuitry, and
bias circuitry.
Operation
As shown in the Block Diagram for the LTC5584, the RF
signal is applied to the inputs of the RF transconductor
V-to-I converters and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated by a precision 90° phase shifter. The
demodulated I/Q signals are lowpass filtered on-chip with
a –3dB bandwidth of 530MHz. The differential outputs of
the I-channel and Q-channel are well matched in amplitude
and their phases are 90° apart.
16
Figure 3. Bottom Side of Evaluation Board
RF Input Port
Figure 4 shows the demodulator’s differential RF input
which consists of high linearity transconductance ampli-
fiers (V-I converters). External DC voltage should not be
applied to the RF input pins. DC current flowing into the
pins may cause damage to the transconductance amplifiers.
Series DC blocking capacitors should be used to couple
the RF input pins to the RF signal source.
The RF input port can be externally matched over the
operating frequency range with simple L-C matching.
An input return loss greater than 10dB can be obtained
over a fractional bandwidth of greater than 66% with
this method. Figure 5 shows the RF input return loss for
various matching component values. Table 1 shows the
differential and single-ended S parameters for the RF input
without using any external matching components. The
input transmission line length and balun are de-embedded
from the measurement.
5584f
 LTC5584
Applications Information
T2
MINI-CIRCUITS C40 LTC5584 Larger bandwidths can be obtained by using more ele-
RF L6 TC1-1-13M+
6 •
0.01µF BIAS
RF+
ments. For example Figure 6 shows an L-C match having
• 1
INPUT
(MATCHED)
2 a bandwidth of about 98% where return loss is >10dB.
C17 C19 4
3 RF–
Figure 7 shows the RF input return loss for the wide
bandwidth match.
C41
0.01µF
0

–5
5584 F04

GND

RETURN LOSS (dB)

–10
Figure 4: Simplified Schematic of the RF Interface
–15

Table 1. RF Input S Parameters –20 TC = 25°C

FREQUENCY S11 (DIFFERENTIAL) S11 (SINGLE ENDED) L6 = 68nH, C19 = 8.0pF

–25 L6 = 15nH, C19 = 1.0pF
(MHz) MAG ANGLE(°) MAG ANGLE(°) C17 = 1.5pF, L6 = 5.6nH
NO MATCHING
10 0.5657 –2.416 0.3253 –5.287 –30
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
20 0.55 –2.674 0.3055 –5.761 FREQUENCY (GHz)
40 0.5391 –2.288 0.2938 –4.499 5584 F05

80 0.5349 –2.268 0.2984 –4.517

Figure 5. RF Input Return Loss
140 0.5336 –2.946 0.3097 –9.805
200 0.5329 –3.836 0.2989 –16.34 T2
MINI-CIRCUITS C40 LTC5584
300 0.5317 –5.453 0.2732 –21.46 L7 L6 0.01µF BIAS
RF INPUT 5.6nH 7.5nH TC1-1-13M+
6 • • 1 RF+
400 0.5301 –7.128 0.2614 –24.35 650MHz TO
2
950MHz C17 4
450 0.5292 –7.975 0.2583 –25.79 2.7pF
3 RF–
500 0.5282 –8.826 0.2562 –27.29
C41
600 0.5258 –10.54 0.2536 –30.43 0.01µF
700 0.523 –12.25 0.2523 –33.66
800 0.5199 –13.97 0.2517 –36.88
5584 F06
900 0.5164 –15.7 0.2519 –39.97 GND
1000 0.5124 –17.43 0.2529 –42.85
Figure 6. Wide Bandwidth RF Input Match
1100 0.5082 –19.17 0.2556 –45.49
0
1200 0.5035 –20.91 0.2609 –48.02 TC = 25°C
C17 = 2.7pF
1300 0.4985 –22.66 0.2693 –50.73 L6 = 7.5nH
1400 0.4931 –24.42 0.2804 –53.98 –5 L7 = 5.6nH
RETURN LOSS (dB)

1500 0.4873 –26.19 0.2925 –57.96

1600 0.4812 –27.97 0.3035 –62.52 –10
1700 0.4747 –29.77 0.3122 –67.36
1800 0.4678 –31.58 0.3187 –72.19
–15
1900 0.4606 –33.41 0.3235 –76.87
2000 0.453 –35.26 0.3271 –81.36
Note: Differential S parameters measured with 1:1 balun and single- –20
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
ended S parameters measured with 50Ω termination on unused port. FREQUENCY (GHz)
5584 F07

Figure 7. RF Input Return Loss for Wideband Match

5584f

17
LTC5584
Applications Information
Broadband Performance
To get an idea of the broadband performance of the
LTC5584, a 6dB pad can be put on the RF and LO ports,
and the ports can be left unmatched. The measured RF
performance for this configuration is shown in Figures 8,
9, 10 and 11 with the 6dB pad de-embedded. The RF
tone spacing is 1MHz, and fLO is 10MHz lower than fRF.
The conversion gain is lower than under the impedance
matched condition, and correspondingly the P1dB, IIP3,
and NF are higher. As shown, the part can be used at
frequencies outside its specified operating range with
reduced conversion gain and higher NF.
LO Input Port
The demodulator’s LO input interface is shown in Fig-
ure 12. The input consists of a high precision quadrature
phase shifter which generates 0° and 90° phase shifted
LO signals for the LO buffer amplifiers to drive the I/Q
mixers. DC blocking capacitors are required on the LO+
and LO– inputs.
The differential and single-ended LO input S parameters
with the input transmission lines and balun de-embedded
are listed in Table 2.

50 20
I, –40°C Q, –40°C I, –40°C Q, –40°C
I, 25°C Q, 25°C 18 I, 25°C Q, 25°C
45 I, 85°C Q, 85°C I, 85°C Q, 85°C
I, 105°C Q, 105°C 16 I, 105°C Q, 105°C
40
14
IIP3, P1dB (dBm)

35 NF, GAIN (dB) NF

12
IIP3
30 10

25 8
6 GAIN
20
4
P1dB
15
2
10 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz) LO FREQUENCY (GHz)
5584 F08 5584 F10

Figure 8. Broadband IIP3 and IP1dB Figure 10. Broadband NF and Gain

140 100
I, –40°C Q, –40°C TC = –40°C
130 I, 25°C Q, 25°C 90 TC = 25°C
I, 85°C Q, 85°C TC = 85°C
120 I, 105°C Q, 105°C
80 TC = 105°C
IMAGE REJECTION (dB)

110
100 70
IIP2 (dBm)

90 60
80 50
70
40
60
30
50
40 20
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz) LO FREQUENCY (GHz)
5584 F09 5584 F11

Figure 9. Broadband IIP2 Figure 11. Broadband Image Rejection

5584f

18
 LTC5584
Applications Information
VCC

LTC5584
TO IDENTICAL
Q-CHANNEL
MINI-CIRCUITS C39
TC1-1-13M+ 0.01µF
6 • LO+
• 1
LO L5 2
4
INPUT
3 LO–
(MATCHED) C14 C13

C38 PHASE SHIFTER

0.01µF

5584 F12

GND

Figure 12. Simplified Schematic of LO Input Interface with External Matching Components

Table 2. LO Input S-Parameters Figure 13 shows LO input return loss using the Mini-
S11 (DIFFERENTIAL) S11 (SINGLE ENDED) Circuits TC1-1-13M+ 1:1 balun with various matching
FREQUENCY
(MHz) MAG ANGLE(°) MAG ANGLE(°) component values.
10 0.8138 –1.736 0.7869 –1.896 For optimum IIP2 and large-signal NF performance the LO
20 0.8485 –6.615 0.8127 –6.425 inputs should be driven differentially with a 1:1 balun such
40 0.7857 –18.67 0.7382 –16.33 as the Mini-Circuits TC1-1-13M+ or M/A Com ETC1-1-13.
80 0.6608 –25.61 0.6356 –20.1 As shown in Figure 14, the LO input can also be driven
140 0.5968 –33.93 0.5801 –25.43 single-ended from either the LO+ or LO– input. The unused
200 0.5515 –42.29 0.5395 –30.5 port should be DC-blocked and terminated with a 50Ω load.
300 0.4932 –54.56 0.4911 –37.49 Figure 15 compares the uncalibrated IIP2 performance of
400 0.4538 –65.21 0.4606 –43.5 single ended versus differential LO drive.
450 0.4396 –70.18 0.4498 –46.36
500 0.4283 –75.01 0.441 –49.17
0
600 0.412 –84.37 0.4278 –54.67
700 0.4018 –93.45 0.4187 –60.04 –5

800 0.3958 –102.3 0.4124 –65.26

RETURN LOSS (dB)

–10
900 0.3928 –110.9 0.4083 –70.32
1000 0.3921 –119.2 0.4059 –75.21 –15

1100 0.3931 –127.2 0.405 –79.94

–20 TC = 25°C
1200 0.3955 –135 0.4052 –84.52
L5 = 82nH
1300 0.399 –142.4 0.4064 –88.94 –25 L5 = 12nH, C14 = 4.0pF
C13 = 2.2pF, L5 = 3.9nH
1400 0.4035 –149.5 0.4084 –93.23 NO MATCHING
–30
1500 0.4088 –156.3 0.411 –97.37 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1600 0.4148 –162.9 0.4143 –101.4 FREQUENCY (GHz)

1700 0.4213 –169.1 0.4181 –105.3

5584 F13

1800 0.4283 –175.1 0.4224 –109.1 Figure 13. LO Input Return Loss
1900 0.4357 –180.8 0.4271 –112.8
2000 0.4435 –186.2 0.4322 –116.4
Note: Differential S parameters measured with 1:1 balun and single-
ended S parameters measured with 50Ω termination on unused port.

5584f

19
LTC5584
Applications Information
VCC The outputs can be DC coupled or AC coupled to exter-
LTC5584
nal loads. The voltage conversion gain is reduced by the
LO TO IDENTICAL external load by:
INPUT Q-CHANNEL
(MATCHED) C39
0.01µF 1 50Ω 
L5 LO+ 20Log10  +  dB
C14 C13
 2 RPULL-UP ||RLOAD(SE) 
50Ω LO–

PHASE SHIFTER
when the output port is terminated by RLOAD(SE). For in-
C38
0.01µF stance, the gain is reduced by 6dB when each output pin is
connected to a 50Ω load (or 100Ω differentially). The output
GND
5584 F14
should be taken differentially (or by using differential-to-
single-ended conversion) for best RF performance, includ-
Figure 14. Recommended Single-Ended LO Input Configuration ing NF and IIP2. When no external filtering or matching
components are used, the output response is determined
100 by the loading capacitance and the total resistance loading
the outputs. The –3dB corner frequency, fC, is given by
90
the following equation:
80
fC = [2π(RLOAD(SE)||100Ω||RPULL-UP) (6pF)]–1
IIP2 (dBm)

70
Figure 16 shows the actual measured output response
60
with various load resistances.
TC = 25°C
50
SINGLE-ENDED LO, I-SIDE Figure 17 shows a simplified model of the I, Q outputs
DIFFERENTIAL LO, I-SIDE
40
SINGLE-ENDED LO, Q-SIDE with a 100Ω differential load and 100Ω pull-ups. The –1dB
30
DIFFERENTIAL LO, Q-SIDE
bandwidth in this configuration is about 520MHz, or about
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
LO FREQUENCY (GHz)
twice the –1dB bandwidth with no load.
5584 F15
Figure 18 shows a simplified model of the I, Q outputs
Figure 15. Broadband IIP2 with Differential with a L-C matching network for bandwidth extension.
and Single-Ended LO Drive Capacitor CS serves to filter common mode LO switching
noise immediately at the demodulator outputs. Capacitor
I-Channel and Q-Channel Outputs CC in combination with inductor LS is used to peak the
The phase relationship between the I-channel output 7
TC = 25°C
6
signal and the Q-channel output signal is fixed. When the 5
LO input frequency is higher (or lower) than the RF input 4
3
CONVERSION GAIN (dB)

frequency, the Q-channel outputs (Q+, Q–) lead (or lag) 2

1
the I-channel outputs (I+, I–) by 90°. 0
–1
Each of the I-channel and Q-channel outputs is internally –2
–3
connected to VCC through a 100Ω resistor. In order to –4 RLOAD(DIFF) = 100Ω, BW = 850MHz
–5
maintain an output DC bias voltage of VCC – 1.5V, external –6
RLOAD(DIFF) = 200Ω, BW = 630MHz
RLOAD(DIFF) = 400Ω, BW = 530MHz
100Ω pull-up resistors or equivalent 15mA DC current –7
–8
RLOAD(DIFF) = 1kΩ, BW = 460MHz

sources are required. Each single-ended output has an 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
BASEBAND FREQUENCY (GHz)
impedance of 100Ω in parallel with a 6pF internal capaci-
tor. With an external 100Ω pull-up resistor this forms a Figure 16. Conversion Gain Baseband Output Response with
lowpass filter with a –3dB corner frequency at 530MHz. RLOAD(DIFF) = 100Ω, 200Ω, 400Ω and 1k and RPULL-UP = 100Ω
5584f

20

Applications Information
output response to give greater bandwidth of 650MHz. In
this case, capacitor CC was chosen as a common mode
capacitor instead of a differential mode capacitor to increase
rejection of common mode LO switching noise.
When AC output coupling is used, the resulting highpass
filter’s –3dB roll-off frequency, fC, is defined by the R-C
constant of the external AC coupling capacitance, CAC, and
the differential load resistance, RLOAD(DIFF):
fC = [2π • RLOAD(DIFF) • CAC]–1
Care should be taken when the demodulator’s outputs
are DC coupled to the external load to make sure that the
I/Q mixers are biased properly. If the current drain from
the outputs exceeds about 6mA, there can be significant
degradation of the linearity performance. Keeping the com-
mon mode output voltage of the demodulator above 3.15V,
LTC5584
with a 5V supply, will ensure optimum performance. Each
output can sink no more than 30mA when the outputs are
connected to an external load with a DC voltage higher
than VCC – 1.5V.
In order to achieve the best IIP2 performance, it is im-
portant to minimize high frequency coupling among the
baseband outputs, RF port, and LO port. Although it may
increase layout complexity, routing the baseband output
traces on the backside of the PCB can improve uncalibrated
IIP2 performance. Figure 19 shows the alternate layout
having the baseband outputs on the backside of the PCB.

VCC

LTC5584 VCC

PACKAGE
6pF 100Ω 100Ω 6pF PARASITICS RPULL-UP RPULL-UP
1.5nH I+ 100Ω 100Ω

1k 1.5nH I– RLOAD(DIFF)
100Ω
0.2pF 0.2pF
–1dB BW = 520MHz
30mA AC CURRENT 30mA
SOURCE

5584 F17

GND

Figure 17. Simplified Model of the Baseband Output Figure 19. Alternate Layout of PCB with
Baseband Outputs on the Backside

VCC

LTC5584 VCC
CS
PACKAGE 2pF
6pF 100Ω 100Ω 6pF PARASITICS LS CC
RPULL-UP RPULL-UP
10nH 4pF
1.5nF I+ 100Ω 100Ω

1k 1.5nF I– LS RLOAD(DIFF)
6mA MAX DC
10nH 100Ω
0.2pF 0.2pF
CS CC
4pF LOWPASS
AC CURRENT 2pF
30mA DC 30mA DC –1dB BW = 650MHz
SOURCE

5584 F18

GND

Figure 18. Simplified Model of the Baseband Output Showing Bandwidth Extension with External L, C Matching

5584f

21
LTC5584
Applications Information
Analog Control Voltage Pins VCC

Figure 20 shows the equivalent circuit for the DCOI, DCOQ, LTC5584

IP2I, and IP2Q pins. Internal temperature compensated

62.5μA current sources keep these pins biased at a nominal
500mV through 8k resistors. A low impedance voltage 62.5µA
DCOI, DCOQ,
source with a source resistance of less than 200Ω is IP2I, IP2Q
recommended to drive these pins. 8k

As shown in Figure 21, the REF pin is similar to the DCOI

pin, but the bias current source is 250µA, and the inter- GND
5584 F20

nal resistance is 2k. If this pin is left disconnected, it will

self-bias to 500mV. A low impedance voltage source with Figure 20. Simplified Schematic of the Interface for the
a source resistance of less than 200Ω is recommended DCOI, DCOQ, IP2I and IP2Q Pins
to drive this pin. The control voltage range of the DCOI,
DCOQ, IP2I and IP2Q pins is set by the REF pin. This range VCC

is equal to 0V to twice the voltage on the REF pin, whether LTC5584

internally or externally applied.
It is recommended to decouple any AC noise present on
the signal lines that connect to the analog control-voltage 250µA

inputs. A shunt capacitor to ground placed close to these REF

pins can provide adequate filtering. For instance, a value 2k

of 1000pF on the DCOI, DCOQ, IP2I and IP2Q pins will

provide a corner frequency of around 6 to 7MHz. A similar 5584 F21

corner frequency can be obtained on the REF pin with a GND

value of 3900pF. Using larger capacitance values such as Figure 21. Simplified Schematic of the REF Pin Interface
0.1µF is recommended on these pins unless a faster control
response is needed. Figure 22 shows the input response 0
–3dB bandwidth for the pins versus shunt capacitance –1
TC = 25°C

when driven from a 50Ω source. –2

–3
DC Offset Adjustment Circuitry
RESPONSE (dB)

–4

Any sources of LO leakage to the RF input of a direct –5

conversion receiver will contribute to the DC offsets of –6

its baseband outputs. The LTC5584 features DC offset –7

adjustment circuitry to reduce such effects. When the –8 DCOI, DCOQ; C = 470pF
DCOI, DCOQ; C = 1000pF
–9
EDC pin is a logic high the circuitry is enabled and the IP2I, IP2Q; C = 100pF
–10
resulting DC offset adjustment range is typically ±20mV. 0 2 4 6 8 10 12 14 16 18 20
In a typical direct conversion receiver application, DC FREQUENCY (MHz) 5584 F22

offset calibration will be done periodically at a time when

Figure 22. Input Response Bandwidth for the
no receive data is present and when the receiver DC levels DCOI, DCOQ, IP2I and IP2Q Pins
have sufficiently settled.

5584f

22

Applications Information
DC Offset Adjustment Example
Figure 23 shows a typical direct conversion receive path
having a DSP feedback path for DC offset adjustment.
Any sources of LO leakage to the RF input of the LTC5584
demodulator will contribute to the DC offset of the receiver.
This includes both static and dynamic DC offsets. If the
coupling is static in nature due to fixed board-level leakage
paths, the resulting DC offset does not typically need to
be adjusted at a high repetition rate. Dynamic DC offsets
due to transmitter transient leakage or antenna reflection
can be much harder to correct for and will require a faster
update rate from the DSP.
LO leakage into the RF port of the demodulator causes a
DC offset at the baseband outputs which is then multiplied
by the gain in the baseband path. The usable ADC voltage
window will be reduced by the amplified DC offset, resulting
in lower dynamic range. Using DSP, this DC offset value
can be averaged and sampled at a given update rate and
then a 1D minimization algorithm can be applied before
a new DCOI or DCOQ control signal is generated to mini-
mize the offset. The 1-D minimization algorithm can be
implemented in many ways such as golden-section search,
backtracking, or Newton’s method.
IM2 Adjustment Circuitry
The LTC5584 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
to adjust the IM2 level. The IM2 level can be effectively
LTC5584
limit of about 200MHz. Any IM2 component that falls in this
frequency range can be minimized. Beyond this frequency,
the gain of the IM2 correction amplifier falls off appreciably
and the circuit no longer improves IP2 performance. The
lower baseband frequency limit of the IM2 adjustment
circuitry is set by the common mode reference decoupling
capacitor at the CMI and CMQ pins. Below this frequency
the circuit can not minimize the IM2 component.
Figure 24 shows the CMI (and identical CMQ) pin interface.
These pins have an internal 40pF decoupling capacitance
to VCC, to provide a reference for the IP2 adjustment cir-
cuitry. The lower 3dB frequency limit, fC, of the circuitry
is set by the following equation:
fC = [2π • 500(40pF + CCM(EXT))]–1
Without any external capacitor on the CMI or CMQ pin the
lower limit is 8MHz. By adding a 0.1μF capacitor, CCM(EXT),
between the CMI and CMQ pins to VCAP, the lower –3dB
frequency corner can be reduced to 3kHz. Figure 25 shows
IIP2 as a function of RF frequency spacing versus common
mode decoupling capacitance values of 0.1µF and 1500pF.
There is effectively no limit on the size of this capacitor,
VCC
LTC5584
VCAP
40pF
CMI OR CMQ
5584 F24

GND
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper Figure 24. Equivalent Circuit of the CMI and CMQ Pin Interfaces

DSP
1-D
DAC MINIMIZATION
DC ALGORITHM
AVERAGING
LOWPASS
BPF DCOI FILTER
SAMPLE AND
LNA ADC HOLD
LTC5584
fLO = 900MHz 5585 F23

Figure 23. Block Diagram of a Receiver with a DSP Feedback Loop for DC Offset Adjustment
5584f

23
LTC5584
Applications Information
other than the impact it has on enable time for the IM2 IM2 Suppression Example
circuitry to be operational. When the chip is disabled, there
IM2 adjustment circuitry can be used in a typical transceiver
is no current in the I or Q mixers, so the common mode
loop-back application as shown in Figure 27. In this example
output voltage will be equal to VCC (if no DC common mode
a 2-tone SSB training source of f1 = 20MHz and f2 = 21MHz
current is being drawn by external baseband circuitry such
is generated in DSP and upconverted by the LTC5588-1
as a baseband amplifier). When the chip is enabled, the
quadrature modulator to RF tones at 870MHz and 871MHz
off-chip common mode decouping capacitor must charge
using an LO source at 850MHz. A narrowband RF filter is
up through a 500Ω resistor. The time constant for this is
required to remove the IM2 component generated by the
essentially 500Ω times the common mode decoupling
LTC5588-1. During the loopback test these RF tones are
capacitance value. For example, with a 0.01µF capacitor
routed through high isolation switches and an attenuation
this wait time is approximately 30μs. Figure 26 shows
pad to the LTC5584 demodulator input. The tones are then
the pulsed enable response of the common-mode output
downconverted by the same LO source at 850MHz to
voltage with 0.01µF on the CMI and CMQ pins.
produce two tones at the baseband outputs of 20MHz and
21MHz plus an IM2 impairment signal at 1MHz. After base-
130
0.1µF (UNCALIBRATED) band channel filtering and amplification the output of the
120
0.1µF (NULLED IP2I = 0.6V)
1500pF (UNCALIBRATED) ADC is filtered by a 1MHz bandpass filter in DSP to isolate
1500pF (NULLED IP2I = 0.6V)
110 T = 25°C the IM2 tone. The power in this tone is calculated in DSP
C
fRF1 = 1000MHz
100 f = 960MHz
and then a 1-D minimization algorithm is applied to calculate
the correction signal for the IP2I control voltage pin. The
IIP2 (dBm)

LO

90
1-D minimization algorithm can be implemented in many
80
ways such as golden-section search, backtracking or
70 Newton’s method.
60

50
Enable Interface
0.01 0.1 1 10
RF FREQUENCY SPACING (MHz) A simplified schematic of the EN pin is shown in Figure 28.
5584 F25 The enable voltage necessary to turn on the LTC5584 is 2V.
To disable or turn off the chip, this voltage should be below
Figure 25. IIP2 vs Common Mode Decoupling Capacitance
0.3V. If the EN pin is not connected, the chip is disabled.
8 10 Figures 29 and 30 show the simplified schematics for the
TC = 25°C
CCMI,Q = 0.01µF EDC and EIP2 pins.
7 5
EN
EN PULSE ON It is important that the voltage applied to the EN, EDC and
ENABLE VOLTAGE (V)

PULSE
OFF EIP2 pins should never exceed VCC by more than 0.3V.
6 0
Otherwise, the supply current may be sourced through the
VCM (V)

5 –5
upper ESD protection diode connected at the pin. Under
no circumstances should voltage be applied directly to
CMI, CMQ
4 –10
the enable pins before the supply voltage is applied to
the VCC pin. If this occurs, damage to the IC may result.
3
BASEBAND OUTPUTS
–15 A 1k resistor in series with the enable pin can be used to
0 10 20 30 40 50 60 70 80 90 100
TIME (µs)
limit current.
5584 F26

Reducing Power Consumption

Figure 26. Common Mode Output Voltage with a Pulsed Enable
Figure 31 shows the simplified schematic of the VBIAS
interface. The VBIAS pin can be used to lower the mixer
5584f

24
 LTC5584
Applications Information
DSP
1-D
DAC MINIMIZATION
ALGORITHM

IP2I 1MHz BPF

LNA
RMS
ADC DETECTION
LTC5584

LOOPBACK fLO = 850MHz

f1 = 20MHz

DAC +
PA
f2 = 21MHz
LTC5588-1

5584 F27

Figure 27. Block Diagram for a Direct Conversion Transceiver with IM2 Adjustment. Only the I-Channel Is Shown

VCC VCC

LTC5584 LTC5584

EN EIP2
100k
100k
10k

100k 100k

5584 F28 5584 F30

GND GND

Figure 28. Simplified Schematic of the EN Pin Interface Figure 30. Simplified Schematic of the EIP2 Pin Interface

VCC
VCC
LTC5584
LTC5584 100Ω
VBIAS
EDC OPTIONAL R
TO REDUCE COPT EN
100k
CURRENT

100k
EN

5584 F29 5584 F31

GND GND

Figure 29. Simplified Schematic of the EDC Pin Interface Figure 31. Simplified Schematic of the VBIAS Pin Interface

core bias current and total power consumption for the P1dB performance versus DC current and resistor value.
chip. For example, adding 487Ω from the VBIAS pin to An optional capacitor, COPT in Figure 31, has minimal effect
GND will lower the DC current to 169mA, at the expense on improving PSRR and IIP2.
of reduced IIP3 performance. Figure 32 shows IIP3 and
5584f

25
LTC5584
Applications Information
50
I, 194mA Q, 194mA
where P0 is the input noise power and –174dBm is the
45 I, 169mA, 487Ω
I, 145mA, 294Ω
Q, 169mA, 487Ω
Q, 145mA, 294Ω
input thermal noise power in a 1Hz bandwidth. A measured
40 TC = 25°C 2-tone output spectrum at 890MHz is shown in Figure 36.
fRF = 900MHz
35 IIP3 is calculated from the 2-tone IM3 levels:
P1dB, IIP3 (dBm)

30 IIP3

25
IIP3 = (–6.929 – (–88.33))/2 – 15.4
20 IIP3 = 25.3dBm
15 P1dB
10 For this example, receiver noise floor is approximated by
5 a measurement from 28MHz to 36MHz offset frequency,
0 where adequate filtering for RF and LO signals was pos-
400 600 800 1000 1200 1400
RF FREQUENCY (MHz)
sible. Using the test data from Figure 36, the receiver
5584 F32 noise figure for the I-channel (Ch 1) is calculated using the
–8.4dBm input power, 15kHz bin width, 40MHz bandwidth,
Figure 32. IIP3 and P1dB vs DC Current and –108dBFS measured in-band noise floor:
and VBIAS Resistor Value
SNRIN = PIN – P0
900MHz Receiver Application SNRIN = –8.4 – (–174 + 76) = 89.6dB
Figure 33 shows a typical receiver application consisting of SNROUT = –10 Log10(BinW/BW) – Floor
the chain of LNA, demodulator, lowpass filter, ADC driver,
SNROUT = –43.3 + 108 = 73.7dB
and ADC. Total DC power consumption is about 2.1W. Full-
scale power at the RF input is –8.4dBm. The Chebychev NF = SNRIN – SNROUT
lowpass filter with unequal terminations is designed us- NF = 89.6 – 73.7 = 15.9dB
ing the method shown in the appendix. Filter component
values are then adjusted for the best overall response Finally, the receiver spurious free dynamic range can be
and available component values. A positive voltage gain calculated using the measured data at 890MHz:
slope with frequency is necessary to compensate for the SFDR = 2(IIP3 – NF – P0)/3
roll-off contributed by the ADC Driver and Anti-Alias Filter.
From the chain analysis shown in Figure 34, the IIP3-NF SFDR = 2(25.3 – 15.9 – (–174 + 76))/3
dynamic range figure of merit (FOM) is 5.3dB at the LNA SFDR = 73dB
input, 11.3dB at the demodulator input, and 16.8dB at the
ADC driver amp input.
The measured 6th order lowpass baseband response is
shown in Figure 35.
The receiver spurious free dynamic range (SFDR) in terms
of FOM can be calculated using the following equations:
FOM = IIP3 – NF
SFDR = 2/3(FOM – P0)
P0 = –174dBm + 10Log10(BW|Hz)

5584f

26
 5V
48mA
R2
5.6k
C3 C6
4.7µF R1 R3 4.7µF
0Ω 10Ω

C5 C4
100pF L2 AVAGO 33pF
L2
33nH MGA-633P8
33nH C19
RF INPUT BIAS 0.5pF
L3 5.6nH 40MHz LOWPASS FILTER 40MHz ANTI-ALIAS FILTER
800MHz
Applications Information

LNA
TO C7 C17 R8
1000MHz 5V R4 R5
C1 C2 1.5pF 1µF 402Ω R14 R17
200mA 110Ω 110Ω 1.8V
0.01µF 0.01µF 243Ω 86.6Ω
5V 206mA
C9 C14 C16 R6 52mA R12 R15 C21
T2
C24 VCC 47pF 150pF 150pF 20Ω 36.5Ω 27.4Ω 39pF VDD
MINI-CIRCUITS +
TC1-1-13M+ 0.01µF LTC5584 I – + AIN+ D13
L5 470nH L7 180nH L9 270nH L11 180nH LTC2185 •
6 • • 1 RF+ R7 VOCN LTC6409 R11 VCM •
2 L6 470nH L8 180nH 20Ω 36.5Ω L10 270nH L12 180nH ADC •
4 RF– D0
I– + – AIN–
3 LO+ LO– C12 C13 C15 C22
C18 R16 R19 R20
47pF 150pF 150pF 27.4Ω 39pF 150Ω 150Ω
0.1µF R9
C25 402Ω
0.01µF C11 C10 C23
0.01µF 0.01µF R13 R18
C20 1µF CONTROL
243Ω 86.6Ω
0.5pF
1 2 3 R10

•
100Ω
T1 5585 F33
MINI-CIRCUITS
TC1-1-13M+

•
LO INPUT L4 3.9nH
6 4
881MHz
6dBm C8
2.2pF

Figure 33. Simplified Schematic of 900MHz Receiver, (Only I-Channel Is Shown)

27
5584f
LTC5584
LTC5584
Applications Information
900MHz Receiver Chain Analysis
G = 34.2dB G = 16.2dB G = 16.5dB G = 16.8dB G = –1.2dB G = 0dB
NF = 1.7dB NF = 14.2dB NF = 11.8dB NF = 11.5dB NF = 24.3dB NF = 23.1dB
IIP3 = 7dBm IIP3 = 25.5dBm IIP3 = 28.6dBm IIP3 = 28.3dBm IIP3 = 48.7dBm IIP3 = 47.5dBm
FOM = 5.3dB FOM = 11.3dB FOM = 16.8dB FOM = 16.8dB FOM = 24.4dB FOM = 24.4dB

MGA-633P8 LTC5584 40MHz LPF LTC6409 40MHz AAF LTC2185

G = 18dB G = –0.3dB G = –0.3dB G = 18dB G = –1.2dB G = 0dB

NF = 0.37dB NF = 10.4dB NF = 0.3dB NF = 10dB NF = 1.2dB NF = 23.1dB
OIP3 = 37dBm IIP3 = 27.9dBm OIP3 = 50dBm IP3 = 47.5dBm
5584 F34

Figure 34. 900MHz Receiver Chain Analysis

20
TC = 25°C
10
0
–10
–20
GAIN (dB)

–30
–40
–50
–60
–70
–80
0 20 40 60 80 100 120 140 160
FREQUENCY (MHz) 5584 F35

Figure 35. Baseband Gain Response without LNA

Figure 36. fRF = 889MHz and 890MHz 2-Tone Receiver Test, fLO = 881MHz.
Ch.1 Is the I Channel and Ch.2 Is the Q Channel. Tested without LNA
5584f

28
 LTC5584
Appendix
Chebychev Filter Synthesis with Unequal where RIN is the input impedance and the terminating
Terminations impedance ROUT is equal to RIN for the n odd case but is
scaled by the gn+1 prototype value for the n even case.
To synthesize Chebychev filters with unequal terminations,
two equally terminated filters are synthesized at the two The Impedance Bisection Theorem can be applied to sym-
different impedance levels and the resulting networks are metrical networks by dividing the element values along
joined using the Impedance Bisection Theorem[1]. This the networks’ plane of symmetry, and then adding the
method only works with symmetrical odd-order filters. The two networks together. The filter response is preserved.
general lowpass prototype element values are generated For example, if LAr|dB = 0.2dB, fC = 40MHz, RIN = 100Ω,
by the method shown [2]: ROUT = 20Ω and n = 5, the prototype element values and
 L |  resulting scaled filter values are listed:
β =In coth Ar dB 
 17.37  Filter 1: RIN = ROUT = 100Ω
β g1 = 1.339 → C1 = 53.3pF
γ = sinh  
 2n  g2 = 1.337 → L1 = 531.98nH
g3 = 2.166 → C2 = 86.19pF
π ( 2k – 1)
ak = sin , k = 1,2,...,n g4 = 1.337 → L2 = 531.98nH
2n
g5 = 1.339 → C3 = 53.3pF
πk
bk = γ 2 + sin2 , k = 1,2,...,n Filter 2: RIN = ROUT = 20Ω
n
where LAr|dB is the passband ripple in dB, and n is the g1 = 1.339 → C1 = 266.48pF
filter order. g2 = 1.337 → L1 = 106.4nH
The prototype element values will be: g3 = 2.166 → C2 = 430.93pF
2a 1 g4 = 1.337 → L2 = 106.4nH
g1 =
γ g5 = 1.339 → C3 = 266.48pF
The Impedance Bisection Theorem can be applied at the
4a k a k–1
gk = , k = 1,2,...,n plane of symmetry about C2 such that a new value of C2
b k−1g k−1 can be computed with half the values of the two filters.
g n+1 = 1 for n odd 86.19pF 430.93pF
C2→ + = 258.56pF
2 2
 β
g n+1 = coth 2   for n even The final unequally-terminated filter design values are
 4
shown in Figure 37.
Assuming the first element is a capacitor, we can scale the [1] A.C. Bartlett, “An Extension of a Property of Artificial Lines,” Phil. Mag., vol.4, p.902,
filter capacitor prototype values up to our desired cutoff November 1927.
[2] G. Matthaei, L. Young, and E.M.T. Jones, Microwave Filters, Impedance-Matching Networks,
frequency fC: and Coupling Structures, p.99, 1964.

gk
Ck = , k = 1,3,...,n RIN
100Ω
L1
531.98nH
L2
106.4nH
2π • fC •RIN
+
C1 C2 C3 ROUT
The filter inductor values can be scaled with: –
53.3pF 258.56pF 266.48pF 20Ω

gk •RIN 5585 F37

LK = , k = 2,4,...,n Figure 37. Final Design Schematic

2π • fC
5584f

29
LTC5584
Appendix
Image Rejection Calculation The image rejection ratio (IRR) can then be written as:
Image rejection can be calculated from the measured gain |desired|2
and phase error responses of the demodulator. Consider IRR|dB = 10log
|image|2
the signal diagram of Figure 38:
where: Written in terms of AERR and φERR as:
RF(t) = sin(ωLO + ωBB)t + sin(ωLO – ωIM)t |1+ AERR 2 + 2AERR cos ( φERR ) |
IRR|dB = 10log
LOI(t) = cos(ωLOt + φERR) |1+ AERR 2 − 2AERR cos ( φERR ) |
LOQ(t) = sin(ωLOt) Figure 39 shows image rejection as a function of amplitude
ωLO + ωBB is the desired sideband frequency and and phase errors for a demodulator.
ωLO – ωIM is the image frequency. The total phase error
of the I and Q channels is lumped into the I-channel LO AERR I(t)
source as φERR. The total gain error is represented by
AERR, and is lumped into a gain multiplier in the I-channel. LOI(t)
RF(t)
After lowpass filtering the I and Q signals can be written as: LOQ(t)

AERR
I(t) = sin ( ω BB t – φERR ) – sin ( ωIM t + φERR ) 
2 
Q(t)
5585 F38

1 Figure 38. Signal Diagram for a Demodulator

Q(t) = cos ( ω BB t ) + cos ( ωIM t ) 
2
70
AERR = 0dB
Shifting the Q channel by –90° can be accomplished by AERR = 0.05dB
replacing sine with cosine such that the shifted Q-channel 60 AERR = 0.1dB
AERR = 0.2dB
signal is:
IMAGE REJECTION (dB)

AERR = 0.3dB
50 AERR = 0.5dB
AERR = 1dB
1
Q –90 (t) = sin ( ω BB t ) + sin ( ωIM t )  40
2
30
We combine I(t) + Q–90(t) and choose terms containing
ωBB as the desired signal: 20

1 A
desired = sin ( ω BB t ) + ERR sin ( ω BB t – φERR )
10
0 1 2 3 4 5 6 7 8 9 10
2 2 PHASE ERROR (DEG)
5585 F39

Similarly, we choose terms containing ωIM as the image

signal: Figure 39. Image Rejection as a Function of Gain and Phase Errors

1 A
image = sin ( ωIM t ) – ERR sin ( ωIM t + φERR )
2 2

5584f

30
 LTC5584
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)

0.70 ±0.05

4.50 ±0.05 2.45 ±0.05

3.10 ±0.05 (4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH
R = 0.20 TYP OR
4.00 ±0.10 0.75 ±0.05 R = 0.115 0.35 × 45° CHAMFER
(4 SIDES) TYP
23 24

PIN 1 0.40 ±0.10

TOP MARK
(NOTE 6) 1
2

2.45 ±0.10
(4-SIDES)

(UF24) QFN 0105 REV B

0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

5584f

31
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC5584
Typical Application
Simplified Schematic of 900MHz Receiver, (Only I-Channel Is Shown)
RF INPUT
800MHz
TO
1000MHz C19
0.5pF
C2 40MHz LOWPASS FILTER 40MHz ANTI-ALIAS FILTER (AAF)
0.01µF
C17 R4 R5 R8
C7 5V 402Ω R14 R17
1µF 110Ω 110Ω
L3 1.5pF 200mA 243Ω 86.6Ω 1.8V
5.6nH 5V 206mA
C9 C14 C16 R6 52mA R12 R15 C21
T2
C24 VCC 47pF 150pF 150pF 20Ω 36.5Ω 27.4Ω 39pF VDD
MINI-CIRCUITS
TC1-1-13M+ 0.01µF LTC5584 I
+
– + AIN+ D13
6 • L5 470nH L7 180nH L9 270nH L11 180nH •
• 1 RF+ R7 VOCM LTC6409 R11 VCM
LTC2185 •
2 L6 470nH L8 180nH 20Ω 36.5Ω L10 270nH L12 180nH ADC •
4
3
RF– I– + – AIN– D0
LO+ LO– C12 C13 C15
C18 R16 C22 R19 R20
47pF 150pF 150pF 27.4Ω 39pF 150Ω 150Ω
0.1µF R9
C25 402Ω C23
0.01µF R13 R18
C20 1µF CONTROL
C11 C10 243Ω 86.6Ω
0.5pF
0.01µF 0.01µF
R10
1 2 3 100Ω
5584 TA02
•

T1
MINI-CIRCUITS
TC1-1-13M+
•

LO INPUT L4 3.9nH
6 4
900MHz
6dBm C8
2.2pF

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5584f

32 Linear Technology Corporation

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