Lecture 2

Common Source Amplifier

Small-Signal Model

Boris Murmann
Stanford University
murmann@stanford.edu
Copyright © 2004 by Boris Murmann

B. Murmann EE 214 Lecture 2 (HO#3) 1

 Overview
• Reading
– 3.0 (Amplifier basics), 3.1 (Model selection)
– 3.2.2 (Common source amplifer)
– 1.6.0 ... 1.6.5 (Small signal MOS model)
• Introduction
– In this lecture, we will use the simple long channel MOS
model to construct our first amplifier - a common source
stage. Looking at its transfer function, we'll find that treating
signals as "small" with respect to the bias conditions allows
us to linearize the circuit. Next, we generalize this approach
and develop a more universal"small signal model" for MOS
devices that are biased in the forward active region.

B. Murmann EE 214 Lecture 2 (HO#3) 2

 First-Order MOS Model Summary

VDS

1 W
I D ≅ µCox (VGS − Vt )2 ≅
2 L

h old "VCCS"
re
s FORWARD ACTIVE
VGS-Vt T h r . ..)
u b- l ate
S re TRIODE
o
(m

I D ≅ µCox
W
L
⎡
(V
⎢⎣ GS − Vt ) −
VDS ⎤
2 ⎥⎦
⋅ VDS ≅

Vt VGS

B. Murmann EE 214 Lecture 2 (HO#3) 3

 One Way to Amplify

• Convert input voltage to current using voltage controlled current

source (VCCS)
• Convert back to voltage using a resistor (R)
• "Voltage gain" = ∆Vout/∆Vin
– Product of the V-I and I-V conversion factors

∆Vin ∆I ∆Vout
VCCS R

B. Murmann EE 214 Lecture 2 (HO#3) 4

 Common Source Amplifier

• MOS device acts as VCCS

VDD

Vo

Vi
Id

1 W 1 W
I D = µCox (Vi − Vt )2 Vo = VDD − µCox (Vi − Vt )2 ⋅ R
2 L 2 L

B. Murmann EE 214 Lecture 2 (HO#3) 5

 Biasing

• Need some sort of "battery" that brings input voltage into useful
operating region
• Define VOV=VI-Vt, "quiescent point gate overdrive"
– VOV=VGS-Vt with no input signal applied

VDD

VO +∆Vo VO ∆Vo
∆Vi
I D+∆Id

"Signal" ∆Vi VOV

"Bias" VI

VI

B. Murmann EE 214 Lecture 2 (HO#3) 6

 Relationship Between Incremental Voltages

• What is ∆Vo as a function of ∆Vi?

1 W
VO + ∆Vo = VDD − µCox (VOV + ∆Vi )2 ⋅ R
2 L
1
2
W
[
∆Vo = − µCox R ⋅ (VOV + ∆Vi )2 − VOV 2
L
]
1
2
W
[
= − µCox R ⋅ 2VOV ∆Vi + ∆Vi 2
L
]
2I ⎡ ∆Vi ⎤
= − D ⋅ R ⋅ ∆Vi ⎢1 + ⎥
VOV ⎣ 2VOV ⎦
• As expected, this is a nonlinear relationship
• Nobody likes nonlinear equations, we need a simpler model
– Fortunately, a linear approximation to the above expression
is sufficient for 90% of all analog circuit analysis
B. Murmann EE 214 Lecture 2 (HO#3) 7
 Small Signal Approximation (1)

2I D ⎡ ∆Vi ⎤
∆Vo = − ⋅ R ⋅ ∆Vi ⎢1 + ⎥
VOV ⎣ 2VOV ⎦

• Assuming ∆Vi << 2VOV, we have

2I D
∆Vo ≅ − ⋅ R ⋅ ∆Vi
VOV

• If we further pretend that the input voltage increment is infinitely

small, we can find this result directly by taking the derivative of
the large signal transfer function at the "operating point" VI

dVo 2I
= − D ⋅R
dVi V =V VOV
i I

B. Murmann EE 214 Lecture 2 (HO#3) 8

 Small Signal Approximation (2)

• Graphical illustration:

dVo/dVi
VO

VOV

VI

• The slope of the above tangent is the so called "small signal

gain" of our amplifier

B. Murmann EE 214 Lecture 2 (HO#3) 9

 Small Signal MOS Model
• Fortunately we don't have to repeat this analysis for every single
circuit we build
• Instead, we derive a linearized circuit model for the MOS
transistor and plug it into arbitrary circuits
ID+id id

+
+
VDS +vds gm⋅vgs
+ + vds
-
VGS+vgs vgs -
- Conditions: -
VDS>VGS-Vt
Id vgs<<VGS-Vt id

gm
gm
ID vgs

VGS Vgs

B. Murmann EE 214 Lecture 2 (HO#3) 10

 Transconductance
• The parameter that relates small signal gate voltage to drain
current is called transconductance (gm), or y21 in two-port
nomenclature
• The transconductance is found by differentiating the large signal
I-V characteristic of the transistor in its operating point

1 W
I D = µCox (VGS − Vt )2
2 L
id ∂I W W
gm = = D = µCox (VGS − Vt ) = µCox VOV
vgs ∂VGS L L
2I D
gm =
VOV

B. Murmann EE 214 Lecture 2 (HO#3) 11

 Additional Model Components
• Now that we've decided to move on using "small signal"
approximations, it also becomes easier to refine our model and
make it more realistic
• Let's first take a look at "intrinsic gate capacitance"
– Intrinsic means that these capacitances are unavoidable and
required for the operation of the device
– Note that there are plenty of extrinsic, technology related
capacitances
• We'll talk about some of those later
• When talking about gate capacitance, we must distinguish
several operating regions
– Transistor on
• Triode and forward active regions
– Transistor "off"
• Subthreshold operation

B. Murmann EE 214 Lecture 2 (HO#3) 12

 Transistor in Triode Region
G

S W D
L

C GC

C CB

• Gate terminal and conductive channel form a parallel plate

capacitor across gate oxide CGC= WLεox/tox= WLCox
– We can approximately model this using lumped capacitors of size
½ CGC each from gate-source and gate-drain
• Changing either voltage will change the channel charge
• The depletion capacitance CCB adds extra capacitance from
drain and source to substrate
– Usually negligible
B. Murmann EE 214 Lecture 2 (HO#3) 13
 Transistor in Forward Active Region

• Assuming a long channel model, if we change the the source

voltage in the forward active region
– The voltage difference between the gate and channel at the
drain end remains at Vt, but the voltage at the source end
changes
– This means that the "bottom plate" of the capacitor does not
change uniformly
• Detailed analysis shows that in this case Cgs=2/3WLCox
– See text, section1.6.2
• In the long channel model for forward active operation, the drain
voltage does not affect the channel charge
– This means Cgd=0 in the forward active region!
• Neglecting second order effects and extrinsic caps, of course

B. Murmann EE 214 Lecture 2 (HO#3) 14

 Transistor Off
G

S W D
L

C GC

C CB

• There is no conductive channel

– Gate sees a capacitor to substrate, equivalent to the series
combination of the gate oxide capacitor and the depletion
capacitance
• If the gate voltage is taken negative, the depletion region
shrinks, and the gate-substrate capacitance grows
– With large negative bias, the capacitance approaches CGC

B. Murmann EE 214 Lecture 2 (HO#3) 15

 Intrinsic MOS Capacitor Summary

Forward
Subthreshold Triode
Active
Cgd

Cgs 0 ½ WLCox 2/ WLCox

3

Cgb Cgd 0 ½ WLCox 0

Cgs
−1
⎛ 1 1 ⎞
Cgb ⎜⎜ + ⎟⎟ 0 0
⎝ CB
C WLCox ⎠

ε Si
CCB = WL
xd

B. Murmann EE 214 Lecture 2 (HO#3) 16

 Dependence of ID on VDS

• Admittedly, our simple first order MOS I-V equation for the
forward active region looks pretty unrealistic
– Ideal current source!
• In reality, the drain current has a weak dependence on VDS

Triode Forward
Region Active Region

Finite dID/dVDS
ID

VGS-Vt

VDS

B. Murmann EE 214 Lecture 2 (HO#3) 17

 Channel Length Modulation
• "Channel length modulation" is outdated nomenclature for a
combination of several physical effects that cause finite dID/dVDS
• The precise dependence of ID on VDS is very hard to model
– You can convince yourself by looking at the BSIM3 manual
• One simple modeling approach was to assume that the large
signal current ID increases linearly with VDS ("fudge factor" λ)
1 W
I D = µCox (VGS − Vt ) 2 (1 + λVDS )
2 L

• Unfortunately, this simple modified equation has become too

inaccurate to predict large signal behavior
– Must rely on simulation for the "final tweak"
– As we will see, this is actually not a big issue…

B. Murmann EE 214 Lecture 2 (HO#3) 18

 Small Signal Output Resistance
• Yet, we must somehow take the finite dID/dVDS into account,
since it quantifies how much our forward active device deviates
form an ideal current source
• Again, this becomes somewhat easier by limiting ourselves to
"small signals"
• Define "small signal output resistance" ro

Slope = 1/ro
ID
1 dI D
= Operating Point
ro dVDS

VDS

B. Murmann EE 214 Lecture 2 (HO#3) 19

 Dependence of ro on VDS
• In the above example, it seemed like ro is independent of the
VDS operating point (as long as the device is forward active)
• Unfortunately, modern MOS I-V curves can look like this

Slope = 1/ro1 OP2

ID
Slope = 1/ro2

OP1

VDS

• Only experimental data or simulation will help us in practice to

take VDS dependence into account

B. Murmann EE 214 Lecture 2 (HO#3) 20

 Another ro Caveat
• Is vds really a "small signal"?
• The small signal approximation for ro becomes somewhat
inappropriate when the vds swing spans a large fraction of a
nonlinear ID-VDS characteristic
• Luckily, in most practical situations, other (well understood)
sources of nonlinearity dominate (e.g. transconductance)

ID
OP

OP1

VDS

B. Murmann EE 214 Lecture 2 (HO#3) 21

 Output Resistance - Summary

• The above conclusions on output resistance seem pretty

devastating
– Don't really know how to calculate ro, have to trust
technology data
– ro depends on operating point, which also means that there
is an additional source of nonlinearity
• In practice this has only mild implications
– We'll never design a circuit that relies on a precise value or
particular dependence of ro
– In order to be able to reason about the impact of ro in the
circuit design process, we will work with typical values and
lower bounds from Spice simulations

B. Murmann EE 214 Lecture 2 (HO#3) 22

 1st Order Small Signal Model (Forward Active)

G D
+
vgs Cgs gmvgs ro
-
S

2I D
gm =
VOV
2
C gs = WLCox
3
ro − follows from technology data

B. Murmann EE 214 Lecture 2 (HO#3) 23