Wide Dynamic Range, High Speed,

Digitally Controlled VGA

Data Sheet ADL5202
FEATURES FUNCTIONAL BLOCK DIAGRAM
Dual independent, digitally controlled VGAs SIDE A
SPI WITH FA,
−11.5 dB to +20 dB gain range PARALLEL WITH LATCH,
UP/DN PWUPA VPOS
0.5 dB ±0.1 dB step size
150 Ω differential input and output
7.5 dB noise figure at maximum gain LOGIC

OIP3 > 47.5 dBm at 200 MHz

VINA+ VOUTA+
0dB TO 31.5dB
−3 dB upper frequency bandwidth of 700 MHz 150Ω +20dB 150Ω
VINA– VOUTA–
Multiple control interface options
MODE0,
Parallel 6-bit control interface (with latch) MODE1 CONTROL
Serial peripheral interface (SPI) (with fast attack) PM
CIRCUITRY

Gain up/down mode

VOUTB+
Wide input dynamic range VINB+
150Ω
0dB TO 31.5dB
+20dB 150Ω
Low power mode option VINB– VOUTB–

Power-down control
LOGIC
Single 5 V supply operation ADL5202
40-lead, 6 mm × 6 mm LFCSP package
SIDE B PWUPB GND

09387-001
APPLICATIONS SPI WITH FA,
PARALLEL WITH LATCH,
UP/DN
Differential ADC drivers
Figure 1.
High IF sampling receivers
High output power IF amplification
Instrumentation

GENERAL DESCRIPTION
The ADL5202 is a digitally controlled, variable gain, wide band-
width amplifier that provides precise gain control, high output
IP3, and low noise figure. The excellent distortion performance
and high signal bandwidth make the ADL5202 an excellent gain
control device for a variety of receiver applications. The ADL5202
also incorporates a low power mode option that lowers the supply
current.
For wide input dynamic range applications, the ADL5202
provides a broad 31.5 dB gain range with 0.5 dB resolution. The
gain is adjustable through multiple gain control interface options:
parallel, serial peripheral interface, and up/down.
Incorporating proprietary distortion cancellation techniques,
the ADL5202 achieves a better than 47.5 dBm output IP3 at
frequencies approaching 200 MHz for most gain settings.
The ADL5202 is powered on by applying the appropriate logic
level to the PWUPx pins. The quiescent current of the ADL5202
is typically 160 mA in low power mode. When configured in high
performance mode for more demanding applications, the quiescent
current is 210 mA. When powered down, the ADL5202 consumes
less than 14 mA and offers excellent input-to-output isolation.
The gain setting is preserved during power-down.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5202 provides precise gain adjustment capabilities with
good distortion performance and low phase error. The ADL5202
amplifier comes in a compact, thermally enhanced 40-lead,
6 mm × 6 mm LFCSP package and operates over a temperature
range of −40°C to +85°C.

Rev. D Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADL5202
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 8
Characterization and Test Circuits ............................................... 15
Theory of Operation ...................................................................... 16
Digital Interface Overview ........................................................ 16
Parallel Digital Interface ............................................................ 16
Serial Peripheral Interface (SPI) ............................................... 16
REVISION HISTORY
1/2017—Rev. C to Rev. D
Change to Features Section and General Description Section ........ 1
Changes to Noise/Harmonic Performance Parameter, Table 1 ....... 4
1/2015—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 4
Change to Table 3 ............................................................................. 6
Rev. D | Page 2 of 29
Data Sheet
Gain Up/Down Interface ........................................................... 16
Truth Table .................................................................................. 17
Logic Timing ............................................................................... 17
Circuit Description......................................................................... 18
Basic Structure ............................................................................ 18
Applications Information .............................................................. 19
Basic Connections ...................................................................... 19
ADC Driving............................................................................... 19
Layout Considerations ............................................................... 21
Evaluation Board ............................................................................ 22
Evaluation Board Control Software ......................................... 22
Evaluation Board Schematics and Artwork ............................ 23
Evaluation Board Configuration Options ............................... 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
9/2013—Rev. A to Rev. B
Changed Logic Pins Absolute Maximum Rating from 3.6 V to
−0.3 V to +3.6 V (not to exceed |VPOS − 0.5 V| at any time) ....5
12/2012—Rev. 0 to Rev. A
Changes to Layout Consideration Section .................................. 21
10/2011—Revision 0: Initial Version
Data Sheet ADL5202

SPECIFICATIONS
VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT < 2 V p-p (5.2 dBm) 700 MHz
Slew Rate 5.5 V/ns
Input Return Loss (S11) 100 MHz −17.7 dB
Output Return Loss (S22) 100 MHz −16.5 dB
INPUT STAGE VINA+, VINB+ and VINA−, VINB− pins
Maximum Input Swing (Differential) Gain code = 111111 10.8 V p-p
Differential Input Resistance 150 Ω
Common-Mode Input Voltage 1.5 V
CMRR Gain code = 000000 40 dB
GAIN
Maximum Voltage Gain Gain code = 000000 20 dB
Minimum Voltage Gain Gain code = 111111 −11.5 dB
Gain Step Size 0.5 dB
Gain Flatness 30 MHz < fC < 200 MHz 0.285 dB
Gain Temperature Sensitivity Gain code = 000000 0.012 dB/°C
Gain Step Response For VIN = 0.2 V, gain code = 111111 to 000000 15 ns
Gain Conformance Error Over 10 dB gain range ±0.03 dB
Phase Conformance Error Over 10 dB gain range 1.0 Degrees
OUTPUT STAGE VOUTx+ and VOUTx− pins
Output Voltage Swing At P1dB, gain code = 000000 10 V p-p
Differential Output Resistance Differential 150 Ω
NOISE/HARMONIC PERFORMANCE
46 MHz Gain code = 000000, high performance mode
Second Harmonic VOUT = 2 V p-p −92 dBc
Third Harmonic VOUT = 2 V p-p −105 dBc
Output IP3 VOUT = 2 V p-p composite 47.5 dBm
70 MHz Gain code = 000000, high performance mode
Second Harmonic VOUT = 2 V p-p −96 dBc
Third Harmonic VOUT = 2 V p-p −105 dBc
Output IP3 VOUT = 2 V p-p composite 47.5 dBm
140 MHz Gain code = 000000, high performance mode
Noise Figure 7.5 dB
Second Harmonic VOUT = 2 V p-p −86 dBc
Third Harmonic VOUT = 2 V p-p −105 dBc
Output IP3 VOUT = 2 V p-p composite 47.5 dBm
Output 1 dB Compression Point 19.5 dBm
300 MHz Gain code = 000000, high performance mode
Second Harmonic VOUT = 2 V p-p −77 dBc
Third Harmonic VOUT = 2 V p-p −91 dBc
Output IP3 VOUT = 2 V p-p composite 45 dBm

Rev. D | Page 3 of 29
ADL5202 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
POWER-UP INTERFACE PWUPA, PWUPB pins
Power-Up Threshold Minimum voltage to enable the device 1.4 V
Maximum voltage to enable the device 3.3 V
PWUPx Input Bias Current 1 μA
GAIN CONTROL INTERFACE
VIH Minimum/Maximum voltage for a logic high 1.41 3.3 V
VIL Maximum voltage for a logic low 0.8
Maximum Input Bias Current 1 μA
SPI TIMING LATCHA and LATCHB, SCLK, SDIO, data pins
fSCLK 1/tSCLK 20 MHz
tDH Data hold time 5 ns
tDS Data setup time 5 ns
tPW SCLK high pulse width 5 ns
POWER INTERFACE
Supply Voltage 4.5 5.5 V
Quiescent Current, Both Channels High performance mode 210 mA
TA = 85°C 250 mA
Low power mode 160 mA
TA = 85°C 180 mA
Power-Down Current, Both Channels PWUPx low 14 mA
1
The minimum value for a logic high on the PM pin is 2.8 V.

Timing Diagrams
tSCLK tPW

SCLK

tDH
tDS
___ ___
CSA, CSB

tDS tDH

09387-002
SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0

Figure 2. SPI Interface Read/Write Mode Timing Diagram

tDS tDS

UPDN_DAT tPW

UPDN_CLK
UP DN RESET
09387-103

tDS tDH

Figure 3. Up/Down Mode Timing Diagram

LATCHA,
LATCHB

A5 TO A0
09387-104

B5 TO B0
tDH

Figure 4. Parallel Mode Timing Diagram

Rev. D | Page 4 of 29
Data Sheet ADL5202

ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Supply Voltage, VPOS 5.5
or any other conditions above those indicated in the operational
PWUPA, PWUPB, A0 to A5, B0 to B5, −0.3 V to +3.6 V
MODE0, MODE1, PM, LATCHA, LATCHB (not to exceed |VPOS − section of this specification is not implied. Operation beyond
0.5 V| at any time) the maximum operating conditions for extended periods may
Input Voltage, VIN+ ,VIN− +3.6 V to −1.2 V affect product reliability.
Internal Power Dissipation 1.6 W
θJA (Exposed Paddle Soldered Down) 34.6°C/W
θJC (At Exposed Paddle) 3.6°C/W
ESD CAUTION
Maximum Junction Temperature 140°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 240°C

Rev. D | Page 5 of 29
ADL5202 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

UPDN_DAT_A/A0
UPDN_CLK_A/A1
FA_A/A2

LATCHA

VOUTA+
VOUTA–
PWUPA
VINA+
VINA–

GND
32
31
40
39
38
37
36
35
34
33
PIN 1
CSA/A3 1 INDICATOR
30 VOUTA–
A4 2 29 VOUTA+
A5 3 28 VPOS
MODE1 4 ADL5202 27 VPOS
MODE0 5 TOP VIEW 26 VPOS
PM 6 (Not to Scale) 25 VPOS
GND 7 24 VPOS
SIDO/B5 8 EXPOSED 23 VPOS
SCLK/B4 9 PADDLE 22 VOUTB+
GS1/CSB/B3 10 21 VOUTB–

12
13
14
15
16
17
18
19
20
11 GS0/FA_B/B2
UPDN_CLK_B/B1
UPDN_DAT_B/B0

PWUPB
GND
LATCHB
VINB–
VINB+

VOUTB–
VOUTB+
NOTES

09387-003
1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
A LOW IMPEDANCE GROUND PAD.

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1 CSA/A3 Channel A Select (CSA). When serial mode is enabled, a logic low (0 V ≤ CSA ≤ 0.8 V) selects Channel A.
Bit 3 for Channel A Parallel Gain Control Interface (A3).
2 A4 Bit 4 for Channel A Parallel Gain Control Interface.
3 A5 Bit 5 (MSB) for Channel A Parallel Gain Control Interface.
4 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.
5 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.
6 PM Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high
(2.8 V ≤ PM ≤ 3.3 V) enables low power mode.
7, 18, 33, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.
8 SDIO/B5 Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing
to the SPI port.
Bit 5 for Channel B Parallel Gain Control Interface (B5).
9 SCLK/B4 Serial Clock Input in SPI Mode (SCLK).
Bit 4 for Channel B Parallel Gain Control Interface (B4).
10 GS1/CSB/B3 MSB for Gain Step Size Control in Up/Down Mode (GS1).
Channel B Select (CSB). When serial mode is enabled, a logic low (0 V ≤ CSB≤ 0.8 V) selects Channel B.
Bit 3 for Channel B Parallel Gain Control Interface (B3).
11 GS0/FA_B/B2 LSB for Gain Step Size Control in Up/Down Mode (GS0).
Fast Attack (FA_B). In serial mode, a logic high (1.4 V ≤ FA_B ≤ 3.3 V) attenuates Channel B according to
the FA setting in the SPI word.
Bit 2 for Channel B Parallel Gain Control Interface (B2).
12 UPDN_CLK_B/B1 Clock Interface for Channel B Up/Down Function (UPDN_CLK_B).
Bit 1 for Channel B Parallel Gain Control Interface (B1).
13 UPDN_DAT_B/B0 Data Pin for Channel B Up/Down Function (UPDN_DAT_B).
Bit 0 for Channel B Parallel Gain Control Interface (B0).
14 LATCHB Channel B Latch. A logic low (0 V ≤ LATCHB ≤ 0.8 V) allows gain changes on Channel B. A logic high
(1.4 V ≤ LATCHB ≤ 3.3 V) prevents gain changes on Channel B.

Rev. D | Page 6 of 29
Data Sheet ADL5202
Pin No. Mnemonic Description
15 VINB− Channel B Negative Input.
16 VINB+ Channel B Positive Input.
17 PWUPB Channel B Power-Up. A logic high (1.4 V ≤ PWUPB ≤ 3.3 V) enables Channel B.
19, 21 VOUTB− Channel B Negative Output.
20, 22 VOUTB+ Channel B Positive Output.
23, 24, 25, VPOS Positive Power Supply.
26, 27, 28
29, 31 VOUTA+ Channel A Positive Output.
30, 32 VOUTA− Channel A Negative Output.
34 PWUPA Channel A Power-Up. A logic high (1.4 V ≤ PWUPA ≤ 3.3 V) enables Channel A.
35 VINA+ Channel A Positive Input.
36 VINA− Channel A Negative Input.
37 LATCHA Channel A Latch. A logic low (0 V ≤ LATCHA ≤ 0.8 V) allows gain changes on Channel A. A logic high
(1.4 V ≤ LATCHA ≤ 3.3 V) prevents gain changes on Channel A.
38 UPDN_DAT_A/A0 Data Pin for Channel A Up/Down Function (UPDN_DAT_A).
Bit 0 for Channel A Parallel Gain Control Interface (A0).
39 UPDN_CLK_A/A1 Clock Interface for Channel A Up/Down Function (UPDN_CLK_A).
Bit 1 for Channel A Parallel Gain Control Interface (A1).
40 FA_A/A2 Fast Attack (FA_A). In serial mode, a logic high (1.4 V ≤ FA_A ≤ 3.3 V) attenuates Channel A according to
FA setting in the SPI word.
Bit 2 for Channel A Parallel Gain Control Interface (A2).

Rev. D | Page 7 of 29
ADL5202 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 200 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted.
25 25
46MHz 20dB 18dB 16dB 14dB 12dB 10dB 8dB 6dB
140MHz 19dB 17dB 15dB 13dB 11dB 9dB 7dB 5dB
20 300MHz 20

15
15
10
10

GAIN (dB)
GAIN (dB)

5
5
0
0
–5

–5
–10

–10 –15
4dB 2dB 0dB –2dB –4dB –6dB –8dB –10dB
3dB 1dB –1dB –3dB –5dB –7dB –9dB –11dB
–15 –20

09387-007
09387-004
0 10 20 30 40 50 60 70 10 100 1000
GAIN CODE FREQUENCY (MHz)

Figure 6. Gain vs. Gain Code at 46 MHz, 140 MHz, and 300 MHz Figure 9. Gain vs. Frequency Response (Every 1 dB Step)

45 50
TA = –40°C
40 45 TA = +25°C
TA = +85°C MIN GAIN (–11.5dB)
35 40

35
NOISE FIGURE (dB)

NOISE FIGURE (dB)

30
30
25
25 MID GAIN (5dB)
20
20
15
15
10 MAX GAIN (20dB)
10
5 5

0 0
09387-010

09387-013
–15 –10 –5 0 5 10 15 20 25 0 100 200 300 400 500 600
PROGRAMMED GAIN (dB) FREQUENCY (MHz)
Figure 7. Noise Figure vs. Programmed Gain at 140 MHz Figure 10. Noise Figure vs. Frequency at Max, Mid, and Min Gain Outputs

25 25
TA = –40°C
TA = +25°C
TA = +85°C
20 20
OP1dB (dBm)

OP1dB (dBm)

15 15

10 10

INPUT
5 MAX RATINGS 5
BOUNDARY

0 0
09387-005

09387-008

–15 –10 –5 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400

PROGRAMMED GAIN (dB) FREQUENCY (MHz)
Figure 8. OP1dB vs. Programmed Gain at 140 MHz Figure 11. OP1dB vs. Frequency at Maximum Gain, Three Temperatures

Rev. D | Page 8 of 29
Data Sheet ADL5202
60 60
–11.5dB –11.5dB
0dB 0dB
10dB 55 10dB
55 20dB 20dB

50

50
45

OIP3 (dBm)
OIP3 (dBm)

45 40
INPUT
MAX RATINGS
35 BOUNDARY
40
30

35
25

30 20
–4 –3 –2 –1 0 1 2 3 4 5 6

09387-014
09387-011
0 50 100 150 200 250 300 350 400
FREQUENCY (MHz) POUT (dBm)

Figure 12. Output Third-Order Intercept vs. Frequency Figure 15. Output Third-Order Intercept vs. Power at Four Gain Codes,
at Four Gain Codes Frequency = 140 MHz at 2 V p-p Composite

60 60
TA = –40°C TA = –40°C
TA = +25°C TA = +25°C
TA = +85°C TA = +85°C
55 55

50 50
OIP3 (dBm)

OIP3 (dBm)
45 45

40 40

35 35

30 30
09387-016

0 50 100 150 200 250 300 350 400 –4 –3 –2 –1 0 1 2 3 4 5 6

09387-019
FREQUENCY (MHz) POUT (dBm)

Figure 13. Output Third-Order Intercept vs. Frequency, Figure 16. Output Third-Order Intercept vs. Power, Frequency = 140 MHz,
Three Temperatures at 2 V p-p Composite Three Temperatures

–60 –60
46MHz TA = –40°C
140MHz
300MHz TA = +25°C
–70 TA = +85°C
–70

–80 –80
IMD3 (dBc)

IMD3 (dBc)

–90 –90

–100 –100

–110 –110

–120 –120
09387-018

–15 –10 –5 0 5 10 15 20 25
09387-021

0 50 100 150 200 250 300 350 400

PROGRAMMED GAIN (dB) FREQUENCY (MHz)
Figure 14. Two-Tone Output IMD3 vs. Programmed Gain, Figure 17. Two-Tone Output IMD3 vs. Frequency,
at 46 MHz, 140 MHz, 300 MHz Three Temperatures

Rev. D | Page 9 of 29
ADL5202 Data Sheet
–50 –20 –60 –40
–11.5dB –11.5dB
0dB 0dB
–60 10dB –30 10dB
–70 –50

HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

20dB 20dB
HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

–70 –40
–80 –60
–80 –50
–90 –70
–90 –60

–100 –70 –100 –80

–110 –80
–110 –90
–120 –90
–120 –100
–130 –100
–130 –110
–140 –110

–150 –120 –140 –120

09387-023

09387-026
0 50 100 150 200 250 300 350 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
FREQUENCY (MHz) POUT (dBm)

Figure 18. Harmonic Distortion vs. Frequency at Four Gain Codes Figure 21. Harmonic Distortion vs. Power at Four Gains,
Frequency = 140 MHz

–60 –40 –80 –60

TA = –40°C TA = –40°C
TA = +25°C TA = +25°C
–70 TA = +85°C –50 TA = +85°C
HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

–90 –70
–80 –60

–100 –80
–90 –70

–100 –80 –110 –90

–110 –90
–120 –100
–120 –100

–130 –110
–130 –110

–140 –120 –140 –120

09387-028

09387-031
0 50 100 150 200 250 300 350 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
FREQUENCY (MHz) POUT (dBm)

Figure 19. Harmonic Distortion vs. Frequency, Three Temperatures Figure 22. Harmonic Distortion vs. Power, Frequency = 140 MHz,
Three Temperatures

25 25
TA = –40°C
TA = +25°C
TA = +85°C
20 20
OP1dB (dBm)

OP1dB (dBm)

15 15

10 10

INPUT
MAX
5 RATINGS 5
BOUNDARY

0 0
09387-009
09387-006

–15 –10 –5 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400

PROGRAMMED GAIN (dB) FREQUENCY (MHz)

Figure 20. OP1dB vs. Programmed Gain at 140 MHz, Low Power Mode Figure 23. OP1dB vs. Frequency at Maximum Gain, Three Temperatures,
Low Power Mode

Rev. D | Page 10 of 29
Data Sheet ADL5202
60 60
–11.5dB –11.5dB
0dB 0dB
10dB 55 10dB
55 20dB 20dB
50
50
45
OIP3 (dBm)

OIP3 (dBm)
45 40

35
40 INPUT
MAX RATINGS
30 BOUNDRY
35
25

30 20

09387-015
09387-012
0 50 100 150 200 250 300 350 400 –4 –3 –2 –1 0 1 2 3 4 5 6
FREQUENCY (MHz) POUT (dBm)

Figure 24. Output Third-Order Intercept vs. Frequency Figure 27. Output Third-Order Intercept vs. Power at Four Gain Codes,
at Four Gain Codes, Low Power Mode at 2 V p-p Composite Frequency = 140 MHz, Low Power Mode

60 60
TA = –40°C TA = –40°C
TA = +25°C TA = +25°C
TA = +85°C 55 TA = +85°C
55
50

50
45

OIP3 (dBm)
OIP3 (dBm)

45 40

35
40
30

35
25

30 20
09387-017

–4 –3 –2 –1 0 1 2 3 4 5 6

09387-020
0 50 100 150 200 250 300 350 400
FREQUENCY (MHz) POUT (dBm)

Figure 25. Output Third-Order Intercept vs. Frequency, Figure 28. Output Third-Order Intercept vs. Power,
Three Temperatures, Low Power Mode Three Temperatures, Low Power Mode at 2 V p-p Composite

–60 –60
46MHz TA = –40°C
140MHz TA = +25°C
300MHz TA = +85°C
–70 –70

–80 –80
IMD3 (dBc)

IMD3 (dBc)

–90 –90

–100 –100

–110 –110

–120 –120
09387-022

09387-025

–15 –10 –5 0 5 10 15 20 25 0 50 100 150 200 250 300 350 400

PROGRAMMED GAIN (dB) FREQUENCY (MHz)
Figure 26. Two-Tone Output IMD3 vs. Programmed Gain Figure 29. Two-Tone Output IMD3 vs. Frequency,
at 46 MHz, 140 MHz, 300 MHz; Low Power Mode Three Temperatures, Low Power Mode

Rev. D | Page 11 of 29
ADL5202 Data Sheet
–50 –20 –60 –40
–11.5dB –11.5dB
0dB 0dB
–60 10dB –30 10dB
–70 –50

HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

20dB 20dB
HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

–70 –40
–80 –60
–80 –50
–90 –70
–90 –60

–100 –70 –100 –80

–110 –80
–110 –90
–120 –90
–120 –100
–130 –100
–130 –110
–140 –110

–150 –120 –140 –120

09387-024

09387-027
0 50 100 150 200 250 300 350 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
FREQUENCY (MHz) POUT (dBm)

Figure 30. Harmonic Distortion vs. Frequency at Four Gain Codes, Figure 33. Harmonic Distortion vs. Power at Four Gain Codes,
Low Power Mode Frequency = 140 MHz, Low Power Mode

–50 –20 –70 –50

TA = –40°C TA = –40°C
–60 TA = +25°C –30 TA = +25°C
TA = +85°C TA = +85°C
HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

HARMONIC DISTORTION HD2 (dBc)

HARMONIC DISTORTION HD3 (dBc)

–80 –60
–70 –40

–80 –50
–90 –70
–90 –60

–100 –70 –100 –80

–110 –80
–110 –90
–120 –90

–130 –100
–120 –100
–140 –110

–150 –120 –130 –110

09387-029

09387-032
0 50 100 150 200 250 300 350 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
FREQUENCY (MHz) POUT (dBm)

Figure 31. Harmonic Distortion vs. Frequency, Three Temperatures, Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz, Three
Low Power Mode Temperatures, Low Power Mode
VOLTAGE

CH1 200mV/DIV
1

CH4 1V/DIV
4
09387-033
09387-036

CH1 200mV Ω M 10ns 10GS/s A CH4 1.12V TIME (10ns/DIV)

CH4 1mV Ω IT 4ps/pt

Figure 32. Enable Time Domain Response Figure 35. Disable Time Domain Response

Rev. D | Page 12 of 29
Data Sheet ADL5202

CH2 500mV/DIV 0pf

5.6pf DIFFERENTIAL

CH3 50mV/DIV
VOLTAGE

VOLTAGE
INPUT

200mV/DIV

09387-030

09387-034
TIME (10ns/DIV) TIME (1ns/DIV)

Figure 36. Gain Step Time Domain Response Figure 39. Large Signal Pulse Response, 0 pF and 5.6 pF, 2 V p-p Composite

0 200 0 300

–10 250
–10 150
–20 200
–20 100
–30 150

S22 MAGNITUDE (dB)

S22 PHASE (Degrees)

S11 MAGNITUDE (dB)

S11 PHASE (Degrees)

–30 50 –40 100

–40 0 –50 50

–60 0
–50 –50
–70 –50
–60 –100
–80 –100
MAGNITUDE MAX GAIN MAGNITUDE MAX GAIN
–70 MAGNITUDE MIN GAIN –150 –90 MAGNITUDE MIN GAIN –150
PHASE MAX GAIN PHASE MAX GAIN
PHASE MIN GAIN PHASE MIN GAIN
–80 –200 –100 –200

09387-038
09387-035

10 100 1000 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 37. S11 Magnitude and Phase vs. Frequency Figure 40. S22 Magnitude and Phase vs. Frequency

1.0 –60

0.8
–65
0.6
–70
CHANNEL ISOLATION (dB)

0.4 CHANNEL A TO CHANNEL B

GAIN ERROR (dB)

CHANNEL A = MAX GAIN

–75 CHANNEL B = ALL GAINS
0.2

0 –80

–0.2
–85
–0.4
–90 CHANNEL B TO CHANNEL A
–0.6 CHANNEL B = MAX GAIN
CHANNEL A = ALL GAINS
–0.8 –95

–1.0 –100
09387-037

09387-043

–15 –10 –5 0 5 10 15 20 25 0 100 200 300 400 500 600 700 800 900 1000
PROGRAMMED GAIN (dB) FREQUENCY (MHz)
Figure 38. Gain Step Error, Frequency = 140 MHz Figure 41. Channel Isolation vs. Frequency

Rev. D | Page 13 of 29
ADL5202 Data Sheet
0 0

–10 –10
REVERSE ISOLATION (dB)

REVERSE ISOLATION (dB)

–20 –20

–30 –30

–40 –40

–50 –50

–60 –60

09387-039

09387-042
10M 100M 1G 10 100 1000
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 42. Reverse Isolation vs. Frequency Figure 45. Disable-State Reverse Isolation vs. Frequency

1.0 60

COMMON-MODE REJECTION RATIO, CMRR (dB)

MIN
MID
MAX
50
0.8
GROUP DELAY (ns)

40
0.6

30

0.4
20

0.2
10

0 0
09387-040

09387-044
10 100 1000 10M 100M 1G
FREQUENCY (MHz) FREQUENCY (Hz)

Figure 43. Group Delay vs. Frequency at Max, Mid, and Min Gain Outputs Figure 46. Common-Mode Rejection Ratio vs. Frequency

4.0

3.5
PHASE VARIATION (Degrees)

3.0

2.5 350MHz
300MHz
250MHz
2.0 200MHz
150MHz
100MHz
1.5 50MHz

1.0

0.5

0
09387-041

0 10 20 30 40 50 60 70
GAIN CODE

Figure 44. Phase Variation vs. Gain Code

Rev. D | Page 14 of 29
Data Sheet ADL5202

CHARACTERIZATION AND TEST CIRCUITS

+5V

L1 L2
1µH 1µH
0.1µF 0.1µF
50Ω 50Ω
1/2
AC 50Ω TRACES ADL5202 50Ω TRACES AC

50Ω 50Ω
0.1µF 0.1µF
6

09387-060
A0 TO A5

Figure 47. Test Circuit for S-Parameters on Dedicated 50 Ω Differential-to-Differential Board

+5V

L1 L2
1µH 1µH
C1 C3
R1 R4
0.1µF 0.1µF
TC3-1T 62Ω 25Ω ETC1-1-13
1/2
50Ω T1 ADL5202 PAD LOSS = 11dB T2 50Ω

AC C2 C4 R2 R3
0.1µF 0.1µF 62Ω 25Ω
6

09387-062
A0 TO A5

Figure 48. Test Circuit for Distortion, Gain, and Noise

09387-063

Figure 49. Differential-to-Differential Characterization Board,

Circuit Side Layout

Rev. D | Page 15 of 29
ADL5202 Data Sheet

THEORY OF OPERATION
DIGITAL INTERFACE OVERVIEW To read the SPI register value, the R/W bit must be set high,
The ADL5202 VGA has three digital gain control options: CSA or CSB must be pulled low, and the part must be clocked.
the parallel control interface, serial peripheral interface, and gain After the register has been read out during the next 16 clock cycles,
up/down interface. The desired gain control option is selected the SPI is automatically put into write mode. Note that there is
via two control pins, MODE0 and MODE1 (see Table 4 for the only one SDIO pin. Readback from the registers should be per-
truth table for the mode control pins). The gain code is in a 6-bit formed individually.
binary format. A voltage of between 1.4 V and 3.3 V is required Fast Attack
for a logic high. The fast attack feature, accessible via the SPI, allows the gain to be
Three pins are common to all gain control options: PM, PWUPA, reduced from its present gain setting by a predetermined step size.
and PWUPB. PM allows the user to choose operation in nominal Four different attenuation step sizes are available. The truth table
mode or high performance mode. PWUPA and PWUPB are for fast attack is shown in Table 5.
power-up pins for Channel A and Channel B, respectively.
Physical pins are shared among the three interfaces, resulting in Table 5. SPI 2-Bit Attenuation Step Size Truth Table
as many as three different functions per digital pin (see Table 3). FA1 FA0 Step Size (dB)
0 0 2
Table 4. Digital Control Interface Selection Truth Table 0 1 4
MODE1 MODE0 Interface 1 0 8
0 0 Parallel control 1 1 16
0 1 Serial peripheral (SPI)
SPI fast attack mode is controlled by the FA_A or FA_B pin.
1 0 Up/down
A logic high on the FA_A or FA_B pin results in an attenuation
1 1 Up/down
that is selected by Bits[FA1:FA0] in the SPI register.
PARALLEL DIGITAL INTERFACE GAIN UP/DOWN INTERFACE
The parallel digital interface uses six binary bits (Bits[A5:A0] or The GS1 and GS0 pins control the up/down gain step function.
Bits[B5:B0]) and a latch pin (LATCHA or LATCHB) per amplifier. Gain is increased by a clock pulse on the UPDN_CLK_A pin or
The latch pin controls whether the input data latch is transparent the UPDN_CLK_B pin (rising and falling edges) when the
or latched. In transparent mode, gain changes as input gain control UPDN_DAT_A or UPDN_DAT_B pin is high. Gain is decreased
bits change. In latched mode, gain is determined by the latched by a clock pulse on the UPDN_CLK_A or UPDN_CLK B pin
gain setting and does not change with changing input gain when the UPDN_DAT_A or UPDN_CLKB pin is low. The truth
control bits. table for the gain step function is shown in Table 6. Reset is
SERIAL PERIPHERAL INTERFACE (SPI) detected by a rising edge latching data having one polarity, with
the falling edge latching the opposite polarity. Reset results in
The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The
a minimum binary gain code of 111111.
SPI data register consists of two bytes: six gain control bits, two
attenuation step size address bits, one read/write bit, and seven Table 6. Step Size Control Truth Table
don’t care bits. SDIO is the serial data input and output pin. The GS1 GS0 Step Size (dB)
SCLK pin is the serial clock, and CSA or CSB is the channel 0 0 0.5
select pin. 0 1 1
DATA
LSB MSB LSB MSB
1 0 2
D0 D1 D2 D3 D4 D5 FA0 FA1 R/W DNC DNC DNC DNC DNC DNC DNC
1 1 4
DO NOT CARE
(7 BITS) The step size is selectable using the GS1 and GS0 pins. The gain
READ/WRITE is limited by the top and bottom of the control range.
FAST ATTACK ATTENUATION
09387-046

STEP SIZE ADDRESS

GAIN CONTROL UPDN_DAT
09387-045

Figure 50. 16-Bit SPI Register UPDN_CLK

UP DN RESET
To write to the SPI register, CSA or CSB must be pulled low and
Figure 51. Up/Down Timing
16 clock pulses must be applied to SCLK. Individual channel
SPI registers can be selected by pulling CSA or CSB low. By
pulling the CSA and CSB pins low simultaneously, the same
data can be written to both SPI registers.

Rev. D | Page 16 of 29
Data Sheet ADL5202
TRUTH TABLE LOGIC TIMING
Table 7. Gain Code vs. Voltage Gain Lookup Table To write to the ADL5202, refer to the timing shown in Figure 2
6-Bit Binary Voltage 6-Bit Binary Voltage (reproduced in this section as Figure 52). The write mode uses
Gain Code Gain (dB) Gain Code Gain (dB) a 16-bit serial word on the SDIO pin. The R/W of the word must be
000000 20 100000 4 low to write Bits[D0:D5], which are the binary weighted codes for
000001 19.5 100001 3.5 the attenuation level (0 = minimum attenuation, 63 = maximum
000010 19 100010 3
attenuation). The FA0 and FA1 bits control the fast attack step size.
000011 18.5 100011 2.5
000100 18 100100 2 The DNC bits are nonfunctional, do not care bits. Reading the
000101 17.5 100101 1.5 ADL5202 SPI register requires the following two steps:
000110 17 100110 1 1. Set the R/W bit high using a 16-bit word and the timing
000111 16.5 100111 0.5 described in this section and Figure 52. All other bits are
001000 16 101000 0
ignored when the R/W bit is high.
001001 15.5 101001 −0.5
001010 15 101010 −1 2. The SDIO is used as an output during the next sequence.
001011 14.5 101011 −1.5 The written pattern is serially clocked out on SDIO using
001100 14 101100 −2 16 clocks and the timing described in this section and
001101 13.5 101101 −2.5 Figure 52. The R/W bit automatically returns low to the
001110 13 101110 −3 write state following the read sequence.
001111 12.5 101111 −3.5
010000 12 110000 −4
010001 11.5 110001 −4.5
010010 11 110010 −5
010011 10.5 110011 −5.5
010100 10 110100 −6
010101 9.5 110101 −6.5
010110 9 110110 −7
010111 8.5 110111 −7.5
011000 8 111000 −8
011001 7.5 111001 −8.5
011010 7 111010 −9
011011 6.5 111011 −9.5
011100 6 111100 −10
011101 5.5 111101 −10.5
011110 5 111110 −11
011111 4.5 111111 −11.5

tSCLK tPW

SCLK

tDH
tDS
___ ___
CSA, CSB

tDS tDH
09387-152

SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0

Figure 52. SPI Interface Read/Write Mode Timing Diagram

Rev. D | Page 17 of 29
ADL5202 Data Sheet

CIRCUIT DESCRIPTION
BASIC STRUCTURE The dc current to the outputs of each amplifier is supplied through
two external chokes. The inductance of the chokes and the
The ADL5202 is a dual, differential, variable gain amplifier, resistance of the load, in parallel with the output resistance of
with each amplifier consisting of a 150 Ω digitally controlled, the device, add a low frequency pole to the response. The para-
passive attenuator that is followed by a highly linear sitic capacitance of the chokes adds to the output capacitance of the
transconductance amplifier with feedback. part. This total capacitance, in parallel with the load and output
1/2 OF resistance, sets the high frequency pole of the device. Generally,
ADL5202
the larger the inductance of the choke, the higher its parasitic
VIN+ ATTENUATOR gm VOUT+ capacitance. Therefore, this trade-off must be considered when
VIN–
AMP
VOUT–
the value and type of the choke are selected. For an operation
frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 µH
LOGIC REF
chokes with a self resonant frequency (SRF) of 160 MHz or
higher are recommended (such as the 0805LS-102XJBB from
DIGITAL INPUTS Coilcraft). If higher value chokes are used, a 4 MHz zero, due to
09387-047

PARALLEL, SPI,
FAST ATTACK
UP/DOWN
the internal ac-coupled feedback, causes an increase in S21 of up
to 6 dB at frequencies below 4 MHz. The supply current of each
Figure 53. Simplified Schematic
amplifier consists of about 35 mA through the VPOS pin and
Input System 50 mA through the two chokes combined. The latter increases
The dc voltage level at the inputs of each amplifier is set by two with temperature at approximately 2.5 mA per 10°C. The total
independent internal voltage reference circuits to approximately choke current increases to 75 mA for high performance mode.
1.6 V. The references are not accessible and cannot be adjusted. Each amplifier has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the board,
Each amplifier can be powered down by pulling the correspond-
care should be taken to minimize the parasitic capacitance due to
ing power-up pin down to ground (logic low). When powered
the routing that connects the corresponding outputs together.
down, the total current of each amplifier reduces to 7 mA
To minimize the parasitic capacitance, a good practice is to avoid
(typical). The dc level at the inputs remains at approximately
any ground or power plane under this routing region and under
1.6 V, regardless of the state of the PWUPA or PWUPB pin.
the chokes.
Output Amplifier
Gain Control
The gain of the output amplifier is set to 22 dB when driving
The gain of each amplifier can be adjusted using the parallel control
a 150 Ω load. The input and output resistance of this amplifier
interface, the serial peripheral interface, or the gain up/down
is set to 150 Ω in matched condition. If the load or the source
interface. In general, the gain step size is 0.5 dB, but larger sizes
resistance is different from 150 Ω, the following equations can
can be programmed using the various interfaces, as described in
be used to determine the resulting gain and input/output
the Digital Interface Overview section. Each amplifier has a
resistances.
maximum gain of +20 dB (Code 0) to −11.5 dB (Code 63).
Voltage Gain = AV = 0.09 × (2000)//RL
The noise figure of each amplifier is approximately 7.5 dB at
RIN = (2000 + RL)/(1 + 0.09 × RL) maximum gain setting, and it increases as the gain is reduced.
S21 (Gain) = 2 × RIN/(RIN + RS) × AV The increase in noise figure is equal to the reduction in gain.
The linearity of the part measured at the output is first-order
ROUT = (2000 + RS)/(1 + 0.09 × RS)
independent of the gain setting. From −4 dB to +20 dB gain,
Note that at the maximum attenuation setting, RS, as seen by OIP3 is approximately 50 dBm into 150 Ω load at 200 MHz
the output amplifier, is the output resistance of the attenuator, (0 dBm per tone). At gain settings below −4 dB, OIP3 drops to
which is 150 Ω. However, at minimum attenuation, RS is the approximately 40 dBm.
source resistance that is connected to the input of the part.

Rev. D | Page 18 of 29
Data Sheet ADL5202

APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 54 shows the basic connections for operating the ADL5202.
A voltage between 4.5 V and 5.5 V should be applied to the VPOS
pins. Each supply pin should be decoupled with at least one low
inductance, surface-mount ceramic capacitor of 0.1 μF, placed
as close as possible to the device.
The outputs of the ADL5202 must be pulled up to the positive
supply with 1 μH RF chokes. The differential outputs are biased
to the positive supply and require ac coupling capacitors, pref-
erably 0.1 μF. Similarly, the input pins are at bias voltages of
about 1.6 V above ground and should be ac-coupled as well.
The ac coupling capacitors and the RF chokes are the principle
limitations for operation at low frequencies.
The digital pins (mode control pins, associated SPI and parallel
gain control pins, PM, PWUPA, and PWUPB) operate on a voltage
of 3.3 V.
BALANCED
SOURCE
RS
AC
2 2
To enable each channel of the ADL5202, the PWUPA or PWUPB
pin must be pulled high (1.4 V≤ PWUPA/PWUPB ≤ 3.3 V).
Taking PWUPA or PWUPB low puts the channels of the ADL5202
in sleep mode, reducing current consumption to approximately
7 mA per channel at ambient.
ADC DRIVING
The ADL5202 is a highly linear, variable gain amplifier that
is optimized for ADC interfacing. The output IMDs and noise
floor remain constant throughout the 31.5 dB gain range.
This is a valuable feature in a variable gain receiver where it is
desirable to maintain a constant instantaneous dynamic range
as the receiver range is modified. The output noise is 18 nV/√Hz,
which is compatible with 14- or 16-bit ADCs. The two-tone
IMDs are usually greater than −100 dB for −1 dBm into 150 Ω
or 2 V p-p output. The 150 Ω output impedance makes the task
of designing a filter for the high input impedance ADCs more
straightforward.
RS

CHANNEL A
GAIN CONTROL INTERFACE 0.1µF 0.1µF

3.3V
32

31
38

37

36

35

34

33
40

39

VOUTA–
PWUPA

GND
LATCHA

VINA–

VINA+

VOUTA+
FA_A/A2

UPDN_CLK_A/A1

UPDN_DAT_A/A0

0.1µF
1 30
CSA/A3 VOUTA–
RL BALANCED
2 29 LOAD
A4 VOUTA+
3 28 0.1µF
GAIN MODE A5 VPOS
0.1µF 1µH 1µH
INTERFACE 4 27
MODE1 VPOS
VPOS
5 26 0.1µF 0.1µF
MODE0 ADL5202 VPOS
6 EXPOSED 25
3.3V PM PADDLE VPOS 0.1µF
VPOS
7 24
GND VPOS
0.1µF
8 23
SIDO/B5 VPOS
UPDN_DAT_B/B0
UPDN_CLK_B/B1

9 22 0.1µF
SCLK/B4 VOUTB+
10 GS1/CSB/ 21
B3 VOUTB– 0.1µF
FA_B/B2

0.1µF
LATCHB

VOUTB+
VOUTB–
PWUPB
VINB+
VINB–
GS0/

BALANCED
GND

RL
LOAD
0.1µF
12

13

14

15

16

17

18

19

20
11

1µH 1µH

3.3V VPOS
0.1µF
CHANNEL B 0.1µF 0.1µF
GAIN CONTROL INTERFACE

RS RS
AC
2 2
09387-048

BALANCED
SOURCE

Figure 54. Basic Connections

Rev. D | Page 19 of 29
ADL5202 Data Sheet
5V

VREF
5V
1.0µH
1:3 0.1µF 0.1µF 56nH 33Ω

1/2 75Ω
50Ω VREF 4pF AD9268
ADL5202 33Ω
75Ω
AC
0.1µF 0.1µF 56nH
1.0µH
DIGITAL

09387-049
INTERFACE
5V

Figure 55. Wideband ADC Interfacing Example Featuring One-Half of the ADL5202 and the AD9268

Figure 55 shows one-half of the ADL5202 driving a two-pole, 0

SNR = 69dB
SFDR = 86dBc
100 MHz low-pass filter into the AD9268. The AD9268 is NOISE FLOOR = –108dB
–15 FUND = –1.035dBFS
a 16-bit, 125 MSPS analog-to-digital converter with a buffered SECOND = –89.17dBc
–30
wideband input, which presents a 6 kΩ differential input impe-

AMPLITUDE (dBFS)
dance and requires between a 1 V or 2 V input swing to reach –45

full scale. This example uses the 2 V p-p input. For optimum –60

performance, the ADL5202 should be driven differentially, –75

3 2
using an impedance transformer or input balun. –90 +
5 4 6
0
–105
–1
–2 –120
–3
–135
–4
INSERTION LOSS (dB)

–5 –150

09387-051
0 6 12 18 24 30 36 42 48 54 60
–6
FREQUENCY (MHz)
–7
–8 Figure 57. Measured Single-Tone Performance of the
–9 Circuit in Figure 55 for a 100 MHz Input Signal
–10
–11
–12 FUNDAMENTAL1 = –7.127dBFS
–13 0 FUNDAMENTAL2 = –7.039dBFS
2F1 – F2 = –91.818dBc
–14 –15 2F2 – F1 = –87.083dBc
–15 NOISE FLOOR = –109.57dB
09387-050

0 20 40 60 80 100 120 140 160 180 200 –30

FREQUENCY (MHz)
AMPLITUDE (dBFS)

–45
Figure 56. Measured Frequency Response of Wideband
–60
ADC Interface, as Depicted in Figure 55
–75
Figure 55 uses a 1:3 impedance transformer to provide the 150 Ω + F1 + F2
–90 2F2 – F1 2F1 – F2
2F1 + F2 2F2 + F1
input impedance of the ADL5202 with a matched input. The F2 – F1

outputs of the ADL5202 are biased through the two 1 μH –105

inductors, and the two 0.1 μf capacitors on the outputs decouple –120

the 5 V inductor voltage from the input common-mode voltage of –135

the AD9268. The two 75 Ω resistors provide the 150 Ω load to the –150
09387-052

ADL5202 whose gain is load dependent. The 56 nH inductors 0 6 12 18 24 30 36 42 48 54 60

FREQUENCY (MHz)
and 4 pF capacitor constitute the (100 MHz – 1 dB) low-pass
filter. The two 33 Ω isolation resistors suppress any switching Figure 58. Measured Two-Tone Performance of the
Circuit in Figure 55 for a 100 MHz Input Signal
currents from the ADC input sample-and-hold circuitry. The
circuit depicted in Figure 55 provides variable gain, isolation,
filtering, and source matching for the AD9268. Using this circuit
with the ADL5202 in a gain of 20 dB (maximum gain), an SNR
of 69 dB, and an SFDR performance of >86 dBc is achieved at
100 MHz, as shown in Figure 57.

Rev. D | Page 20 of 29
Data Sheet
An alternative narrow-band approach is presented in Figure 59.
By designing a narrow band-pass antialiasing filter between the
ADL5202 and the target ADC, the output noise of the ADL5202
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves by several decibels (dB) when including a reasonable
order antialiasing filter. In this example, a low loss 1:3 input
transformer is used to match the 150 Ω balanced input of the
ADL5202 to a 50 Ω unbalanced source, resulting in minimum
insertion loss at the input.
Figure 59 is optimized for driving some of the Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 8 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
that the ADC input acts like a real resistance at the target center
frequency.
In addition, the L6 inductor shorts the ADC inputs at dc, which
introduces a zero into the transfer function. The ac coupling
capacitors and the bias chokes introduce additional zeros into the
ADL5202
transfer function. The final overall frequency response takes on
a band-pass characteristic, helping to reject noise outside of the
intended Nyquist zone. Table 8 provides initial suggestions for
prototyping purposes. Some empirical optimization may be
needed to help compensate for actual PCB parasitics.
LAYOUT CONSIDERATIONS
The ADL5202 has two output pins for each polarity, and they
are oriented in an alternating fashion. When designing the board,
care should be taken to minimize the parasitic capacitance due
to the routing that connects the corresponding outputs together.
A good practice is to avoid any ground or power plane under
this routing region and under the chokes to minimize the
parasitic capacitance.
If the common-mode load capacitance including the capaci-
tance of the trace is > 2 pF, use parasitic suppressing resistors
at the device output pins. The resistors should be placed in
the output traces just after the crossover connections. Use 5 Ω
series resistors (Size 0402) to adequately de-Q the output
system without a significant decrease in gain.

5V

5V
1µH
1:3 1nF 1nF L1 L3 L5

1/2 75Ω AD9246

C2 C4
50Ω ADL5202 4pF 4pF CML L6 AD9640
75Ω AD6655
AC
1nF 1nF L1 L3 L5
1µH
DIGITAL

09387-053
INTERFACE
5V

Figure 59. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications

Table 8. Interface Filter Recommendations for Various IF Sampling Frequencies

Center Frequency 1 dB Bandwidth L1 C2 L3 C4 L5 L6
96 MHz 27 MHz 68 nH 15 pF 220 nH 15 pF 68 nH 150 nH
140 MHz 31 MHz 47 nH 11 pF 150 nH 11 pF 47 nH 82 nH
170 MHz 25 MHz 39 nH 10 pF 120 nH 10 pF 47 nH 51 nH
211 MHz 40 MHz 30 nH 7 pF 100 nH 7.5 pF 30 nH 43 nH

Rev. D | Page 21 of 29
ADL5202 Data Sheet

EVALUATION BOARD
The ADL5202 evaluation board is available with software to
program the variable gain control. It is a 4-layer board with a split
ground plane for analog and digital sections. Special care is
taken to place the power decoupling capacitors close to the
device pins. The board is designed for easy single-ended
(through a Mini-Circuits TC3-1T+ RF transformer) or
differential configuration for each channel.
EVALUATION BOARD CONTROL SOFTWARE
The ADL5202 evaluation board is configured with a USB-
friendly interface to program the gain of the ADL5202. The
software graphic user interface (see Figure 60) lets users select
a particular gain mode and gain level to write to the device and
also to read back data from the SDIO pin, showing the currently
programmed gain setting. The software setup files can be
downloaded from the ADL5202 product page at www.analog.com.

09387-054

Figure 60. Evaluation Control Software

Rev. D | Page 22 of 29
Data Sheet ADL5202
EVALUATION BOARD SCHEMATICS AND ARTWORK
09387-055

Figure 61. Evaluation Board Schematic

Rev. D | Page 23 of 29
ADL5202 Data Sheet
09387-056

Figure 62. RF Output Detail

Rev. D | Page 24 of 29
Data Sheet ADL5202

09387-057

Figure 63. Schematic for the USB Section of the Evaluation Board
Rev. D | Page 25 of 29
ADL5202 Data Sheet

09387-058
Figure 64. Evaluation Board Top Layer

09387-059

Figure 65. Evaluation Board Bottom Layer

Rev. D | Page 26 of 29
Data Sheet ADL5202
EVALUATION BOARD CONFIGURATION OPTIONS
Configuration Options for the Main Section
Table 9. Bill of Materials for Main Section
Components Function Default Conditions
C24 to C27, C51 Power supply decoupling. Nominal supply decoupling consists of a 0.1 µF C24 to C27, C51 = 0.1 µF (Size 0603)
capacitor to ground.
VPOS, 3V3 Power supply connections. VPOS, 3V3 (test loop red) installed
GND GND (test loop black) installed
DUT1 Evaluation device. Installed
INA+, INA− Input interfaces. The INA+ and INA− input SMA connectors are used to INA+ (SMA connector) installed
INB+, INB− drive the Channel A balun in a single-ended fashion. The INB+ and INB− INA− (SMA connector) installed
T1, T2, C18 to C23, input SMAs are used to drive the Channel B balun in a single-ended fashion. INB+ (SMA connector) installed
R8, R9, R20 to R29, The default configuration of the evaluation board is for single-ended INB− (SMA connector) installed
R88, R89 operation. T1, T2 = TC3-1T+ (Mini-Circuits)
T1 and T2 are 3:1 impedance ratio RF transformers that are used to transform C18 to C23 = 0.1 µF (Size 0603)
a 50 Ω, single-ended input into a 150 Ω balanced differential signal. R8, R9, R26 to R29 = 0 Ω (Size 0402)
C18 and C19 are balun decoupling capacitors. C20 to C23 are used for R20 to R25, R88, R89 = open
dc blocking purposes.
R20 to R29 are provided for generic placement of matching components.
R88 and R89 are populated to ground on one side of the transformer
primary, creating the 50 Ω single-ended input.
OUTA+, OUTA− Output interfaces. The OUTA+ and OUTA− output SMA connectors are used to OUTA+ (SMA connector) installed
OUTB+, INB− load the Channel A balun in a single-ended fashion. The default configuration OUTA− (SMA connector) installed
T3, T4, C36 to C45, of the evaluation board is for single-ended operation. The OUTB+ and OUTB+ (SMA connector) installed
R63 to R82, L1 to L4 OUTB− output SMAs are used to load the Channel B balun in a single- OUTB− (SMA connector) installed
VXA, VXB ended fashion. The default configuration of the evaluation board is for T3, T4 = TC3-1T+ (mini-circuits)
single-ended operation. C36 to C45 = 0.1 µF (Size 0603)
T3 and T4 are 3:1 impedance ratio transformers used to transform a 50 Ω, R63 to R72, R77 to R80 = 0 Ω
single-ended output into a 150 Ω balanced differential load. (Size 0402)
C40 to C43 are used for ac coupling. C44 and C45 are balun decoupling R73 to R76, R81, R82 = open
capacitors. L1, L2, L3, L4 = 1 µH (Size 0805)
R69 to R76 are provided for generic placement of matching components. VXA, VXB (test loop) installed
By removing R79 and R80 and installing 0 Ω at R81 and R82, the output is
converted to a differential output. L1 to L4 provide dc bias to the output
stages. R67 and R68 provide a connection to the 5 V power plane.
Optionally, R67 and R68 can be removed and the output stage biased
through the VXA and VXB terminals.
P1, P2, PWUPA, PWUPB, Power-up interface. The ADL5202 is powered up by applying a logic high P1 installed for enable
R30 (1.4 V ≤ PWUPA/PWUPB ≤ 3.3 V) to PWUPA and PWUPB from an external P2 installed for enable
source or by installing a shunt between Pin1 and Pin 2 of P1 andP2. PWUPA (SMA connector) installed
PWUPB (SMA connector) installed
R30 = open
A0 to A5, B0 to B5, Gain control interface. All of the gain control functions are fully controlled A0 to A5 (3-pin header) installed
LATCHA, LATCHB, PM, via the USB microcontroller by using the supplied software. Three-pin B0 to B5 (3-pin header) installed
MODE0, MODE1 headers allow for manual operation of the gain control, if desired. LATCHA (3-pin header) installed
R10 to R19, R31 to R62, The R31 to R34, R45, R46, R53, R54, and R84 to R87 resistors and the C28 to LATCHB (3-pin header) installed
R84 to R87, C35 and C47 to C50 capacitors allow for the generic placement of filter MODE0 (3-pin header) installed
C28 to C35, C47 to C50 components. MODE1 (3-pin header) installed
The R10 to R19, R31 to R62, and R84 to R87 resistors isolate the gain control PM (3-pin header) installed
pins from the microcontroller and provide current limiting. R10 to R19 = 1 kΩ (Size 0603)
R35 to R44 = 1 kΩ (Size 0603)
R47 to R52 1 kΩ (Size 0603)
R55 to R62 1 kΩ (Size 0603)
R31 to R34 = open
R45, R46 = open
R53, R54 = open
R84 to R87 = open
C28 to C35 = open
C47 to C50 = open

Rev. D | Page 27 of 29
ADL5202 Data Sheet
Configuration Options for the USB Section
Table 10. Bill of Materials for USB Section
Components Default Conditions
C7, C8 22 pF (Size 0603)
C13 1000 pF (Size 0603)
C2, C3, C4, C6, C10, C11, C12, C14, C16, C46 0.1 µF (Size 0402)
C9, C15 1 µF (Size 0402)
C1, C5 10 pF (Size 0402)
CR1 Green LED ( Panasonic LNJ308G8TRA)
P3 USB SMT connector (Hirose Electric UX60A-MB-5ST 240-0003-4)
R1, R2, R5 2 kΩ (Size 0603)
R6, 78.7 kΩ (Size 0603)
R7 140 kΩ (Size 0603)
R3, R4 100 kΩ (Size 0603)
R83 0 Ω (Size 0603)
U2 USB microcontroller (Cypress CY7C68013A-56LFXC)
U1 64 kB EEPROM (Microchip 24LC64-I/SN)
U3 Low dropout regulator (Analog Devices ADP3334ACPZ)
Y1 24 MHz crystal oscillator (AEL Crystals X24M000000S244)

Rev. D | Page 28 of 29
Data Sheet ADL5202

OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.23
PIN 1 5.90 0.18
INDICATOR PIN 1
31 40
INDICATOR
30 1

0.50
BSC 4.45
EXPOSED
PAD 4.30 SQ
4.25

21 10
20 11
0.45 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

05-06-2011-A
PKG-003438

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 66. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-10)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADL5202ACPZ-R7 −40°C to +85°C 40-Lead LFCSP_WQ, 7” Tape and Reel CP-40-10
ADL5202-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09387-0-1/17(D)

Rev. D | Page 29 of 29