IMPACT OF TEMPERATURE ON

SCHOTTKY BARRIER MOSFET

A major project report submitted Impartial
Fulfillment of the Requirements For the
award of the degree of

BACHELOR OF TECHNOLOGY
In
Electronics and Communication Engineering
by
Nikhil Yadav Sameer Mansoori Lucky Mayank Athwal
(09614802820) (12414802820) (08014802820) (08514802820)

Under the Supervision of

Ms.Swati Sharma, Assistant Professor

to

MAHARAJA AGRASEN INSTITUTE OF

TECHNOLOGY SECTOR 22, ROHINI, DELHI
Affiliated to
GGSIPU University, Dwarka, Delhi

Dec,2023
 CERTIFICATE

Certified that Nikhil Yadav(enrollment no.09614802820), Sameer Mansoori

(enrollmentno.12414802820), Lucky(enrollment no. 08014802820),Mayank Athwal
(enrollment no.08514802820) has carried out the minor project work presented in
this report entitled “IMPACT OF TEMPERATURE ON SCHOTTKY
BARRIER MOSFET” for the award of Bachelor of Technology in Electronics
and Communication Engineering from Maharaja Agrasen Institute of
Technology affiliated to GGSIP University, Delhi under my/our supervision. The
report embodies results of original work and studies as carried out by the students
themselves.

Prof. (Dr.Sunil Mathur) (Ms.Swati Sharma)

Professor & HOD, ECE Assistant Professor, ECE

Date:

ii
 MOSFET BASED BIOSENSORS

This project presents a Fire Detection, Alarm, and Prevention System utilizing
Arduino, a flame sensor, relay, and pump. The Arduino microcontroller, integrated
with a flame sensor, continuously monitors the environment for potential fire
hazards.

Upon detection, the system triggers an alarm to alert occupants and authorities. The
relay interfaces with external devices, such as a pump, initiating the dispensing of a
fire-suppressing agent for proactive fire prevention.

The modular design allows customization for diverse applications. The user-
friendly Arduino interface facilitates system configuration and monitoring.

This affordable and scalable solution enhances fire safety in various settings,
providing real-time detection, prompt alarms, and preventive measures to minimize
the impact of fire-related incidents.

The system's adaptability makes it suitable for implementation in residential,

commercial, and industrial environments, contributing to overall safety and
emergency response capabilities.

3
ACKNOWLEDGEMENT

This work could be possible due to the guidance and support of many people. I
express my sincere gratitude to all those who contributed to the successful
completion of this project. First and foremost, I would like to thank my supervisor
for their guidance, support, and invaluable insights throughout the development
process.

I extend my appreciation to the academic staff whose teachings and mentorship

have provided a solid foundation for this project. Special thanks to [Name], [Title],
for their expertise and constructive feedback.

I would like to acknowledge the contribution of my peers and colleagues who

provided assistance and encouragement, fostering a collaborative and stimulating
environment.

Furthermore, I am grateful to my family for their unwavering support and

understanding during the challenges of this undertaking.

Lastly, I appreciate the open-source community for providing resources and tools
that significantly contributed to the realization of this project.
This project would not have been possible without the collective efforts and
encouragement from everyone involved. Thank you all for your invaluable
contributions.Most of all, I would like to thank God for everything especially His
love and grace

4
TABLE OF CONTENTS

1. ABOUT BIOSENSORS

2. ABOUT MOSFET

3. MOSFET BASED BIOSENSORS

4. INTRODUCTION

5. DIELECTRIC-MODULATED GATE STACK SOURROUNDING TRIPLE GATE

MOSFET FOR APPLICATION AS BIOSENSOR

6. DESCRIPTION OF STRUCTURE

7. MATHEMATICAL MODELLING

8. ADVANTAGES AND LIMITATIONS

9. CONCLUSION

5
CHAPTER1: INTRODUCTION

This chapter illustrates the significant background information about the invention
of Metal Oxide Semiconductor Field Effect Transistor(MOSFET)and its scaling. A
concise review of MOSFET devices developed and investigated for more than last
five decade is also presented. In this chapter, the state of art of the multi gate
MOSFET devices and challenges in nano scale MOSFETs has also been presented.
The concept of a device in which, the current through a semiconducting channel
could be controlled by a perpendicular electric field was originally proposed by
Lilienfeld in 1930 [Lilienfeld30] as a device namely “Method and apparatus for
controlling electric currents”. In today’s electronics, this device is known as Field
Effect Transistor (FET). But due to the presence of very high-density surface states
which traps free carriers and shields the semiconductor underneath the surface from
the gate field, the device performance was poor and could not be available
commercially [Schwierz10]. However, this was the first forward step towards
microelectronics after the vacuum tube devices. After the initial start by Lilienfeld,
the first amazing technological invention in the field of semiconductor resulted as
“Bipolar Junction Transistor” at “Bell Labs” by a team of three scientist John
Bardeen, Walter Brattain, and William Shockley in 1947 [Cressler16]. This three-
terminal semiconductor transistor was a versatile invention. The invention of BJT
resulted in the form of the first transistor based computer TRADIC (Transistor
digital Computer) in 1954 which was faster, reliable and much smaller in size than
the vacuum tubes based first electronic computer ENIAC (Electronic Numerical
Integrator And Computer) in 1943.
The switching losses in BJT which is a bipolar device meaning conduction carried
out simultaneously by electrons and hole is very high with very poorperformance.
However, as an amplifier, it is an ultimate semiconductor device. The Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) is the central component of all
modern electronic gadgets and Integrated Circuit’s (IC’s). After the invention of
MOSFET, the first IC and first CMOS (Complementary Metal Oxide
Semiconductor) was demonstrated in 1961 and 1963.
Integrated Circuit had advanced with doubling the number of on-chip MOSFETs in
every generation, reducing the physical device size. Scaling is the major factor
behind it. It has attracted many possibilities of novel structures and MOSFET
devices. But scaling poses many challenges on device performance as it enters into
the nanometer regime. It causes threshold voltage variation, increases the body-bias
effect and many other detrimental effects.
Also, in short channel device, the fabrication complexity increases as it becomes
difficult to form a steep source/drain and channel junctions. Thus, to conquer these
challenges, novel device architectures are needed in order to guarantee the ultimate
scaling in device dimensions simultaneously maintaining the performance expected
from the scaling.

1
The trend of MOSFET scaling is shown in figure 1.01. However, the trend
of miniaturization and its associated benefits will continue while the
performance can be addressed depending on the individual application,
sustained by the incorporation into devices of new materials, and the application
of new transistor concepts.

Figure 1. Trend of Moore’s law for MOSFET scaling (gate length scaling) over
the decades

1.1 MOSFET:
A Metal-oxide Semiconductor(silicon) Field-Effect Transistor, also known as
MOSFET is an essential electronic device that is widely used in digital andanalog
devices. It is a semiconductor device that controls electrical current with
high
accuracy. It is used to switch or amplify voltage in a circuit.

A transistor consists of three layers: a metal gate, an oxide insulator, and a

semiconductor material(semiconductor). The metalgate is usually made of metal
and is connected to the semiconductor through a thin insulating material (usually
silicon dioxide). The semiconductor material (usually silicon) forms the
current channel.
It has four terminals named Source, Drain, Gate, and Substrate (body). But
assource and substrate are connected internally, Mosfet is considered a three-
terminal device.

1
1.2 SHORT CHANNEL EFFECTS:DEVICE MINIATURIZATION /SCALI NG CHALLENGES

As the co-founder of the Intel Corporation Gordon E. Moore predicted that

the densityoftransistors ona chip would be doubled approximately
ineveryeighteen months and this is consistently true since 1970. But this can be
made possible by the reduction in transistor size as mentioned above in the scaling
section. Due to the reduction in MOSFET dimensions, the source to channel and
drain to channel depletionwidthbecomes large and comparable with the
lengthof the channeland thusthe gate
losescontroloverthechannelresultinginnumeroustypesofadverse effect in the device,
which alters the device electrical characteristics.

The main adverse effects of scaling are discussed

1.2.1 THRESHOLD VOLTAGE DEGRADATION AND HIGHER SUBTHRESHOLD CONDUCTION

In general, the dependency ofthe threshold voltage ofa MOSFET should be least on
the channel length. But as the length of the channel reduces, charge sharing
between the source and drain region increases, that leads to significant field
penetration from the drain-to-source region . The potential barrier at the source is
lowered,resultinginincreasedflowofcarriers,givingrisetohighersub-threshold drain
current. Consequently, the sub-threshold leakage occurs. This results in the
reduction of the threshold voltage. Furthermore, the field penetration lines
from drain affect the concentration of carriers in the channel and degrade the
device threshold voltage. Thus the threshold voltage roll-off of MOSFET is
generally described as the reduction in threshold voltage with the reduction
in channel length. Figure 1.03 shows the schematic view of the depletion
region in the channel for long and short channel devices.

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1.2.2 DRAIN INDUCED BARRIER LOWERING (DIBL)

Drain Induced Barrier Lowering is an undesirable phenomenon which occurs in

short channel devices. When the channel is long in MOSFET, the horizontal and
vertical electric fields have distinct effects on device electrical characteristics. In
long channel devices, the potential barrier between source and drain is
mainly controlled by the applied gate to source voltage.

Figure2(a)Schematic view of the long channel and short channel device,

(b)Schematic illustration of DIBL

1
CARRIERVELOCITYSATURATION(IMPACTIONIZATION AND
HOT CARRIER EFFECT)

The velocity of majority carriers in the channel saturates at high electric field due
to mobility reduction. To maintain the same electric field in short channel
MOSFET as in long channel MOSFET constant field scaling is a suitable
approach because in constant field scaling all parameters are equally scaled
to maintain the same electric fields. However, all the scaling trends may not follow
through constant field scaling techniques [Taur98]. For example, the oxide
thickness is more scaled as compared to supply voltages. This results in an
increased electric field in the nano scale MOSFET. At high electric field in short
channel MOSFETs, various scattering mechanism like phonon scattering and
coulomb scattering occur. The velocity of carriers is directly proportional to the
electric field (v=μE).At the high electric field, the carriers velocity reaches up
to a critical value and at that condition, the velocity of the carriers tends to
saturate. But, in a nano scale MOSFET, velocity saturation is observed at much
lower drain voltages, resulting in a decreased ON current which reduces
transconductance and degrades other analog/RFperformance of the device. The
graphical representation of carrier velocity saturation is shown in figure 3.

Figure.3Velocity of the carrier verses electric field for silicon

1
GATEOXIDELEAKAGE

As the device dimension reduces the oxide thickness is also scaled down. Silicon
Dioxide (SiO2) and Aluminium Oxide (Al2O3) are good insulators used as a gate
dielectric in MOSFET. But, the thickness of the oxide can not be reduced
arbitrarily because for the gate oxide thickness less than 2 nm, the carrier
can surmount the barrier of silicon and oxide interface. After surmounting the
barrier through tunnelling they will be collected by the gate terminal
causing an undesirable gate current or oxide leakage current. The graphical
representation of oxide tunnelling has been shown in figure 4. To minimize
these setbacks some device engineering techniques has been proposed and
investigated.

Figure4Schematicillustrationofchannellengthmodulationeffects

INCREASEDSOURCE/DRAIN SERIESRESISTANCEIN NANOSCALE

MOSFETS

Apart from above discussed short channel effects, high parasitic source/drain
resistanceoriginatesinshortchannelMOSFETsduetothesmallercontactareaof the
source and drain [Chen13]. Along with the reduction in channel length the
thickness of the device also reduces to maintain the W/L ratio of MOSFET and
thus the series source resistance (RS) and series drain resistance (RD)
becomes noticeable fraction of the channel resistance (Rch) and can no longer be
neglected.

1
CHAPTER2:STRUCTUREDESIGN
GATEALLAROUNDMOSFET

In Gate All Around MOSFET (GAA)(also called Surrounding Gate MOSFET

or Wrap Around Gate MOSFET) the gate wraps around a pillar/slab of
semiconductor, which may be wide or narrow, rectangular, square, or circular, and
of any of the orientations like triangular. Studies show that this extra degree
of electrostatic confinement permits the GAA FET to be scaled about 50% further
than the DG-FET, and this trend is confirmed experimentally by Leobandung et .
This property may also be used to relax the thickness requirements on the silicon
and oxide layers for a given gate length. The main advantage of the GAA
approach is extremely high packing density for the case of vertical structures
which is good for memory, whereas the main disadvantage is the very
limited current-carrying capability per device. However, the current density
can be increased using the stacking of nano wire in a MOSFET structure .
Depending upon the geometry, various types of gate-all-around structures are
described below.

RECTANGULARGATEALLAROUNDMOSFET

The three-dimensional and cross-sectional view of Rectangular Gate All Around

(RecGAA) MOSFET is shown in figure 1.15. Here rectangular substrate material is
completely surrounded by the gate of rectangular shape. Rectangular Gate-All-
Around (Rec GAA) offers excellent electrostatic control of the channel and
robustness against SCE in comparison to Double Gate (DG) and Fin-FET
structure. The Rectangular GAA device provides higher current drivability, ideal
sub threshold swing and mobility enhancement at a certain crystal orientation.

Figure5Three-Dimensional view of Rectangular GAA MOSFET

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TRIANGULAR GATE ALL AROUND MOSFET

The three-dimensional representation of triangular GAA is shown in figure 6 (a).

Figure 6 (b)shows the cross-sectional view oftriangularGAA. It canbe observed
fromfigure6(a)thatthetriangularshapesemiconductorslabissurroundedbythe
triangular shape gate.
Local volume inversion in corners and gate coupling occur and so-called corner
effects increase the low field mobility in the triangular GAA MOSFET
[Moselund06]. Triangular cross-section device shows a significant enhancement of
the extracted carrier mobility (up to ~1000 cm 2 /Vs). This effect enhances
conduction in the sharp corners of triangular GAA MOSFET. The major benefit
of this structure is that it is fabricated in a relatively low area compared to
rectangular GAA MOSFET.

Figure6Structure of Triangular GAA MOSFET

(a) 3Dview, (b) Cross-sectional view

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CYLINDRICALGATEALLAROUNDMOSFET

The Cylindrical Gate All Around (Cyl-GAA) MOSFET was proposed by J.

P. Colinge in 1990. In Cylindrical Gate All Around MOSFET, the cylindrical
semi conductor pillar is surrounded by an oxide followed by a metal gate on top of
the oxide. Figure 7 shows the three-dimensional and cross-sectional view
of cylindrical Gate All Around MOSFET.
The sidewalls of the semiconductor pillar act as a channel region for
inversion
mode MOSFET. Cylindrical Gate All Around (CGAA) MOSFET is one of
the most promising and attractive structures for future Complementary Metal
Oxide Semiconductor (CMOS) technology due to its ultimate short-channel
effects immunity, best gate controllability, suppressed floating body effects,
improved carrier transport and excellent CMOS compatibility.

Figure7Structure of Cylindrical GAA(CGAA) MOSFET

cylindrical GAA MOSFETs suppress corner effects. The downscaling of device

dimensions has been the primary factor leading to improvements in IC
performance and cost, which contributes to the rapid growth of the semi-conductor
industry.

1
 the pillar is made-up of silicon and surrounded by SiO2 layer

Cylindrical Gate All Around (CGAA) MOSFET is one of the most

promising and attractive structures for future Complementary Metal Oxide
Semiconductor (CMOS) technology due to its ultimate short-channel effects
immunity,.

best gate controllability.

suppressed floating body effects.

improved carrier transport, and excellent CMOS compatibility.

Figure8. Cylindrical GAA MOSFET considered in this paper.

(a) 3-Ddevicestructure, (b) Cross section.

2
CHAPTER3:ATLAS3DSIMULATOR

Benefits of TCAD
Reduce Development Costs
Reduce the time and manufacturing cycles spent to develop semiconductor
technologies
ITRS roadmaps indicates that TCAD simulation can reduce the costs
during development cycles by ~30%

Visualize Internal Physical Processes

Using simulation, you can see ‘inside” the device. Experimental
measurements tell you what happens, but not why it happens. TCAD can tell
you why.
For example:

Reverse voltage characterization on a power device tells you what

happens at high reverse biases. The device experiences reverse
breakdown at a specific voltage.
A TCAD simulation can also replicate the reverse current-voltage
curve, but also can also tell you why the device is experiencing
breakdown. In TCAD the engineer can “see inside” the device
and identify what region within the semiconductor first succumbs
to breakdown due to high impact ionization generation.

2
Design Technology Co-Optimization(DTCO)

TCAD is part of a DTCO flow which improves designs across

multiple domains – Layout, Process, Device, SPICE, and RC extraction.
A full TCAD to SPICE flow, in an integrated DTCO environment,
delivers clear actionable results for circuit design optimization.

Virtual Experimentation

Experiment with cause and effect: Change the device design (layout),
technology (semiconductor process steps) or device operation condition
(biasing, etc.), and understand and improve device performance.
Experiment with theories in TCAD: control the impact of various physics in
the device via model settings and coefficients. If theory as applied to
simulation matches the measured result, you may have found the root cause
and gained physical understanding of device performance.

Communicate Device Complexities Clearly

Semiconductor device design, and processing of semiconductors is a

complex task. Engineers must work collaboratively to solve problems,
explain issues and opportunities to a variety of colleagues with varied
technical expertise.

Utilizing TCAD can clearly communicate device and process changes;

communicating potential performance improvements with clarity while
minimizing manufacturing cycle times.

x
 ATLAS2D/3DSIMULATOR

Basic Principles: What is ATLAS?

ATLAS is a 2D and 3D Device Simulation Framework.

ATLAS solves the fundamental physical equations describing the dynamics

of carriers in semiconductor devices for arbitrary device structures.
ATLAS predicts terminal characteristics of semiconductor devices for
steady state, transient, and small signal AC stimuli.
ATLAS gives insight into the internal characteristics of semiconductor
devices (e.g. carrier densities, fields, ionization/ recombination
rates, current densities etc.)

Basic Principles: Create a Structure for Simulation

x
 ATLAS Inputs and Outputs

3.2.2 ATLAS Framework Architecture

x
 CHAPTER 4: RESULT AND DISCUSSION

Fig. the variation in transconductance

Fig. 1(a) shows 1(a): gm Fig b: Drain current ids
Transconductance gm Fig.(b) demonstrate
varies with gatethevoltage
drain current
vgs at
by varying the gate voltage Vgs for GaN material. diferent gate voltage for GaN
T=250K showsvaries with
better gate voltage
transconductance material. GaN has an advantage over Si in that
Than other tempratures because of its higher drain it suppresses the leakages, supports a more
current. The useof AL2O3 as a dielectric increases the extensive drive current, and eases the
constraint of the device cooling . It can also be
drain current as itreduces leakages. gm can be
interpreted that T=450K shows a better drain
current than other temperatures because of
AL2O3 as the dielectric material.
Since its energy barrier creation is
lower as compared with SiO2, the production
formulated as: of carriers is faster in AL2O3, resulting in a
higher drain current .
In addition, the nebulous nature of AL2O3
makes it highly stable, which creates further
improvement in structure.

x
Fig. 2(a) Variation of drain current (Ids) Fig. (b) Output conductance (gd)
with drain voltage (Vds) variation with drain voltage (Vds)
Fig. (b) validates output conductance gd variation with drain voltage V
Fig. 2(a) validates the drain current Ids Output
variation with the drain voltage Vds for GaN conductance gd can be formulated as:
material. As seen from fig.
GaN material show a higher drain current than
Fig. 6(a) validates the drain current Ids
Si material. This is due to the more
variation with the drain voltage Vds for GaN
comprehensive bandgap and supporting larger
and Si devices. As seen from fg.
drive current property of GaN. It can be
GaN devices show a higher drain current than
interpreted from the fig. That T=250K conducts
Si devices. This is due to the more
a better drain current than other tempratures.
comprehensive bandgap and supporting larger
This owes to the use of AL2O3 as a dielectric
drive current property of GaN. It can be
which gives better controllability of the channel
interpreted from the fg. That DE-HK-GaN-
and reduces leakage current .
SNWFET conducts a better drain current than
GaN-SNWFET. This owes to the use of HfO2
as a dielectric which gives better controllability
of the channel and reduces leakage current

x
 Fig .3(a) Demonstrate subthreshold (SS) for diverse Fig .(b) Threshold voltage for
divrse temperature temperature
Fig. 3(a) shows subthreshold swing (SS) for various tempratures. The subthreshold swing is the ratio of variation in gate voltage (Vgs) for a decad
and can be formulated as:
Fig.(b) shows the threshold voltage of devices
at different tempratures . It can be observed that
the Vth of GaN-based material is lower as
compared to Si material. The variation in
temprature results in a change of threshold
voltage as the temprature increased threshold
voltage is getting reduced voltage . The
performance of T=250K
at diverse tempratures is enlisted in. the drain

Fig. 4(a) Cut- off frequency (fT) for different

temperatures Fig .(b) Gate Capacitance for
Different temperatures

Fig. 4(a) shows variation Fig

.(b) The total gate capacitance CGG variation with
in cutof frequency (fT) applied
with gate voltage Vgs for gate voltage Vgs for GaN material in
Tempratures(T=250K, T=300K, T=350K, T=400K,
GaN material. The higher T=450K) is shown in Fig. 4(b).
cutof frequency makes CGG is defned as the
sum of the gate to source capacitance and gate to drain
the device suitable for capacitance. The higher value of these capacitances
high-frequency hinders device switching by raising the turn-on delay
applications. fT can be time.
T=250K exhibits higher CGG than other
evaluated from the ratio tempratures but ofers a desirable high cutof frequency due
of transconductance gd to much higher transconductance
and total gate capacitance x
(CGG). T=450K shows
Fig .5(a) (a) MTPG for contemplated different temperatures (b) UPG for contemplated different temperatures
Fig. 5(a) exhibits the Maximum
transducer power
gain (MTPG) for different tempratures.
T=450K shows the highest value of MTPG
because of high on-current and high-power gain.
The high
value of MTPG of GaN-based material makes
it appropriate
for high-power applications .
x
Fig. (b) validates the Unilateral Power
Gain (UPG) for
Different temperatures . UPG leads the
desirable maximum power transfer. It
manifests that T=450K has higher unilateral
power gain than other
temperatures and makes the device appropriate
for application
that requires maximum transfer of power
from input to output .
Fig .6 Contour plot of Electric field for (a) T=250K (b) T=300K (c) T=350K
(d) T=400K (e) T=450K
x
Fig. 6 defines Electric field contour plot for (a) T=250K (b) T=300K (c) T=350K (d) T=400K
(e) T=450K with Vgs = 0.1 V and Vds = 0.2 V. As analyzed from the fig. the T=450K shows
the lowest electric field. The reduced electric field in the temprature results in better immunity
from SCEs and hot carrier reliability. GaN material in T=450K elevated electron mobility and
thus reduces electric field. The use of GaN material Reduces drain side electric field and hot
carrier effects.

x
x
Fig .7 Contour plot of E-Mobility for (a) T=250K (b) T=300K (c) T=350K
(d) T=400K (e) T=450K

Fig. 7 defines Electric mobility contour plot for (a) T=250K (b) T=300K (c) T=350K (d) T=400K
(e) T=450K at Vgs = 0.1 V and Vds = 0.2 V. Electron mobility is an essential parameter for
semiconductor material. The higher value of mobility leads to better device performance, with
other parameters kept constant.
T=450K shows better electron mobility as compared to other temperatures owing to its structure.

x
CHAPTER 4: CONCLUSION

The impact of temperature on Schottky barrier MOSFETs involves changes in carrier mobility,
threshold voltage, and leakage current. Elevated temperatures generally result in increased
electron mobility, potentially improving device performance. However, it can also lead to
higher leakage currents due to enhanced thermal generation of carriers. Understanding these
temperature effects is crucial for optimizing Schottky barrier MOSFET designs for
specific applications.

x
CHAPTER 5: REFFERENCE

International technology roadmap for semiconductors (ITRS), 2014 [Online]

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Depleted, Surrounding-Gate MOSFET’s”, IEEE Electron Device Letters, vol. 18, no. 2, pp. 74-76,
1997.
[Colinge90] J. M. Colinge, M. Gao, A. R. Rodriguez, H. Maes, and C. Claeys, “Silicon-on-Insulator
‘Gate-All-Around Device,” in Proceedings of International Electron Devices Meeting, pp. 595-
598,
1990.
[Pratap14a] Y. Pratap, P. Ghosh, S. Haldar, R.S Gupta, and M. Gupta “An analytical sub threshold
current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the inluence of device
design engineering,” Microelectronics Journal, vol. 45, no. 4, pp. 408–415, April 2014.
[Pratap 14b] Y. Pratap, S. Haldar, R.S. Gupta, and M. Gupta “Performance Evaluation and Reliability
Issues of Junctionless CSG MOSFET for RFIC Design” IEEE Trans. Device and Material Reliability,
vol. 14, no. 1, pp. 418–425, March 2014.
J. M. Colinge, M. Gao, A. R. Rodriguez, H. Maes, and C. Claeys, “Silicon-on-Insulator ‘Gate-All-
Around Device,” in Proceedings of International Electron Devices Meeting, pp. 595-598, 1990.
C. Li, Z. Yiqi, and Han Ru, “New analytical threshold voltage model for halo-doped
cylindrical surrounding-gate MOSFETs,” Journal of Semiconductor, vol. 32, no.7, pp. 1–8, 2011.
J. D. Cressler, “Silicon Earth: Introduction to Microelectronics and Nanotechnology”, CRC Press,
2016.
R. H. Dennard, F. H. Gaensslen, L. Khun, and H. N. Yu, “Design of micron switching devices”, IEEE
Electron Device Meeting (IEDM), vol. 18, pp. 168-170, December 1972.
R. Gautam “Analytical modeling and simulation of cylindrical gate all around MOSFET: reliability
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x