Faculty of Engineering and Technology

Electrical Engineering Department

EED220: Logic Design

Lecture 8
Gate-level Minimization
Mostafa Salah, Ph.D.
mostafa.abdulkhalek@fue.edu.eg
Contents
• Product‐of‐Sums Simplification
• SOP/POS Implementation
• Don’t‐Care Conditions
• NAND/NOR Implementation
• Other Two-level Implementation
• AOI
• OAI
• XOR Gate
• Tristate Gate
• References

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 Product of Sum Simplification
• Mark the empty squares by 0’s and combine them into valid adjacent
squares, obtain a simplified sum-of-products expression of the
complement of the function F’ . Use DeMorgan’s theorem to obtain POS.

Example: F (A, B, C, D) = (0, 1, 2, 5, 8, 9, 10)

From the map

F’ = AB + CD +BD’
F = (F’)’ = (AB + CD +BD’)’
= (A’ + B’)(C’ + D’)(B’ + D)

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Don’t Care Conditions
• A don’t-care term is a combination of variables whose logical value
is not specified.
• Thus, an X inside a square in the map indicates that we don’t care whether the value of
0 or 1 is assigned to F.

• When simplifying the function, we can choose to include each don’t-care term with
either the 1’s or the 0’s, depending on which combination gives the simplest
expression.

• In simulation, an X value can result from two or more sources driving

a signal simultaneously, or the stable output of a flip-flop not having
been reached.
• In synthesized hardware, however, the actual value of such a signal
will be either 0 or 1 but will not be determinable from the circuit's
inputs.
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 Don’t Care Conditions
Example: F(w, x, y, z) = (1, 3, 7, 11, 15),
d(w, x, y, z) = (0, 2, 5)
• A group will cover m3, m7, m11, and m15.
• m1 can be covered by two ways

First Solution: Assuming Second Solution: Assuming

m0 and m2 as 1’s m5 as 1.

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Other Simplification Methods – Quine-McCluskey method
• The K-map method breaks down
beyond six variables.
• The Quine-McCluskey method, also
known as the method of prime
implicants, find the minimized
representation of any Boolean
expression by a systematic
procedures of applying the uniting
theorem.

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Other Simplification Methods – Espresso
• The number of prime implicants, unfortunately, grows
quickly as the number of input increases.
• Espresso is a program developed at University of California at
Berkeley as a logic minimization tool. It combines many of the
best heuristic techniques, such as mini and presto.

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SOP/POS Implementation
• The gate-level implementation of the simplified expressions
F (A, B, C, D) = B’D’ + B’C’ + A’C’D = (A’ + B’)(C’ + D’)(B’ + D)

F = B’D’ + B’C’ + A’C’D F = (A’ + B’)(C’ + D’)(B’ +D)

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NAND/NOR Implementation
• A gate or set of gates is universal if it can be used to construct
any Boolean function.
• The set {AND, OR, NOT} is universal.
• NAND gate is universal.
• NOR gate is universal.

• Digital circuits are frequently constructed with NAND or NOR

gates rather than with AND and OR gates.
• NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic
families.
• The conversion from Boolean functions given in terms of AND, OR,
and NOT into equivalent NAND and NOR logic diagrams.
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 NAND Circuits
• The implementation of Boolean functions with NAND gates requires
that the functions be in sum-of-products form.
• The complement operation is obtained A F A F
from a one-input NAND gate that
F = A’
behaves exactly like an inverter. F = (A.A)’ = A’

A F A F
• The AND operation requires two NAND B B
gates. The first produces the NAND
F = AB F = ((AB)’)’ = AB
operation and the second inverts the
logical sense of the signal.
A
A F
• The OR operation is achieved through a F
NAND gate with additional inverters in B
F=A+B B
each input.
F = (A’ . B’)’ = A + B
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NAND Circuits
• To facilitate the conversion to NAND logic, it is convenient to define an
alternative graphic symbol for the gate.
• It is possible to represent a NAND gate by an OR graphic symbol that is
preceded by a bubble in each input.

A A
F B F
B
C C
F = (ABC)’ F = (A’ + B’ + C’) = (ABC)’

AND - Invert Invert - OR

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 NAND Circuits
Example: F = AB + CD

1- Implement the function 2- AND gates are replaced by 3- Invert-OR graphic symbol
with AND and OR gates NAND gates, OR gate is replaced replaced by NAND gate.
by Invert-OR graphic symbol.

F = ((AB)‘.(CD)‘)‘ = AB + CD

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 NAND Circuits
Example: F(x, y, z) = (1, 2, 3, 4, 5, 7)
1- Simplify the function
F = xy’ + x’y + z

2- Implement the function

with AND and OR gates 3- AND gates are replaced by NAND
gates, OR gate is replaced by Invert- 4- Invert-OR graphic symbol
OR graphic symbol. replaced by NAND gate.
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NAND Circuits
Exercise
• F(w, x, y, z) = w(yz + x) + xy’
• F(w, x, y, z) = (wx’ + w’x)(y + z)

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 NOR Circuits
• The NOR operation is the dual of the NAND operation.
• The implementation of Boolean functions with NOR gates requires that the
functions be in product-of-sum form.
• The complement operation is obtained A F A F
from a one-input NOR gate that behaves F = A’
exactly like an inverter. F = (A+A)’ = A’
A
• The AND operation is achieved through a A F F
NOR gate with additional inverters in each B
B
input. F = AB
F = (A’ + B’)’ = AB

• The OR operation requires two NOR

gates. The first produces the NOR A F A F
operation and the second inverts the B B
logical sense of the signal.
F=A+B F = ((A + B)’)’ = A + B
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NOR Circuits
• To facilitate the conversion to NOR logic, it is convenient to define an
alternative graphic symbol for the gate.
• It is possible to represent a NOR gate by an AND graphic symbol that is
preceded by a bubble in each input.

A A
F B F
B
C C
F = (A + B + C)’ F = (A’ B’ C’) = (A + B + C)’

OR - Invert Invert - AND

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 NOR Circuits
Example: F = (A + B)(C + D)E

1- Implement the function 2- OR gates are replaced by NOR

3- invert-AND graphic symbol
with OR and AND gates gates, AND gate is replaced by
replaced by NOR gate.
invert-AND graphic symbol.

F = ((A + B)‘+(C + D)‘ + E‘)‘ = (A + B)(C + D)E

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NOR Circuits
Exercise
• F(w, x, y, z) = (wx’ + w’x)(y + z’)

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Other Two-Level Implementation
• AND–OR–INVERT Implementation
• The two forms, NAND–AND and AND–NOR, are equivalent and can be treated together. Both
perform the AND–OR–INVERT function, Example: F = (AB + CD + E)’

AND - NOR AND - NOR NAND - AND

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Other Two-Level Implementation
• OR–AND–INVERT Implementation
• The OR–NAND and NOR–OR forms perform the OR–AND–INVERT function, as in
Example: F = [(A + B)(C + D)E]’

OR - NAND OR - NAND NOR - OR

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Other Two-Level Implementation
Summary
Nondegenerate Form Implement the
Simplify F’ to: To Get:
(a) (b) Function
AND–OR– SOP (Combine 0’s
AND–NOR NAND–AND F
Invert from K-map)
OR–AND– POS (Combine 1’s
OR–NAND NOR–OR F
Invert from K-map)

Notes:
• 7451 is TTL chip: dual 2-wide 2-input AND-OR-invert gate
• The complete guide to the TTL chips and their datasheets
https://en.wikipedia.org/wiki/List_of_7400-series_integrated_circuits

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 Other Two-Level Implementation
Example: Implement the function F(x, y, z) = (0, 6) with
the four 2-level forms listed in Table

• Combine 0’s from map

→ F’ = x’y + xy’ + z → F = (x’y + xy’ + z)’
• Combine 1’s from map
→ AND–OR–INVERT
→ F = x’y’z’ + xyz’ → F’ = (x + y + z)(x’ + y’ + z)
→ OR–AND–INVERT

AND - NOR NAND - AND OR - NAND NOR - OR

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Other Two-Level Implementation – Example
Example: F = A + BC’ + B’CD

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Other Two-Level Implementation – Example
Example: F = (A + B + C)(A + B’ + C’)(A + C’ + D)

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XOR Gate – Revisited
• The exclusive-OR (XOR), denoted by the symbol Ꚛ, is a logical operation
that performs the following Boolean operation:
x Ꚛ y = xy’ + x’y
• XOR is equal to 1 if its input differ in value, but not when they are equal.

• The exclusive NOR (XNOR), also known as equivalence, performs the

following Boolean operation:

(x Ꚛ y)’ = xy + x’y’
• XNOR is equal to 1 if its input same in value, but not when they are different.

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 XOR Gate – Revisited
x xy'
The following apply to the XOR
operation: xy’ + x’y

▪ xꚚ0=x
▪ x Ꚛ 1 = x’ y x’y
▪ xꚚx=0 Realization using AND-NOR-NOT gate

▪ x Ꚛ x’ = 1
▪ x Ꚛ y’ = x’ Ꚛ y = (x Ꚛ y)’ x (x(xy)’)’
▪ xꚚy=yꚚx
xy’ + x’y
▪ (x Ꚛ y) Ꚛ z = x Ꚛ (y Ꚛ z) = x Ꚛ y Ꚛ z (xy)’

y
(y(xy)’)’
Realization using NAND gates

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 XOR Gate – Revisited
• The XOR operation with three or more variables can be written as:
x Ꚛ y Ꚛ z = (xy’ + x’y)z’ + (xy’ + x’y)’z
= (xy’ + x’y)z’ + (xy + x’y’)z
= xy’z’ + x’yz’ + xyz + x’y’z
= (1, 2, 4, 7)
Indicates that the three-variable XOR function is equal to 1 if only odd
number if its input equal to 1. → Odd Function

• The XNOR operation with three or more variables can be written as:
(x Ꚛ y Ꚛ z)’ = [(xy’ + x’y)z’ + (xy’ + x’y)’z]’
= x’y’z’ + x’yz + xy’z + xyz’
= (0, 3, 5, 6)
Indicates that the three-variable XNOR function is equal to 1 if only even
number if its input equal to 1. → Even Function

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XOR Gate – Revisited

XOR with three variables

XOR with four variables

XNOR with three variables

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Tri-State Gate
• Two of the states are signals equivalent to logic 1 and logic 0 as in a
conventional gate; the third state is a high-impedance state.
• The symbol Z indicates that a node is being driven neither HIGH nor LOW: the
node is said to be floating, high impedance, or high Z.
• Any gate can be a tri-state gate, but the most used is the buffer

• Consider the Tristate buffers shown (A is input, C is control input)

Tristate buffer (with active high enable) Tristate buffer (with active low enable)
• If C = 1 → Y = A • If C = 0 → Y = A
• If C = 0 → Y = High impedance • If C = 1 → Y = High impedance

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References
‒ M. Mano and M. Ciletti, Digital Design, with an introduction to the
Verilog HDL. 5th Ed. Pearson, 2013.
‒ John F. Wakerly, Digital Design: Principles and Practices. 4th Ed.
Pearson, 2005.
‒ R. Katz and G. Boriello, Contemporary Logic Design. 2nd Ed. Pearson,
2005.
‒ S. Brown and Z. Vranesic , Fundamentals of Digital Logic with Verilog
Design. 3rd Ed. SEM, 2013.

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