COEN 317 - Microprocessor-based Systems

Assignment 2
 Microprocessor-based Systems – Assignment 2

1. Consider a subtraction instruction with flexible second operand Operand2:

SUB Rd, Rn, Rm, LSL #n
It is desired to modify this instruction to the following new syntax:
SUB Rd, Rm, LSL #n, Rn
This new syntax can be called subtraction instruction with flexible first operand
Operand1. What minimum change in the hardware architecture is required for the
implementation of this instruction? Please draw hardware modifications. (10 points)
Write reg
Solution 1: Read reg2
Read reg1
A shifter must be added between the first operand
and the ALU input. The first operand is given to the
shift unit before passing to the ALU as an input. Register Bank
Operand 1 Operand 2

Shifter

ALU
 Microprocessor-based Systems – Assignment 2

2. Assume you want to design the instruction fields for a simple processor, which
has only 64 instructions. The registers bank is made of 32 8-bit registers. If you
would design the instruction fields, what would be the range of bits for each field in
the following cases: (24 points)

a) The instruction field is 16 bits fixed, and it is made of Rds (one register for both
source and destination), Rs, immediate, and opcode fields, and only the first 6
registers can be used for Rs and Rds in the instruction.

b) The instruction field is 32 bits fixed, and it is made of Rd, Rs1, and Rs2 (separate
registers for source and destination), immediate, and opcode fields.

c) The instruction field is 32 bits fixed, and it is made of Rds (one register for source
and destination), Rs, and immediate and opcode fields.
 Microprocessor-based Systems – Assignment 2

Solution 2:
To code 64 instructions, 6 bits are required ( 64 = 26 ). Therefore, opcode
(instruction) field must be 6 bits.

a) Since the first 6 registers are available in this case (22 = 4, so 2 is not
enough), 3 bits are required for register addressing. There are two fields for
registers: Rds, and Rs. Therefore 6 bits are needed for these two. The last field
is imm, which can have 16 − 6 − 6 = 3 bit. It means that 3 bit will be available
for the immediate register.

b) Since all 32 registers are available in this case (25 = 32), Rs1 field = Rs2 field
= Rds field = 5 bits. Instruction = 6 bits, and imm = 32 − 5 − 5 − 5 − 6 =
11 bits for the immediate field

c) Like the previous part, Rs = 5 bits, Rds = 5 bits. Instruction = 6 bits, and imm =
32 − 5 − 5 − 6 = 16 bits.
 Microprocessor-based Systems – Assignment 2

3. Consider the execution of an addition instruction. Before the execution of this

instruction, both C and V flags are cleared. If the instruction uses the S suffix, then
give two examples of operands that result in the setting of C and V flags: One
example of operands that results in the setting of the C flag, and another example
of operands that results in the setting of the V flag. (8 points)

Solution 3:
Carry flag will be set when there is a carry after an arithmetic instruction such as
addition. Assume R1 = AB00 0000 and R2 = A200 0000. Then ADD R1, R2 results
in a carry, therefore carry flag will be set to 1.
 Microprocessor-based Systems – Assignment 2

Solution 3 (continue):
There are two types of overflow: unsigned overflow and signed overflow.

Unsigned overflow:
Let’s say R0 = 0xFFFFFFFF and R1 = 0x00000001. If we perform an addition
instruction, the 32-bit answer comes out to be 0x00000000 with carry, i.e., 1
comes out of the most significant bit (MSB). If these numbers are assumed to be
unsigned, then our expected answer is:
4,294,967,295 + 1 = 4,294,967,296.

As the correct answer cannot be accommodated in a 32-bit register, we got an

incorrect answer (i.e., 0). This situation is reflected by a 1 carried out of the MSB
and we say that an unsigned overflow has occurred. The carry flag is used for
unsigned overflow. In this case, the Carry flag will be set to 1.

Signed overflow:
Let’s say R0 = 0x7FFFFFFF and R1 = 0x7FFFFFFF and both are signed. By
performing an addition instruction, the answer will be 0xFFFF FFFE. However, the
real answer is out of the range of signed numbers and we say that a signed
overflow has occurred. It will be indicated by V = 1.
 Microprocessor-based Systems – Assignment 2

4. Write the equivalent assembly instructions for each of the following instructions
written in C (programming language). Assume 𝑥, 𝑦, and 𝑧 are R1, R2, and R3
registers, respectively. (12 points)
a) 𝑦 = 𝑧 + 𝑥/32;
b) 𝑧 = −1 ∗ 𝑧 + 𝑦 ∗ 𝑥;

Solution 4:
a) ADD R2, R3, R1, ASR #5

b) MLS R3, R2, R1, R3

or (both are equivalent)
MLS R3, R1, R2, R3
 Microprocessor-based Systems – Assignment 2

5. Assume the content of the registers and flags are as follows before executing
any instructions (values are signed):

R1 = A000 D4BA H
R2 = B001 B1C2 H
R3 = 7FFF FFFE H
R4 = 8000 0002 H

N = 0, Z = 0, C = 1, V = 0, Q = 0

Indicate the content of registers and flags after executing each one of the following
instructions: (30 points)
a) ADD R1, R2
b) ADD R3, R1, R2
c) ADDS R1, R2
d) ADDS R3, R4, R3
e) ADCS R3, R1, R2
f) ADDEQ R3, R4

Note: Examine each instruction independent of the previous instructions.

 Microprocessor-based Systems – Assignment 2

Solution 5:
a) ADD R1, R2: As the instruction does not have the optional S, the flags are not
updated if there is any.
R1 R2 R3 R4 N Z C V Q
5002 867C B001 B1C2 7FFF FFFE 8000 0002 0 0 1 0 0

b) ADD R3, R1, R2: As the instruction does not have the optional S, the flags are
not updated if there is any.
R1 R2 R3 R4 N Z C V Q
A000 D4BA B001 B1C2 5002 867C 8000 0002 0 0 1 0 0

c) ADDS R1, R2: The result is placed in R1, and flags are updated. R1 and R2
are negative, the result is positive, which is wrong -> an overflow occurs

R1 R2 R3 R4 N Z C V Q
5002 867C B001 B1C2 7FFF FFFE 8000 0002 0 0 1 1 0
 Microprocessor-based Systems – Assignment 2

Solution 5 (continue):
d) ADDS R3, R4, R3: The flags are updated.
R1 R2 R3 R4 N Z C V Q
A000 D4BA B001 B1C2 0000 0000 8000 0002 0 1 1 1 0

e) ADCS R3, R1, R2: This one is an addition with carry. Since carry bit is 1, the
result of R1, and R2 addition will be incremented by 1.
R1 R2 R3 R4 N Z C V Q
A000 D4BA B001 B1C2 5002 867D 8000 0002 0 0 1 1 0

f) ADDEQ R3, R4: This one is a conditional instruction. EQ means if zero flag is
equal to 1 (i.e. Z = 1), then execute the instruction. Since before this
instruction execution Z = 0, therefore the instruction will not be executed, and
everything will remain unchanged.
R1 R2 R3 R4 N Z C V Q
A000 D4BA B001 B1C2 7FFF FFFE 8000 0002 0 0 1 0 0
 Microprocessor-based Systems – Assignment 2

6. Consider the following assembly program: (16 points)

MOV CX, 1100H

DLY: SUBS CX, CX, #1
NOP
BNE DLY
NXT: --- ---

(a) How many times does the BNE DLY instruction get executed?
(b) Change the program so that BNE DLY is executed 22 times.

Solution 6:
The program is known as the delay loop:

a) 110016 = 212 + 28 = 4352 times

b) 22 = 1616 → 1100H must be replaced with 16H