Computer Architecture & Organization

Unit 2
M S . M AY U R I K U L K A R N I
 Content
➢Characteristics
➢Types of operands
➢Types of Operations
➢Assembly Language
➢Addressing modes
➢Instruction Format
➢Types of Instruction
➢Instruction Execution
Instruction Set ➢Machine state & processor status
➢Structure of program
➢Introduction to RISC & CISC architecture
Machine Instruction Characteristics
The operation of processor is determined by the instructions it executes, referred to as machine
instruction or computer instructions.
The collection of different instructions that the processor can execute is referred to as the
processor’s instruction set.
Characteristics
oElements of Machine Instruction
oInstruction Representation
oInstruction types
oNumber of Addresses
oInstruction set design
Elements of Machine Instruction
Each instruction contain the information required by the processor for execution.
oOperation code
oSource operand reference
oResult operand reference
oNext instruction reference

Source & result operands can be

in one of four areas:
1. Main or virtual memory
2. Processor register
3. Immediate
4. I/O device
Instruction Representation
Within a computer, each instruction is represented by a sequence of bits.
The instruction is divided into fields, corresponding to the constituent elements of the
instruction.

4 bits 6 bits 6 bits

Opcode Operand reference Operand reference
16 bits
Instruction Types
Categorizes of instruction types as follows
oData processing
Arithmetic & logical instruction
oData storage
Movement of data into or out of register and or memory locations.

oData movement
I/O instruction

oControl
Test & branch instruction
Number of Addresses
➢Three address instruction format are not common because they require a relatively long
instruction format to hold the three address references.
➢The two address format reduces the space requirement.
➢One address instruction has second address must be implicit. This was common in earlier
machines with implied address being a processor register known as accumulator. Accumulator
contains one of the operands & is used to store the result.
➢Zero-address instruction are applicable to a special memory organization called stack.
Number of Addresses
➢Traditional of describing processor architecture is in terms of the number of addresses
contained in each instruction.
➢ This dimension has become less significant with the increasing complexity of processor design.
➢Arithmetic & logical instruction requires more operands. Virtually all arithmetic & logical
operands are either unary or binary.
TYPES OF OPERATIONS
■ Data transfer
■ Arithmetic
■ Logical
■ Conversion
■ I/O
■ System control
■ Transfer of control
Common Instruction Set Operations
Type Operation Description
Name
Data transfer Move Transfer word or block from source to destination
Store Transfer word from processor to memory Load (fetch)
Transfer word from memory to processor
Exchange Swap contents of source and destination Clear (reset)
Transfer word of 0s to destination
Set Transfer word of 1s to destination
Push Transfer word from source to top of stack
Pop Transfer word from top of stack to destination
Common Instruction Set Operations
Type Operation Name Description
Arithmetic Add Add Compute sum of two operands
Subtract Compute difference of two operands
Multiply Compute product of two operands
Divide Compute quotient of two operands
Absolute Replace operand by its absolute value
Negate Change sign of operand
Increment Add 1 to operand
Decrement Subtract 1 from operand
Common Instruction Set Operations
Type Operation Name Description

Logical AND Perform logical AND

OR Perform logical OR
NOT (complement) Perform logical NOT
Exclusive- OR Perform logical XOR
Test Test specified condition; set flag(s) based on outcome
Compare Make logical or arithmetic comparison of two or more
operands; set flag(s) based on outcome
Set Control Variables Class of instructions to set controls for protection purposes,
interrupt handling, timer control, etc.
Shift Left (right) shift operand, introducing constants at end Rotate
Left (right) shift operand, with wraparound end
Common Instruction Set Operations
Type Operation Name Description
Transfer of control Jump (branch) Unconditional transfer; load PC with specified address
Jump Conditional Test specified condition; either load PC with specified address or do nothing, based on
condition
Jump to Subroutine Place current program control information in known location; jump to
specified address
Return Replace contents of PC and other register from known location
Execute Fetch operand from specified location and execute as instruction; do not modify PC Skip
Skip Increment PC to skip next instruction
Skip Conditional Test specified condition; either skip or do nothing based on condition
Halt Stop program execution
Wait (hold) Stop program execution; test specified condition repeatedly; resume execution when
condition is satisfied
No operation No operation is performed, but program execution is continued
Common Instruction Set Operations
Type Operation Name Description
Input/output Input (read) Transfer data from specified I/O port or device to
destination (e.g., main memory or processor register)
Output (write) Transfer data from specified source to I/O port or device
Start I/O Transfer instructions to I/O processor to initiate I/O
operation
Test I/O Transfer status information from I/O system to specified
destination
Common Instruction Set Operations
Type Operation Name Description
Conversion Translate Translate values in a section of
memory based on a table of
correspondences
Convert Convert the contents of a word
from one form to another (e.g.,
packed decimal to binary)
Addressing Modes
To achieve this objective, a variety of
addressing techniques has been employed.
They all involve some trade- off between
address range and/or addressing flexibility,
on the one hand, and the number of memory
references in the instruction and/or the
complexity of address calculation, on the
other.
The most common addressing techniques, or
modes:
■ Immediate
■ Direct
■ Indirect
■ Register
■ Register indirect
■ Displacement
■ Stack
Addressing Modes
The following notation:
A = contents of an address field in the instruction
R = contents of an address field in the instruction that refers to a register
EA = actual (effective) address of the location containing the referenced operand
(X) = contents of memory location X or register X
In a system without virtual memory, the effective address will be either a main memory address
or a register.
In a virtual memory system, the effective address is a virtual address or a register.
The actual mapping to a physical address is a function of the memory management unit (MMU)
and is invisible to the programmer.
Immediate Addressing Mode
The simplest form of addressing is immediate addressing, in
which the operand value is present in the instruction
Operand = A
Advantage
• no memory reference other than the instruction fetch is
required to obtain the operand, thus saving one memory
or cache cycle in the instruction cycle.
Disadvantage
• The size of the number is restricted to the size of the
address field, which, in most instruction sets, is small
compared with the word length.
Direct Addressing Modes
Addressing is direct addressing, in which the
address field contains the effective address
of the operand:
EA = A
The technique was common in earlier
generations of computers but is not common
on contemporary architectures.
It requires only one memory reference and
no special calculation.
The obvious limitation is that it provides only
a limited address space.
Indirect Addressing
The address field refer to the address of a word in
memory, which in turn contains a full- length address
of the operand. This is known as indirect addressing:
EA = (A)
The parentheses are to be interpreted as meaning
contents of. The obvious advantage of this approach is
that for a word length of N, an address space of 2N is
now available.
The disadvantage is that instruction execution requires
two memory references to fetch the operand: one to
get its address and a second to get its value.
Register Addressing
Register addressing is similar to direct addressing. The only
difference is that the address field refers to a register rather
than a main memory address:
EA = R
Advantages
(1) only a small address field is needed in the instruction, and
(2) no time- consuming memory references are required.
Disadvantage
The address space is very limited.
Register Indirect Addressing
Register indirect addressing is analogous to indirect
addressing. In both cases, the only difference is whether the
address field refers to a memory location or a register. Thus,
for register indirect address,
EA = (R)
The advantages and limitations of register indirect
addressing are basically the same as for indirect addressing.
In both cases, the address space limitation (limited range of
addresses) of the address field is overcome by having that
field refer to a word-length location containing an address.
In addition, register indirect addressing uses one less
memory reference than indirect addressing.
Displacement Addressing
It is known by a variety of names depending on the context of its
use, but the basic mechanism is the same. We will refer to this as
displacement addressing:
EA = A + (R)
Displacement addressing requires that the instruction have two
address fields, at least one of which is explicit.
The value contained in one address field (value = A) is used
directly. The other address field, or an implicit reference based on
opcode, refers to a register whose contents are added to A to
produce the effective address.
Common uses of displacement addressing:
■ Relative addressing
■ Base- register addressing
■ Indexing
Stack Addressing
It is sometimes referred to as a pushdown list or last- in- first- out
queue.
The stack is a reserved block of locations. Items are appended to the
top of the stack so that, at any given time, the block is partially filled.
Associated with the stack is a pointer whose value is the address of the
top of the stack. Alternatively, the top two elements of the stack may
be in processor registers, in which case the stack pointer references
the third element of the stack.
The stack pointer is maintained in a register. Thus, references to stack
locations in memory are in fact register indirect addresses.
The stack mode of addressing is a form of implied addressing. The
machine instructions need not include a memory reference but
implicitly operate on the top of the stack.
INSTRUCTION FORMATS
An instruction format defines the layout of the bits of an instruction, in terms of its constituent
fields. An instruction format must include an opcode and, implicitly or explicitly, zero or more
operands.
Instruction Length
Allocation of Bits
◦ The following interrelated factors go into determining the use of the addressing bits.
◦ Number of addressing modes
◦ Number of operands
◦ Register versus memory
◦ Number of register sets
◦ Address range
◦ Address granularity
ASSEMBLY LANGUAGE
A processor can understand and execute machine instructions. Such instructions are
simply binary numbers stored in the computer. If a programmer wished to program
directly in machine language then it would be necessary to enter the program as
binary data.
Consider the simple BASIC statement
N=I+J+K
Suppose we wished to program this statement in machine language and to initialize
I, J, and K to 2, 3, and 4, respectively
Example of assembly code:
Instruction Execution
The response from researchers and industry has been to develop ever more powerful and
complex high- level programming languages. These High- level languages (HLLs):
(1) allow the programmer to express algorithms more concisely;
(2) allow the compiler to take care of details that are not important in the programmer’s
expression of algorithms; and
(3) often support naturally the use of structured programming and/or object- oriented design.
Instruction Execution
This solution gave rise to a perceived problem, known as the semantic gap, the difference
between the operations provided in HLLs and those provided in computer architecture.
Symptoms of this gap are alleged to include execution inefficiency, excessive machine program
size, and compiler complexity. Designers responded with architectures intended to close this
gap.
complex instruction sets are intended to:
■ Ease the task of the compiler writer.
■ Improve execution efficiency, because complex sequences of operations can be implemented
in microcode.
■ Provide support for even more complex and sophisticated HLLs.
Instruction Execution
To understand the line of reasoning of the RISC advocates, we begin with a brief review of
instruction execution characteristics. The aspects of computation of interest are as follows:
■ Operations performed: These determine the functions to be performed by the processor and
its interaction with memory.
■ Operands used: The types of operands and the frequency of their use determine the memory
organization for storing them and the addressing modes for accessing them.
■ Execution sequencing: This determines the control and pipeline organization.
Characteristics of Some CISCs, RISC
THE USE OF A LARGE REGISTER FILE
The reason that register storage is indicated is that it is the fastest available storage device, faster
than both main memory and cache.
The register file is physically small, on the same chip as the ALU and control unit, and employs much
shorter addresses than addresses for cache and memory.
Thus, a strategy is needed that will allow the most frequently accessed operands to be kept in
registers and to minimize register- memory operations.
Two basic approaches are possible, one based on software and the other on hardware. The software
approach is to rely on the compiler to maximize register usage.
The compiler will attempt to assign registers to those variables that will be used the most in a given
time period. This approach requires the use of sophisticated program- analysis algorithms.
The hardware approach is simply to use more registers so that more variables can be held in registers
for longer periods of time.
Register Windows
On the face of it, the use of a large set of registers should decrease the need to access memory.
The design task is to organize the registers in such a fashion that this goal is realized.
Because most operand references are to local scalars, the obvious approach is to store these in
registers, with perhaps a few registers reserved for global variables. The problem is that the
definition of local changes with each procedure call and return, operations that occur frequently.
On every call, local variables must be saved from the registers into memory, so that the registers
can be reused by the called procedure. Furthermore, parameters must be passed. On return, the
variables of the calling procedure must be restored (loaded back into registers) and results must
be passed back to the calling procedure.
Register Windows
At any time, only one window of registers is visible and is addressable as if it were the only set
of registers (e.g., addresses 0 through N - 1). The window is divided into three fixed- size areas.
Parameter registers hold parameters passed down from the procedure that called the current
procedure and hold results to be passed back up. Local registers are used for local variables, as
assigned by the compiler.
Temporary registers are used to exchange parameters and results with the next lower level
(procedure called by current procedure). The temporary registers at one level are physically the
same as the parameter registers at the next lower level.
This overlap permits parameters to be passed without the actual movement of data. Keep in
mind that, except for the overlap, the registers at two different levels are physically distinct. That
is, the parameter and local registers at level J are disjoint from the local and temporary registers
at level J + 1.
Register Windows
To handle any possible pattern of calls and returns, the number of register windows would have
to be unbounded. Instead, the register windows can be used to hold the few most recent
procedure activations.
Register Windows
The circular organization which depicts a
circular buffer of six windows. The buffer is
filled to a depth of 4 (A called B; B called C; C
called D) with procedure D active. The current-
window pointer (CWP) points to the window of
the currently active procedure. Register
references by a machine instruction are offset
by this pointer to determine the actual physical
register.
The saved- window pointer (SWP) identifies
the window most recently saved in memory. If
procedure D now calls procedure E, arguments
for E are placed in D’s temporary registers (the
overlap between w3 and w4) and the CWP is
advanced by one window.