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LogicDesign 6
LogicDesign 6
Ch 7
note 6
Topics
Sequential circuits
primitive sequential elements
combinational logic
Models for representing sequential circuits
finite-state machines (Moore and Mealy)
Basic sequential circuits revisited
shift registers
counters
Design procedure
state diagrams
state transition table
next state functions
A’C+B’C+ABC’
= (AB)’C+ABC’
= (AB)C OUTA OUTB OUTC
D Q D Q D Q
CLK
A’B+AB’
= AB
"1"
A’
C+ C B+ C A+ C
0 0 0 X 1 1 0 X 0 1 0 X
A X 1 X 1 A X 0 X 1 A X 1 X 0
B B B
Start-up states
At power-up, a counter may be in an unused or invalid state
Designer must guarantee that it (eventually) enters a valid state
Ex: implementation on previous slide
If the counter is initiated at state 100 or 111, 000 110
it can never enter a valid state.
111
010 101
Self-starting solution
100 011
Must design a counter so that
invalid states eventually transition 001
to a valid state
May limit exploitation of don't cares
Inputs Outputs
Combinational
Logic
Memory Cells
states
12 Digital Logic Design
Finite state machine representations
In = 0 In = 1
Components 001 010 111
States: determined by possible
values in sequential memory cells
100 110
Transitions: change of state In = 1
Tsu
based on sequence of values on
input signals Clock
Input
State time is the time between
Output
related clocking events
13 Digital Logic Design
FSM design procedure
Example: counter
The states of the circuit stored in registers (flip-flops) represent
counter values
Next state is a function of current state and inputs
Outputs are the state reset, up/down
FSM model for a counter
Combinational logic implements the function for next state
Outputs are directly connected to registers
reset, up/down next state
Next counter value
logic
registers
Outputs
Current counter value
15 Digital Logic Design
State diagram
CLK
Input value shown
on transition arcs
1
100 110
1 0 1 1
1
0
0 0 1 0
Tsu Th
Next State
State
Clock 0 1 2 3 4 5
1/0
state feedback
logic for
inputs outputs outputs
Mealy combinational
logic for reg
next state
Registered/Synchronous combinational
logic for reg
next state
Mealy
state feedback
23 Digital Logic Design
Registered Mealy machine
Current State
24 Digital Logic Design
FSM design example: Vending machine
Clock
25 Digital Logic Design
Step2: abstract representation
0¢
N’ D’ 0¢ N’ D’/0
[0]
N N/0
5¢ D/0
D N’ D’ 5¢ N’ D’/0
[0]
N N/0
10¢
D N’ D’ D/1 10¢ N’ D’/0
[0]
N+D N+D/1
15¢ R’/1
Reset’ 15¢
[1]
D0 = Q0’N + Q0N’
+ Q1N + Q1D
D1 = Q1 + D + Q0N
OPEN = Q1Q0 + Q1N
+ Q1D + Q0D
Q
Synch. Mealy w/o state
or equivalently… B
D Q
Moore where next states are only clock 10
11
dependent on inputs as shown below Q
S10
10
[0] S11
01 01
10 10 11 [0]
00,
S0 S1 S00
10, 01 S01 01
[0] [1] [0]
11 00,10,11 01
[1]
00 01
00
A
D Q
B
S1101 D Q
… [0] … Q
clock
11
SQ3Q2Q1Q0
S0110 out
[1]
A Q3 Q1
01 D Q D Q
… 10
Q Q
S1001 … Q2 Q0 Moore: 16 states generated
[0] B
D Q D Q
by 4 state bits
Q Q
clock
36 Digital Logic Design
Example: reduce-1-string-by-1
Moore Mealy
zero
[0] 0/0
zero
1 0
0 one1 0/0 1/0
[0]
0 one1
1
1 1/1
two1s
[1]