Assignment-2

Q1. Explain the 8279 block diagram,pin diagram and how it work .
Ans- 8279 Block Diagram consists of four main sections-

1.CPU Interface and Control Section:This section consists of data buffers, I/O
control, control and timing registers, and timing and control logic.

Data Buffers:The data buffers are 8-bit bi-directional buffers that connect the
internal data bus to the external data bus.

I/O Control: The I/O control section uses the A 0, CS, RD and WR signals to control
data flow to and from the various internal registers and buffers.

Control and Timing Registers:The control and timing registers store the keyboard
and display modes and other operating conditions programmed by the CPU. The
modes are programmed by sending the proper command on the data lines with A 0 =
1.

Timing Control: The timing control consists of the basic timing counter chain. The
first counter is divided by N prescaler that can be programmed to give an internal
frequency of 100 kHz.
2. Scan Section (Scan counter):The scan section has a scan counter which has two
modes : Encoded mode and decoded mode.

Encoded Mode:In the encoded mode, the scan counter provides a binary count from
0000 to 1111 on the four scan lines (SC3 — SC0) with active high outputs. This
binary count must be externally decoded to provide 16 scan lines.

Decoded Mode:In the decoded mode, the internal decoder decodes the least
significant 2 bits of binary count and provides four possible combinations on the scan
lines (SC3 — SC0) :1110, 1101, 1011 and 0111. Thus the output of decoded scan is
active low.

3. 8279 Keyboard section:This section consists of return buffers, keyboard debounce

and control, FIFO/sensor RAM and FIFO/sensor RAM status.

Return buffers:The 8 return lines (RL7 — RL0) are buffered and latched by the
return buffers during each row scan in scanned keyboard or sensor matrix imode In
strobed input mode, the contents of the return lines are transferred to the FIFO RAM
on the rising edge of the CNTL/STB line pulse.

Keyboard debounce and control:Keyboard and debounce control is enabled only

when scanned keyboard mode is selected. In the scanned keyboard mode, return lines
are scanned, looking for key closures in that row.

FIFO/Sensor RAM:This is a dual function 8 x 8 RAM. In scanned keyboard and

strobed input modes, it is a FIFO. Each new entry is written into successive RAM
positions and then read in order of entry.

FIFO/sensor RAM status:FIFO RAM status keeps track of the number of characters
in the FIFO and whether it is full or empty.

4. Display section:The display section consists of display RAM, display address

registers.

Display RAM:It is 16 x 8 RAM, which stores the display codes for 16 digits. It can
be accessed directly by CPU. In decoded mode, 8279 uses only first four locations of
display RAM. In encoded mode, Block Diagram of 8279 uses first eight locations.

Display address registers:The display address registers hold the address of the byte
currently being written or read by the CPU and scan count value.
Pin diagram of 8279:
How it work:The Intel 8279 is a programmable keyboard and display interface chip.
It is commonly used in microprocessor-based systems to interface with keyboards,
displays, and other input/output devices. The 8279 performs the following functions:
1. Keyboard Interface:

• The 8279 can scan a matrix keyboard with up to 64 keys (8 rows by 8

columns).
• It can detect key closures and generate key codes for the pressed keys.
• The keyboard is typically connected to the rows and columns of the
matrix, and the 8279 scans through them to determine which key is
pressed.
2. Display Interface:

• The 8279 can be used to interface with a variety of display devices, such
as 7-segment displays or LED displays.
• It can drive up to 16 display patterns with a maximum of 16 characters
each.
• The chip provides multiplexing capabilities for driving multiple displays.
3. Modes of Operation:

• The 8279 has different modes of operation, including:

• Scanned Keyboard Mode: Used for scanning the keyboard matrix
and detecting key presses.
• 2-Key Lockout Mode: Prevents the detection of more than two
keys pressed simultaneously.
• Decoded Keyboard Mode: Allows the use of encoded or
unencoded key matrices.
• Encoded Display Scan Mode: Used for interfacing with display
devices.
4. Control Words and Registers:

• The chip is programmed using control words written to its control

register.
• It has various registers, including the Keyboard Matrix, Display RAM,
and Status Register.
• Control words specify the operations to be performed and the modes of
operation.
5. Interrupt Generation:

• The 8279 can generate interrupts to the microprocessor when certain

events occur, such as key presses or display-related events.
 • The microprocessor can then respond to these interrupts and take
appropriate actions.
6. Data and Command Communication:

• Data and commands are exchanged between the microprocessor and the
8279 through data and command registers.
• The microprocessor sends control words to configure the 8279 and read
status information.
• The chip sends data, such as key codes or display information, to the
microprocessor.

Q2. Explain the 8259 block diagram,pin diagram and how it work .

Ans-

It includes eight blocks : data bus buffer, read/write logic, control logic, three
registers (IRR, ISR and IMR), priority resolver, and cascade buffer.
Data Bus Buffer:The data bus buffer allows the 8085 to send control words to the
8259A and read a status word from the 8259 Block Diagram. The 8-bit data bus
buffer also allows the 8259A to send interrupt opcode and address of the interrupt
service subroutine to the 8085.

Read/Write Logic:The RD and WR inputs control the data flow on the data bus
when the device is selected by asserting its chip select (CS) input low.

Control Logic:This block has an input and an output line. If the 8259A is properly
enabled, the interrupt request will cause the 8259A to assert its INT output pin high.
Interrupt Request Register (IRR): It stores those bits which are requested for
their interrupt services.
Interrupt Service Register (ISR): It stores the interrupt levels which is currently
being served.
Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked.
These interrupt levels are already accepted by the 8259 microprocessor.
Priority Resolver (PR): It examines all the 3 registers and sets the priority of
interrupts and sets the interrupt levels in ISR which has the highest priority and the
rest of the interrupt bit is IRR which is already accepted.
SP/EN (low active pin): If its value is 1 it works in master mode & if its value is 0
then it works in slave mode.
How it work: The Intel 8259 is a Programmable Interrupt Controller (PIC)
commonly used in microprocessor-based systems to manage and prioritize interrupts
from various sources. Here is an overview of how the 8259 works:
1. Interrupt Handling:

• The primary function of the 8259 is to manage interrupt requests (IRQs)

from different devices in a system.
• Devices connected to the 8259 can request attention by asserting their
corresponding interrupt lines.
2. Cascading:

• The 8259 can be cascaded to handle more than eight interrupt sources. In
a cascaded configuration, one 8259 is designated as the master, and
additional 8259s are set as slaves.
• This allows the system to handle more than eight interrupt sources by
chaining multiple 8259s together.
3. Priority Resolution:

• The 8259 supports interrupt priority resolution. Each interrupt source is

assigned a priority level (0 to 7).
• The chip resolves interrupt priorities and services the highest-priority
interrupt first.
4. Interrupt Masking:

• The 8259 allows masking of interrupts, which means that specific

interrupt sources can be temporarily disabled.
• This feature is useful when certain interrupt sources need to be ignored
for a specific period.
5. Initialization and Programming:

• The 8259 is initialized and programmed by sending command words to

its control registers.
• Initialization involves setting the interrupt vector addresses, configuring
interrupt modes (edge/level-triggered), and setting up interrupt masks.
6. Interrupt Acknowledgment:

• When an interrupt occurs, the 8259 generates an interrupt

acknowledgment signal to the CPU.
• The CPU responds to this signal by fetching the appropriate interrupt
vector from the interrupt vector table.
7. Modes of Operation:

• The 8259 has several modes of operation, including:

 • Single Interrupt Mode: Only one interrupt request is serviced at
a time.
• Special Mask Mode: Allows masking of specific interrupt levels.
• Auto EOI Mode: Automatically issues an End of Interrupt (EOI)
signal after servicing an interrupt.
• Cascaded Mode: Used when multiple 8259 chips are cascaded.
8. End of Interrupt (EOI):

• After the CPU has processed an interrupt, it sends an EOI command to

the 8259 to indicate that the interrupt has been serviced.
• In a cascaded configuration, the EOI is sent to the appropriate 8259 in
the chain.
9. Interrupt Request (IRQ) Lines:

• The 8259 is connected to the CPU via IRQ lines, and each device that
can generate interrupts is connected to a specific IRQ line.
10.Priority Rotation:

• The 8259 can be configured to rotate priority levels, ensuring that lower-
priority interrupts get a chance to be serviced.

Q3. Explain the 8257 block diagram,pin diagram and how it work .

Ans- The Intel 8257 is DMA (Direct Memory Access) controller. The 8257 is
designed to facilitate the transfer of data between external devices and memory
without involving the microprocessor in each data transfer.
Here's an overview of how the Intel 8257 DMA controller works:
1. Functionality:

• The primary purpose of the 8257 is to offload the data transfer tasks
from the microprocessor to enhance overall system efficiency.
• It is commonly used to transfer blocks of data between memory and
various peripherals, such as I/O devices.
2. Channels:

• The 8257 typically has multiple channels (four channels in the case of
the Intel 8257).
• Each channel can operate independently, allowing simultaneous data
transfers between different devices and memory.
3. Control Registers:
 • The DMA controller is configured and controlled through a set of control
registers.
• These registers include the base address register, word count register,
mode register, and command register, among others.
4. Modes of Operation:

• The 8257 supports different modes of operation, such as single transfer,

block transfer, demand transfer, and cascade mode.
• Single transfer mode transfers one data word, block transfer transfers a
block of consecutive words, and demand transfer allows the device to
transfer data only when the peripheral requests it.
5. Cascade Mode:

• In cascade mode, multiple 8257 controllers can be connected to increase

the number of DMA channels.
• This is particularly useful when a system requires more than four DMA
channels.
6. Data Transfer Process:

• The microprocessor initializes the DMA controller by writing

appropriate values to its control registers.
• The DMA controller takes control of the system buses during data
transfer, allowing it to access the system memory directly.
7. Interrupts:

• The 8257 can be configured to generate interrupts upon the completion

of a data transfer.
• This allows the microprocessor to be informed when the DMA operation
is finished.
8. Arbitration:

• The 8257 includes a priority resolver to manage multiple requests for

DMA service. It determines the priority of channels based on their
assigned priority levels.