Lec02 ASA

dce 2021
dce 2021
Advanced System Architectures

BK
TP.HCM
Assoc.Prof. Dr. Tran Ngoc Thinh
HCMC University of Technology
Review of Instructions Set
Architecture
©2021, dce
Advanced System Architectures, Chapter 2 2
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Outline 2021
Machine Instruction
 Instruction structure
 ISA styles
 Addressing modes
 Analysis on instruction set
 Case study: MIPS
Computer can only understand binary values

The operation of a computer is defined by
predefined binary values called Instruction
Advanced System Architectures, Chapter 2 3 Advanced System Architectures, Chapter 2 4
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The Instruction Set 2021
Instruction execution cycle
software Instruction
Obtain the instruction
Fetch
instruction set Instruction

Determine action to be perform
Decode
hardware
Operand
Obtain the operand data
Fetch
Instruction set: set of all instructions a processor Execute Compute the result (update status)
can perform Write

Store the result
Interface between software and hardware Back
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ISA Styles 2021

ISA Styles: Stack
Input1 Input2 TOS Stack Element C= A+B?
Stack Element
PUSH A
Operation PUSH B
ISA Styles? ADD
• Stack POP C
Output
• Accumulator  Stack: The operands is on top of stack. The
• Register memory/ Memory memory result is push back to the stack
• Register register/load store  (+): Code density, simple hardware
 (-): Low parallelism, stack bottle-neck
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ISA Styles: Accumulator 2021
ISA Styles: Memory-memory
C= A+B?
Accumulator
LOAD A - Put A in
Memory Accumulator (AC)
ADD B - Add B with AC Memory
put result in AC
STORE C- Put AC in C
 Memory-memory: The operands is located in

 Accumulator: One accumulator register is used in all
operations
memory
 (+): Easy to write compiler, few instruction  (+): Simple hardware, design & understand
 (-): Very high memory traffic, variable CPI  (-): Accumulator bottle-nect, memory access
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ISA Styles: Register-Memory 2021
ISA Styles: Register-Register
Register C= A+B?
Register Input, Output: Register
or Memory Register
Register
Register LOAD R1, A
Register
LOAD R2, B
C= A+B?
ADD R3, R1, R2
Memory STORE R3, C
LOAD R1, A
ADD R3, R1, B
add R1 & B
đưa vào R3
STORE R3, C
 Register-Register: All operations are on registers
R3 thanh ghi đích  Need specific Load and Store instruction to access
memory cần nhiều thanh ghi và nhiều lệnh hơn.
nhưng tốc độ tính toán nhanh, có thể tái sử
dụng giá trị tính toán trên thanh ghi
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ISA Styles 2021
Other ISA Styles
Machine # general- Architecture style Year  High-level-language architecture:
purpose • In the 1960s (B5000)
registers
Motorola 6800 2 Accumulator 1974
• Lack of effective compiler
DEC VAX 16 Register-Memory/ 1977  Reduced Instruction Set architecture:
Memory-Memory
• Simplify hardware
Intel 8086 1 Extended Accumulator 1978
Motorola 16 Register-Memory 1980 • Simplify the instruction set
68000 • Simplify the instruction format
Intel 80386 32 Register-Memory 1985
• Rely on compiler to perform complex
Power PC 32 Load-Store 1992
operation
Dec Alpha 32 Load-Store 1992
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Evolution of Instruction Sets 2021
Instruction set design
Single Accumulator (EDSAC 1950)  The design of an Instruction Set is critical to
Accumulator + Index Registers
(Manchester Mark I, IBM 700 series 1953)
the operation of a computer system.
 Including many aspects
Separation of Programming Model
from Implementation • Operation repertoire
High-level Language Based Concept of a Family • Addressing modes
(B5000 1963) (IBM 360 1964)
• Data types
General Purpose Register Machines
• Instruction format
Complex Instruction Sets Load/Store Architecture
(Vax, Intel 432 1977-80)
(CDC 6600, Cray 1 1963-76) • Registers
RISC
(Mips,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987)
LIW/”EPIC”? (IA-64. . .1999)

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Simple format 2021
Instruction Types
Opcode Source Operand Result Operand Can be classified into 4 types:
reference reference - Data processing: Arithmetic, Logic
Operation Code: the operation to be performed Ex: ADD, SUB, AND, OR, …
by the processor - Data storage: Move data from/to memory
Source Operand Reference: Input of the Ex: LD, ST
operation. One or more source operands can - Data movement: Register and register/IO
be involved Ex: MOV
Result Operand Reference: Result of the - Control: Test and branch
operation
Ex: JMP, CMP
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Operations 2021
Operations
There must certainly be instructions for performing Operator type Example
the fundamental arithmetic operations Arithmetic & Integer arithmetic and logical operations: add, and, subtract
Burkes, Goldstine and Von Neumann, 1947 Logical …
Data transfer Loads-stores (move instructions on machines with memory
addressing)
How many programs have “IF” statement? Control Branch, jump, procedure call and return, trap
System Operating system call, Virtual memory management
-> Branch instructions instructions
How many programs have “Call” statement? Floating point Floating point instructions: add, multiply
Decimal Decimal add, decimal multiply, decimal to character
-> Call, Return instructions conversion
How many programs have to access memory? String String move, string compare, string search
Graphic Pixel operations, compression/decompression operations
… and so on
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Operations 2021
Operation usage
 Arithmetic, logical, data transfer and control
are almost standard categories for all
machines
 System instructions are required for multi-
programming environment although support
for system functions varies
 Others can be primitives (e.g. decimal and
string on IBM 360 and VAX), provided by a  Simple instructions are the most widely
co-processor, or synthesized by compiler executed
 Make the common case fast
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Addressing Modes 2021
Addressing modes
The way the processor refers to the operands is - Immediate addressing: the operand is put in
called addressing mode the instruction
The addressing modes can be classified based Ex: ADD R0, #10
on: - Register addressing: the index of the register
• The source of data: Immediate, registers, which contains the operand is specified in the
memory instruction
• The address calculation: Direct, indirect, Ex: ADD R0, R1
indexed - Direct addressing: the address of the operand
is put in the instruction
Ex: ADD R0, (100)
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Addressing modes 2021
Addressing mode use
- Register Indirect addressing: the address of
the operand is put in the register which is
specified in the instruction
Ex: ADD R0, (R1)
- Displacement addressing: the address of the
operand is Base register + Displacement
Ex: LD R1, 100(R2)
- Indexed addressing: The address of the
operand is Base register + Indexed register
Ex: ADD R3, (R1+R2)
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Addressing mode 2021
Addressing modes
 Is Memory indirect addressing necessary?
 Is Scaled addressing necessary?
 Is Register addressing necessary?
 How long should a displacement value be?
 How long should an immediate value be?
dựa theo thiết kế và thực nghiệm để đánh giá.
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Addressing modes 2021
Operand types
 Character:
- ACSII (8-bit): amost always used
- Unicode (16-bit): sometime
 Integer: 2’s complement
- Short: 16 bit
- Long: 32 bit
 Floating point:
- Single precision: 32 bit
- Double precision: 64 bit
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Operand types 2021
Operand types and size
 Business  Should CPU support all those types of
- Binary Coded Decimal (BCD): Accurately operand?
represents decimal fraction  Should CPU support very big-size operand?
 DSP  Is DSP’s data types used frequently?
- Fixed point  Is BCD used in most of operations?
- Block floating point  How about RGBA?
 Graphic: RGBA or XYZW
- 8-bit, 16-bit or single precision floating
point
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mips: có 32bits cố định nên by-line giảm hazardous
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Instruction format 2021
Instruction format
 Instruction must be encoded to binary values Addr Addr Addr Addr
Opcode
Specifier Field
… Specifier Field
 Effect the size of compiled program
Variable instruction length (e.g. VAX, X86)
 Easy to decode -> Simple to implement chiều dài tập lệnh ko cố định
 Support as many registers and addressing Addr Addr Addr
Opcode
modes as possible Field 1 Field 2 Field 3
MIPS Opcode Rs Rt Rd Shamt Funct Fixed instruction length (e.g. ARM, MIPS, PowerPC)
Ex: ADD $t0, $s1, $s2 Hybrid: to gain high code density, use 2 types of
000000 10001 10010 01000 00000 100000 fixed length instruction (e.g. MIPS16, Thumb)
0x02324020
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Registers file 2021
Complex Instruction Set Computer (CISC)
 Emphasizes doing more with each instruction:
 Register is the fastest memory element • Thus fewer instructions per program (more compact code).
 Register cost much more than main memory  Motivated by the high cost of memory and hard disk capacity
when original CISC architectures were proposed
 Register is flexible for compiler to use • When M6800 was introduced: 16K RAM = $500, 40M hard disk = $ 55,
000
 More register need more bits to encode • When MC68000 was introduced: 64K RAM = $200, 10M HD = $5,000
 Original CISC architectures evolved with faster more complex
 Register file with more locations can be CPU designs but backward instruction set compatibility had to
be maintained.
slower  Wide variety of addressing modes:
• 14 in MC68000, 25 in MC68020
 How many locations in register file is the most  A number instruction modes for the location and number of
effective? operands:
• The VAX has 0- through 3-address instructions.
 Variable-length instruction encoding.
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Example CISC ISA: Motorola 680X0 2021
Example CISC ISA:Intel IA-32, X86 (80386)
18 addressing modes: GPR ISA (Register-Memory)
• Data register direct. 12 addressing GPR ISA (Register-Memory)
Operand sizes:
•
•
Address register direct.
Immediate.
Operand size: modes:
• Absolute short. Can be 8, 16, 32, 48, 64, or 80 bits long.
Range from 1 to 32 bits, 1, 2, 4, • Register.
• Absolute long. 8, 10, or 16 bytes. Also supports string operations.
• Address register indirect. • Immediate.
• Address register indirect with postincrement. • Direct.
• Address register indirect with predecrement. • Base.
• Address register indirect with displacement.
Instruction • Base + Displacement. Instruction Encoding:
• Address register indirect with index (8-bit).
• Index + Displacement.
• Address register indirect with index (base). Encoding: • Scaled Index + Displacement.
The smallest instruction is one byte.
• Memory inderect postindexed.
• Memory indirect preindexed. Instructions are stored in 16-bit • Based Index. The longest instruction is 12 bytes long.
• Program counter indirect with index (8-bit). words. • Based Scaled Index. The first bytes generally contain the
• Program counter indirect with index (base). the smallest instruction is 2- opcode, mode specifiers, and register
• Based Index + Displacement.
• Program counter indirect with displacement. bytes (one word). fields.
• Program counter memory indirect postindexed. • Based Scaled Index +
• Program counter memory indirect preindexed. The longest instruction is 5 Displacement. The remainder bytes are for address
words (10 bytes) in length. • Relative. displacement and immediate data.
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dce dce Example RISC ISA: HP Precision Architecture, HP PA-

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Reduced Instruction Set Computer (RISC) 2021
RISC
• Focuses on reducing the number and complexity of instructions of the
machine. Operand sizes:
• Reduced CPI. Goal: At least one instruction per clock cycle.
7 addressing modes:
Five operand sizes ranging in
• Designed with pipelining in mind. • Register powers of two from 1 to 16 bytes.
(CPI = 1 or less) • Immediate
• Fixed-length instruction encoding.
• Only load and store instructions access memory. • Base with displacement
• Base with scaled index and
• Simplified addressing modes.

(Thus more instructions executed than CISC) displacement Instruction Encoding:
• Predecrement
– Usually limited to immediate, register indirect, register displacement, • Postincrement Instruction set has 12 different
indexed. formats.
• PC-relative
• Delayed loads and branches. All are 32 bits in length.
• Instruction pre-fetch and speculative execution.
• Examples: MIPS, SPARC, PowerPC, Alpha
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Example RISC ISA: Alpha AXP 2021
Case study: MIPS
Operand sizes: • Used as the example throughout the course
4 addressing modes: • Stanford MIPS commercialized by MIPS
Four operand sizes: 1, 2, 4 or 8
• Register direct. bytes. Technologies (www.mips.com)
• Immediate.
• Register indirect with • Large share of embedded core market
displacement.
– Applications in consumer electronics, network/storage
• PC-relative. Instruction Encoding: equipment, cameras, printers, …
Instruction set has 7 different • Typical of many modern ISAs
formats.
All are 32 bits in length.
• GroupX_RISC_CISC_assignment_K2021.doc
• Each Group has 4-6 persons

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The MIPS ISA 2021
MIPS (RISC) Design Principles
Registers
• Instruction Categories • Simplicity favors regularity
– Load/Store 32 thanh ghi – fixed size instructions
R0 - R31
– Computational – small number of instruction formats
– opcode always the first 6 bits
– Jump and Branch
• Smaller is faster
– Floating Point – limited instruction set
• coprocessor PC
HI hi, low cho phép – limited number of registers in register file 32 registers
– Memory Management nhân, chia – limited number of addressing modes 4-5 modes
LO
– Special • Make the common case fast
• 3 Instruction Formats: all 32 bits wide – arithmetic operands from the register file (load-store machine)
– allow instructions to contain immediate operands
OP rs rt rd shamt funct R-format • Good design demands good compromises
OP rs rt immediate I-format – Same instruction length
– Single instruction format => 3 instruction formats
OP jump target J-format cân nhắc giữa hiệu suất và tài nguyên
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mips là 1 họ nhà rics
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MIPS Instruction Classes Distribution 2021
MIPS Register Convention
Name Register Usage Preserve on
• Frequency of MIPS instruction classes for Number call?
SPEC2006 $zero 0 constant 0 (hardware) n.a.
$at 1 reserved for assembler n.a.
Instruction Class Frequency $v0 - $v1 2-3 returned values no
Integer Ft. Pt. $a0 - $a3 4-7 arguments yes
Arithmetic 16% 48% $t0 - $t7 8-15 temporaries no
Data transfer 35% 36% $s0 - $s7 16-23 saved values yes
Logical 12% 4% $t8 - $t9 24-25 temporaries no
Cond. Branch 34% 8% $k0 - $k1 26-27 reserved for operating system n.a
Jump 2% 0% $gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 return addr (hardware) yes
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MIPS - Endianness 2021
MIPS R-Format instructions
Op Rs Rt Rd Shamt Funct
địa chỉ cao
• Op: opcode
• Rs: First source register number
địa chỉ thấp • Rt: Second source register number
• Rd: Destination register number
• Big Endian: Most-significant byte at lowest
• Shamt: shift amount
address of a word byte cao nằm ở địa chỉ cao
– Number of bit-shift –(left/right)
• Little Endian: Least-significant byte at lowest • Funct: Extend opcode
address of a word byte cao nằm ở địa chỉ thấp – ALU function to encode the data path operation
• MIPS is Big-endian Execution: Rd <- Rs func Rt
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MIPS R-Format instructions 2021
Arithmetic instruction
• Arithmetic operations on register • ADD, SUB, MUL, DIV, …
• Logical operations on register • Ex: ADD $t0, $s1, $s2
• And more (refer [1]) Special $s1 $s2 $t0 0 add
• For arithmetic and logical instruction:
0 17 18 8 0 32
– Opcode is always SPECIAL (000000),
– Funct indicates the specific operation to be 000000 10001 10010 01000 00000 100000
performed
Encoded instruction word is:
• What addressing mode do these instructions
use? 0x02324020
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Logical operations 2021
Logical operations
• AND, OR, XOR, XNOR (bit-wise) • Shift Right Arithmetic (SRA) use MSB as the
• Ex: OR $t0, $t1, $t2 #$t0 = $t1 | $t2 shift-in bit
• Please calculate the encoded instruction word • Ex: SRA $t2, $s0, 8
for the above instruction 000000 00000 10000 01010 01000 000011
• Shift left, shift right
• Shamt indicates the number of bit to shift • Why is there no SLA? do dịch trái thì bit dấu tự mất đi, nên ko cần dịch trái số học
• Ex: SLL $t2, $s0, 8 • Why is there no NOT?

shift trái tương ứng với nhân 2^(số bit dịch).
000000 00000 10000 01010 01000 000000 shift phải tương ứng với chia 2^(số bit dịch).
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Jump register 2021
MIPS I-Format instructions
• Register indirect addressing Opcode Rs Rt 16-bit immediate value
• JR: Jump register (JR rs) • This types of instruction can be:
- Rs: target address - Operation with immediate addressing
- Rd, Rt = 0; shamt: special purpose (hint) [1] - Operation with displacement addressing
• JALR: Jump and link register (JALR rs, JALR - Operation with PC-relative addressing
rd,rs)
- Rs: target address
- Rd: return address
- Rt = 0; shamt: special purpose (hint) [1]
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Immidiate arithmetic and logical 2021
Immediate arithmetic and logical
Opcode Rs Rt 16-bit Immediate Value • Ex: ADDI $t0, $t1, 0x0005
001000 01001 01000 0000000000000101
• Arithmetic and Logical instruction with immediate
value
- Op: opcode • Ex: ORI $t0, $t1, 0xFF00
- Rs: source register 001101 01001 01000 1111111100000000
- Rt: destination register
- Constant: immediate value (-32768 to 32767) • Why is there no SUBI? sub immediate
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Load-Store (Displacement) có độ dời
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Load-Store (Displacement)
giả sử t1 data = 4.
Opcode Rs Rt 16-bit immediate value • Ex: LW $t0, 16($t1) địa chỉ load: t1 + 16 = 20
tương đương load data ở register số 20 vào t0
• Load/Store instructions with offset 100011 01001 01000 0000000000010000

– Rs: base register number thanh ghi nền giả sử t1 data = 4.
– 16-bit immediate value: offset added to base • Ex: SW $t0, 16($t1)
t0 có data = 7
địa chỉ store: t1 + 16 = 20
address in Rs w = word
tương đương store data của t0 (=7) vào register số 20
– The effective address (EA) = Rs + 16-bit 101011 01001 01000 0000000000010000

immediate value Load: thì rt là thanh ghi đích
Store: thanh ghi nguồn
– Load: Rt is the destination register number
– Store: Rt is the value to be store to the EA in
memory
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PC-Relative 2021
MIPS J-format Instructions
Opcode Rs Rt 16-bit Immediate Value Opcode 26-bit Offset
• Near branch instructions • Jump (J and JAL)
– Rs: source register number
• Pseudo-Direct addressing
– Rt: source register number
– Target address = PC + offset x 4
– Cannot put 32-bit value in instruction
– PC already incremented by 4 by this time – Target address = PC31…28: (26-bit offset ×4)
• EX: BEQ $s0, $s1, 256
– if($s0 == $s1) goto PC+256x4; • Ex: J 0x01000000
000010 00000001000000000000000000000000
000100 10000 10001 0000000100000000
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Quiz 2021
Working with byte/halfword
• How to move data from $t0 to $t1 using 1 • LB/LH/LBU/LHU: Load byte/haftword from
MIPS instruction? memory
– LBU $t0, 1($s0): Zero-extended
– LH $t0, 2($s0): Sign-extended
• SB, SH: Store byte/halfword to memory
– SB $t0, 1($s0)
– SH $t0, 2($s0)
• Why don’t we have SBU, SHU?
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Atomic operation 2021
Atomic operation
• An atomic Read-Modify-Write operation can • Example atomic swap:
be done by a pair of instructions: LL (Load try: ADD $t0, $zero, $s4 //$t0 = $s4
Link Word) and SC (Store Conditional Word) LL $t1, 0($s1) //$t1 = mem($s1)
LL $Rt, offset($Rs)
SC $t0, 0($s1) //mem($s1) = $t0
SC $Rt, offset($Rs)
BEQ $t0, $zero, try //if mem($s1) changed,
• If the content at memory address specified by
LL is modified before SC to the same address, //try again
SC fails and return 0 in $Rt. Or else, SC store //else mem($s1) = $t0
$Rt to memory and return 1 in $Rt ADD $s4, $zero, $t1//$s4 = $t1
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Constant (Immediate) value 2021
Procedure call
• Small constants are used quite frequently • Save return address
(50% of operands in many common programs) • Save necessary registers
Ex: $t0 = 0x1234 • Callee execute the function
ADDI $t0, $zero, 0x1234
• Restore previously saved registers
• How to use 32-bit constant?
• Restore return address
Ex: $t0 = 0x12345678
• Jump to the return address
LUI $t0, 0x1234
– JAL: Jump to a Label (Procedure), return address
ORI $t0, $t0, 0x5678
is stored in $ra (register 31)
– JR: Jump to the address which is stored in a
register
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Example in C: swap 2021

swap: MIPS
swap:
swap(int v[], int k) addi $sp,$sp, –4 ; create space on stack
{ sw $16, 0($sp) ; callee saved register put onto stack
int temp; sll $t2, $a2,2 ; multiply k by 4
addu $t2, $a1,$t2 ; address of v[k]
temp = v[k];
lw $15, 0($t2) ; load v[k]
v[k] = v[k+1]; lw $16, 4($t2) ; load v[k+1]
v[k+1] = temp; sw $16, 0($t2) ; store v[k+1] into v[k]
} sw $15, 4($t2) ; store old value of v[k] into v[k+1]
lw $16, 0($sp) ; callee saved register restored from stack
addi $sp,$sp, 4 ; restore top of stack
° Assume swap is called as a procedure
jr $31 ; return to place that called swap
° Assume temp is register $15; arguments in $a1, $a2; $16 is scratch
reg:
° Write MIPS code
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Procedure call: Factorial 2021
Quiz
• MIPS code: • Which one, caller or callee, has to save return
fact:
addi $sp, $sp, -8 # adjust stack for 2 items address?
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument • Which one, caller or callee, has to save
slti
beq
$t0,
$t0,
$a0, 1
$zero, L1
# test for n < 1
necessary registers?
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack • Is it necessary for leaf-procedure to save
jr
L1: addi
$ra
$a0, $a0, -1
#
#
and return
else decrement n
return address (in MIPS)?
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result n*fact(n-1)
jr $ra # and return
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MIPS arithmetic instructions 2021
MIPS logical instructions
Instruction Example Meaning Comments Instruction Example Meaning Comment
add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND
subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR
add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible xor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XOR
add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR
subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant
add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant
multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant
multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant
divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant
Hi = $2 mod $3 shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend)
divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable
Hi = $2 mod $3 shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable
Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable
Move from Lo mflo $1 $1 = Lo Used to get copy of Lo
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MIPS data transfer instructions 2021
Compare and Branch
Instruction Comment
SW 500(R4), R3 Store word
• Compare and Branch BEQ rs, rt, offset if R[rs] == R[rt] then
SH 502(R2), R3 Store half
PC- relative branch
SB 41(R3), R2 Store byte
LW R1, 30(R2) Load word

BNE rs, rt, offset <>
LH R1, 40(R3) Load halfword • BLEZ rs, offset if R[rs] <= 0 then PC-relative branch
LHU R1, 40(R3) Load halfword unsigned • BGTZ rs, offset >
LB R1, 40(R3) Load byte • BLTZ rs, offset <
LBU R1, 40(R3) Load byte unsigned
• BGEZ rs, offset >=
LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)
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MIPS jump, branch, compare instructions 2021
Start SPIM
Instruction Example Meaning
branch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100
Equal test; PC relative branch
branch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100
Not equal test; PC relative
set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; 2’s comp.
set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; 2’s comp.
set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0
Compare less than; natural no.
set l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0
Compare < constant; natural
jump j 10000 go to 10000
Jump to target address
jump register jr $31 go to $31
For switch, procedure return
jump and link jal 10000 $31 = PC + 4; go to 10000
For procedure call
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Load Program 2021
Execute Program
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Program data 2021
Set a break point
Set a break point at the conditional instruction
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Debug by stepping your code line by line 2021
Example
.text
.globl main
main:
li $t0, 0x2 # $t0  0x2
li $t1, 0x3 # $t1  0x3
addu $t2, $t0, $t1 # $t2  ADD($t0, $t1)
.text
.globl main
main:
ori $t0, $0, 0x2 # $t0  OR(0, 0x2)
ori $t1, $0, 0x3 # $t1  OR(0, 0x3)
addu $t2, $t0, $t1 # $t2  ADD($t0, $t1)
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Example 2021
Example
.data .data
n: .word 0x2 n: .word 0x2, 0x3, 0x4
m: .word 0x3
r: .space 4 .text
.globl main
.text main:
.globl main la $t5, n # load address of n to $t5
main: lw $t0, 0($t5) # load n to $t0
lw $t0, n # load n to $t0 lw $t1, 4($t5) # load n+4 to $t1
lw $t1, m # load m to $t1 addu $t2, $t0, $t1 # $t2  ADD($t0, $t1)
addu $t2, $t0, $t1 # $t2  ADD($t0, $t1) sw $t2, 8($t5) # store $t2 to n+8
sw $t2, r # store $t2 to r
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21

Lec02 ASA

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dce 2021

Advanced System Architectures

Computer can only understand binary values

Advanced System Architectures, Chapter 2 3 Advanced System Architectures, Chapter 2 4

instruction set Instruction

can perform Write

Advanced System Architectures, Chapter 1 5 Advanced System Architectures, Chapter 2 6

ISA Styles 2021

 Memory-memory: The operands is located in

LIW/”EPIC”? (IA-64. . .1999)

Advanced System Architectures, Chapter 2 27 Advanced System Architectures, Chapter 2 28

Advanced System Architectures, Chapter 2 35 Advanced System Architectures, Chapter 2 36

dce dce Example RISC ISA: HP Precision Architecture, HP PA-

• Simplified addressing modes.

• Each Group has 4-6 persons

Advanced System Architectures, Chapter 2 45 Advanced System Architectures, Chapter 2 46

Advanced System Architectures, Chapter 2 48

Advanced System Architectures, Chapter 2 49 Advanced System Architectures, Chapter 2 50

• Ex: SLL $t2, $s0, 8 • Why is there no NOT?

Advanced System Architectures, Chapter 2 51 Advanced System Architectures, Chapter 2 52

Advanced System Architectures, Chapter 2 56

• Load/Store instructions with offset 100011 01001 01000 0000000000010000

– The effective address (EA) = Rs + 16-bit 101011 01001 01000 0000000000010000

Advanced System Architectures, Chapter 2 59

Advanced System Architectures, Chapter 2 61 Advanced System Architectures, Chapter 2 62

Advanced System Architectures, Chapter 2 63 Advanced System Architectures, Chapter 2 64

Example in C: swap 2021

Advanced System Architectures, Chapter 2 69 Advanced System Architectures, Chapter 2 70

LW R1, 30(R2) Load word

Set a break point at the conditional instruction

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