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Group 4 Sap-1 Arch Cao
Group 4 Sap-1 Arch Cao
I. INTRODUCTION
purposes and not intended for commercial use. Its architecture is 8 bits, consisting of a 16
requires 4 address lines, which are supplied either by the Program Counter (PC) during
the computer run phase or by the 4 address switches during the program phase. The
memory can store only 5 instructions, limiting SAP to programs with a maximum of 16
instructions.
● SAP's functionality is limited to addition and subtraction, with no capability for logical
● The output unit of SAP-1 consists of 8 LEDs connected to the 8-bit output register. All
SAP-1.
● The SAP-1 computer is the first stage in this evolution, and it contains the fundamental
understanding of how a computer works and interacts with memory and other system
components such as input and output. The SAP-1 instruction set is relatively limited and
straightforward.
architecture. It makes use of an 8-bit central bus and has ten main components. A
pictorial representation of its architecture is shown below. Each of the individual
II. DESCRIPTION
The SAP (Simple-As-Possible) computer has been designed for beginners. The main purpose of
SAP is to introduce all the crucial ideas behind computer operation without burying you in unnecessary
detail. SAP-1 is the first stage in the evolution toward modern computers. SAP-1 is a big step for
beginners.
III. SAP-1 COMPONENTS
1. Program Counter
b. It signals the memory address of the next instruction to be fetched and executed.
a. During a computer run, the address in the PC is latched into the Memory Address
Register (MAR).
3. The RAM
a. The program code to be executed and data for SAP-1 computer is stored here.
b. During a computer run, the RAM receives 4-bit addresses from MAR and a read
operation is performed. Hence, the instruction or data word stored in RAM is placed on
c. It is asynchronous RAM, which means that the output data is available as soon as a valid
4. Instruction Register
computer.
5. Controller-Sequencer
a. It generates the control signals for each block so that actions occur in the desired
sequence. CLK signal is used to synchronize the overall operation of the SAP1 computer.
b. A 12-bit word comes out of the Controller-Sequencer block. This control word
determines how the registers will react to the next positive CLK edge.
6. Accumulator
a. It is a 8-bit buffer register that stores intermediate results during a computer run.
7. Adder/Subtractor
a. It is a 2's complement adder-subtractor.
b. This module is asynchronous (unblocked), which means that its contents can change as
8. B-register
a. It is an 8-bit buffer register which is primarily used to hold the other operand (one
9. Output Register
b. Binary display unit is the output device for the SAP-1 microprocessor.
● Advantages
implement.
● Disadvantages
1. Limited Functionality: SAP-1 is limited in terms of instruction set and lacks features
2. Low Speed: The architecture may not be optimized for high-speed processing due to its
simplicity.
Operation Description
SAP-1 SAP-2
PC is 4-bit. PC is 16-bit.
It does not have hexadecimal keyboard encoder. It has hexadecimal keyboard encoder.
MAR receives 4-bit address from PC. MAR receives 16-bit address from PC.
References
Okonkwo, K. (2020, December 7). Designing and implementing a SAP-1 Computer.
SAP-1-Computer. https://karenok.github.io/SAP-1-Computer/