Chapter 2

Basic Architecture of the 8086 and 8088 Microprocessors

8086 Microprocessor is an enhanced version of 8085 Microprocessor that was designed by Intel
in 1976. It is a 16-bit Microprocessor having 20-address bus so; it can address up to 2 20
=1048576=1 megabyte memory locations. The term 16 bit means that it’s ALU , its internal
registers and most of the instructions are designed to work with 16 bit binary words. It consists
of powerful instruction set, which provides operations like multiplication and division easily.

It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode
is suitable for system having multiple processors and Minimum mode is suitable for system
having a single processor.

The following diagram depicts the architecture of a 8086 Microprocessor.

Fig Block diagram of 8086 microprocessor

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Intel 8088 microprocessor has the same ALU, same registers and same instruction set as the
8086. But the only difference is 8088 has only 8-bit data. Hence, the 8088 can only
read/write/ports of only 8-bit data at a time.

Fig Block diagram for 8088 microprocessor

Comparison between 8086 and 8088 Microprocessors :

(i) 8086 has 16-bit data bus lines whereas 8088 has 8-data lines.
(ii) The memory address space of 8086 is organized as two 512kB banks whereas 8088
memory space is implemented as a single 1MByte memory bank.
(iii) 8086 has a 6-byte instruction queue whereas 8088 has a 4-byte instruction queue. The
reason for this is that 8088 can fetch only one byte at a time.
(iv) The byte and word data operations of 8086 are different from 8088. 8086 can read or
write either 8-bit or 16-bit word at a time, whereas 8088 can read only 8-bit data at a
time.

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REGISTER ORGANISATION:
The 14 registers of 8086 microprocessor are categorized into four groups. They are general-
purpose data registers, Pointer & Index registers, Segment registers and Flag register as shown in
the table below.

S.No Type Register width Name of the Registers

1 General purpose Registers (4) 16-bit AX,BX,CX,DX

8-bit AL,AH,BL,BH,CL,CH,DL,DH
2 Pointer Registers 16-bit Stack Pointer(SP)
Base Pointer (BP)
3 Index Registers 16-bit Source Index (SI)
Destination Index (DI)
4 Segment Registers 16-bit Code Segment(CS)
Data Segment(DS)
Stack Segment(SS)
Extra Segment(ES)
5 Instruction 16-bit Instruction Pointer (IP)
6 Flag (PSW) 16 bit Flag Register

The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU),
and The Execution Unit (EU).

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It
performs various machine cycles such as memory read, I/O read, etc. to transfer data between
memory and I/O devices.

BIU performs the following functions are as follows:

 It generates the 20-bit physical address for memory access.

 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue (supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue
(Instruction stream byte queue), and an Address Generation Circuit.

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 Instruction Pointer (IP):
 It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
 The address of the next instruction is calculated by using the formula CS x 10H + IP.

Segment registers
 Code Segment register: (16 Bit register): CS holds the base address for the Code
Segment. All programs are stored in the Code Segment and accessed via the IP.
 Data Segment register: (16 Bit register): DS holds the base address for the Data
Segment.
 Stack Segment register: (16 Bit register): SS holds the base address for the Stack
Segment.
 Extra Segment register: (16 Bit register): ES holds the base address for the Extra
Segment.
Address Generation Circuit:
The BIU has a Physical Address Generation Circuit.
It generates the 20-bit physical address using Segment and Offset addresses using the formula:
Physical Address = Segment Address x 10H + Offset Address
In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the calculation
unit which is used to calculate the physical address of an instruction in memory.
6 Byte Pre-fetch Queue:
 It is a 6-byte queue (FIFO).
 Fetching the next instruction (by BIU from CS) while executing the current instruction is
called pipelining.
 Gets flushed whenever a branch instruction occurs.
 The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can
have in 8086 is 6 bytes.
 The pre-Fetch queue is connected with the control unit which is responsible for decoding op-
code and operands and telling the execution unit what to do with the help of timing and
control signals.
 The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor
is called fetch, decode, execute type microprocessor.

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 2. The Execution Unit (EU):

The main components of the EU are General-purpose registers, the ALU, Special purpose
registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.
(Control Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

F 8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two 8-bit parts (higher and lower).
AX register: (Combination of AL and AH Registers) It holds operands and results during
multiplication and division operations. Also an accumulator during String operations.

BX register: (Combination of BL and BH Registers) It holds the memory address (offset

address) in indirect addressing modes.
CX register: (Combination of CL and CH Registers) It holds the count for instructions like a
loop, rotates, shifts and string operations.
DX register: (Combination of DL and DH Registers) It is used with AX to hold 32-bit values
during multiplication and division.
Special purpose registers (16-bit): Special purpose registers are called Offset registers also.
Which points to specific memory locations under each segment

We can understand the concept of segments as Textbook pages. Suppose there are 10 chapters
in one textbook and each chapter takes exactly 100 pages. So the book will contain 1000 pages.
Now suppose we want to access page number 575 from the book then 500 will be the segment
base address which can be anything in the context of microprocessors like Code, Data, Stack,
and Extra Segment. So 500 will be segment registers that are present in Bus Interface Unit
(BIU). And 500 + 75 is called an offset register through which we can reach on specific page
number under a specific segment.
Hence 500 is the segment base address and 75 is an offset address or (Instruction Pointer,
Stack Pointer, Base Pointer, Source Index, Destination Index) any of the above according to
their segment implementation.
 Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like
PUSH, POP, CALL, RET etc.

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 Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is
used to access random locations of the stack.
 Source Index: It holds offset address in Data Segment during string operations.
 Destination Index: It holds offset address in Extra Segment during string operations.
Flag Register: This register is also called status register. It is a 16 bit register which contains six
status flags and three control flags. So, only nine bits of the 16 bit register are defined and the
remaining seven bits are undefined. The 9 flag registers help to change or recognize the state of
the microprocessor.

Status flags

1. CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or
a borrow in case of subtraction.
2. PF - Parity Flag : This flag is set to 1, if the lower byte of the result contains even
number of 1’s else (for odd number of 1s ) set to zero.
3. AF- Auxiliary Carry Flag: This is set, if there is a carry from the lowest bit during
addition and subtraction.
4. ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed
by the previous instruction is zero
5. SF- Sign Flag : This flag is set, when the result of any computation is negative
6. OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination register.

Control flags

1. TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode.
2. IF- Interrupt Flag: If this flag is set, the mask able interrupt INTR of 8086 is enabled
and if it is zero, the interrupt is disabled.
3. DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is
‘0’, the string is processed beginning from the lowest address to the highest address, i.e.,
auto incrementing mode. Otherwise, the string is processed from the highest address
towards the lowest address, i.e., auto decrementing mode.