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Research Article: CMOS Ultra-Wideband Low Noise Amplifier Design
Research Article: CMOS Ultra-Wideband Low Noise Amplifier Design
Research Article
CMOS Ultra-Wideband Low Noise Amplifier Design
Copyright © 2013 K. Yousef et al. This is an open access article distributed under the Creative Commons Attribution License, which
permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth
extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB
and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency
band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 𝜇m
CMOS technology process.
𝑉𝑑𝑑 𝑉𝑑𝑑
𝑅𝑑3 𝐿 out
𝐿 𝑑2 𝐶out 𝑉out
𝐿 𝑑2
𝑅𝐺2 𝑅𝐺2 𝑉𝐺3
𝑅𝑑2 𝑀3
𝐶3 𝑅out
𝐿 𝑔2 𝐿 𝑔2
𝑉out 𝑀2
𝑀2
𝐶1 𝐶1 𝐿 𝑠3
𝐿 𝑑1 𝐶2 𝐿 𝑑1 𝐶2
𝑉in 𝐶𝑓 𝑅𝑓 𝑅𝐿 𝑉in 𝐶𝑓 𝑅𝑓
𝑀1 𝑀1
𝐿 𝑔1 𝐿 𝑔1
𝑅𝐺1 𝑅𝐺1
𝐿 𝑠1 𝐿 𝑠1
𝑉𝐺1 𝑉𝐺1
Figure 1: Current reuse UWB LNA (LNA1). Figure 4: Schematic circuit of LNA2.
Metal 6
𝑅𝑠 𝐿 𝑔 𝐶gs
𝑔𝑚 𝑉gs 𝑟𝑜 Port 1
𝑍in (Metal 6)
𝑉𝑠
Port 2
(Metal 6)
𝐿𝑠
Metal 2
Metal 4
20.0
18.0
𝑅FB
16.0
2
𝑖 rfb 14.0
Gain and NF (dB)
2 2
12.0
𝐿 𝐺1 𝑅lg 𝑒lg 𝑅𝑔 𝑒rg
+ 10.0
𝑅𝑆 𝑖𝑔2 𝐶gs1 𝑉gs1 𝑔 𝑉 𝑖𝑑2 2
𝑖𝑛,out
− 𝑚1 gs1 8.0
𝑒𝑠2 𝑅𝑠 6.0
𝑒2rs 4.0
𝐿𝑠 1 2.0
𝑅ls 0.0
2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5
𝑒ls2
Frequency (GHz)
Gain
Noise figure
Figure 3: Equivalent circuit of the fisrt stage for noise calculation
[1]. Figure 6: 𝑆21 (dB) and NF (dB) of LNA1.
4 International Journal of Microwave Science and Technology
15.0 0
−5.0
10.0
5.0
−15.0
Gain (dB)
−20.0
0
−25.0
−5.0
−30.0
−10.0 −35.0
2.0 3.5 5.0 6.5 8.0 9.5 11.0 12.5 14.0 15.5 17.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5
Frequency (GHz) Frequency (GHz)
LNA2 (planar Ind.) 𝑆22
LNA2 (3D Ind.) 𝑆11
Figure 7: 𝑆21 (dB) of LNA2. Figure 9: 𝑆11 (dB) and 𝑆22 (dB) of LNA1.
𝑆-parameter response 0
6.0
−2.5
5.0
−5.0
4.0
Noise figure (dB)
−7.5
𝑆11 (dB)
3.0
−10.0
2.0
−12.5
1.0 −15.0
0.0 −17.5
2.0 3.5 5.0 6.5 8.0 9.5 11.0 12.5 14.0 15.5 17.0 2.0 3.5 5.0 6.5 8.0 9.5 11.0 12.5 14.0 15.5 17.0
Frequency (GHz) Frequency (GHz)
LNA2 (planar Ind.) LNA2 (planar Ind.)
LNA2 (3D Ind.) LNA2 (3D Ind.)
circuit is shown in Figure 4 is an extended version of LNA1. It figure indicating the enhanced noise performance of the
has a wider operating band of frequency which extends from suggested design.
2.5 GHz to 16 GHz. Shunt-peaking technique increases the low frequency
Input impedance match has a special importance and gain and hence decreases the gain flatness while having a wide
consideration especially in wideband sensitive circuits operating bandwidth. In spite of shunt-peaking drawbacks, it
design. Input impedance matching bandwidth is broadened mainly facilitates LNA output impedance to load matching.
by the use of a weaker shunt capacitive-resistive feedback LNA2 bandwidth extension and gain flatness over its operat-
loop which mainly leads to quality factor reduction of the ing band of frequency are achieved through the removal of
input matching circuit. Weakness of shunt feedback strength shunt peaking. Moreover the control of gate peaking is used
not only reduces the input reflection coefficient over this to enhance the current reuse amplifier core gain.
wide bandwidth but it also reduces the input side injected For wideband output impedance matching, a unity com-
thermal noise which decreases the proposed LNA2 noise mon gate (CG) matching topology in addition to series
International Journal of Microwave Science and Technology 5
Table 1: Proposed UWB LNA performance summery in compari- is to implement these UWB LNAs to have a comparison
son to recently published UWB LNAs. between post-layout simulation results and measured results.
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