RTL Coding Guidelines

Think Synchronous
l Synchronous designs run smoothly through synthesis,
simulation and place-and-route
l Isolate necessary Asynchronous logic into separate blocks

ACK_SET
ADDR
ADDR_IN DECODE Asynchronous
+5
ACK
Address Decoder
GND
AS
ACK_CLR

How
HowamamI Igoing
goingto
to
synthesize this?
synthesize this?

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 77
 RTL Coding Guidelines
Think RTL
l Describe the circuits in terms of its registers and the
combinational logic between them
module GIZMO (A, CLK, Z);
module GIZMO (A, CLK, Z);
...
GIZMO ...
always @(A) begin : COMBO1...
always @(A) begin : COMBO1...
always @(posedge CLK)...
COMBO1 COMBO2 always @(posedge CLK)...
always @(B) begin : COMBO2...
always @(B) begin : COMBO2...
always @(posedge CLK) ...
Verilog
always RTL Code
@(posedge
end module;
CLK) ...
end module;

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 78
 RTL Coding Guidelines
Separate Combinational from Sequential
l Follows RTL coding style
l Easy to read and self-documenting

module
module EXAMPLE
EXAMPLE (DATA1,DATA2,CLK,Q)
(DATA1,DATA2,CLK,Q)
input
input DATA1,DATA2,CLK;
DATA1,DATA2,CLK;
output
output Q;
Q;
Combinational Logic
reg
reg DATA,
DATA, Q;
Q;
always DATA1 DATA
always @(DATA1 or
@(DATA1 or DATA2)
DATA2) GOBBLEDY Q
begin:
begin: COMBO
COMBO -GOOK
DATA2
DATA
DATA <=
<= GOBBLEDYGOOK(DATA1,DATA2);
GOBBLEDYGOOK(DATA1,DATA2);
end CLK
end Sequential Logic
always
always @(posedge
@(posedge CLK)
CLK)
begin: SEQUENTIAL
begin: SEQUENTIAL
QQ <=
<= DATA;
DATA;
end
end
endmodule
endmodule

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 79
 IF Statements

l IF statements infer multiplexer logic

always @(SEL or A or B)
always @(SEL or A or B) B 0
if (SEL) D
if (SEL) 1
D <= A; A
D <= A;
else
else
D <= B;
D <= B; SEL

l Latches are inferred unless all variables are assigned in all

branches

always @(SEL or A)
always @(SEL or A) 0
if (SEL)
if (SEL) 1
D
D <= A; A
D <= A;

SEL

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 80
 IF Statements (cont.)

l IF-ELSE-IF statements infer priority-encoded multiplexers

D 0
always @(SEL or A or B or C or D) 1
always @(SEL or A or B or C or D) C
if (SEL[2] == 1’b1)
if (SEL[2] == 1’b1)
OUT <= A;
OUT <= A;
else if (SEL[1] == 1’b1) SEL SEL[0]=‘1’ 0
else if (SEL[1] == 1’b1)
OUT <= B; 1
OUT <= B; B
else if (SEL[0] == 1’b1)
else if (SEL[0] == 1’b1)
OUT <= C;
OUT <= C;
else SEL[1]=‘1’ 0
else OUT
OUT <= D; 1
OUT <= D; A
SEL[2]=‘1’

Long delay from D to OUT

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 81
 IF Statements (cont.)

l Remove redundant conditions

l Use CASE statements if conditions are mutually exclusive

Don’t Do

always @(A or B or C or D or E) always @(A or B or C or D or E)

always @(A or B or C or D or E) always @(A or B or C or D or E)
if (A < B) if (A < B)
if (A < B) if (A < B)
OUT <= C; OUT <= C;
OUT <= C; OUT <= C;
else if (A > B) else if (A > B)
else if (A > B) else if (A > B)
OUT <= D; OUT <= D;
OUT <= D; OUT <= D;
else if (A == B) else
else if (A == B) else
OUT <= E; OUT <= E;
OUT <= E; OUT <= E;

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 82
 CASE Statements
Verilog Directives

l full_case indicates that all user-desired cases have been

specified
l Do not use default for one-hot encoding
always
always @(SEL
@(SEL or
or AA or
or BB or
or C)
C)
begin
begin
case
case (SEL)
(SEL) //synopsys
//synopsys full_case
one hot 3’b001 : OUT <= A;
full_case
3’b001 : OUT <= A;
3’b010
3’b010 :: OUT
OUT <=
<= B;
B;
Does not infer latches
3’b100
3’b100 :: OUT
OUT <=
<= C;
C;
endcase
endcase
end
end

always
always @(SEL
@(SEL or
or AA or
or B)
B)
begin
begin
case
case (SEL)
(SEL) Infers latches for OUT
3’b001
3’b001 :: OUT
OUT <=
<= A;
3’b010 : OUT <=
A;
B; because not all cases
3’b010 : OUT <= B;
3’b100
3’b100 :: OUT
OUT <=
<= C;
C; are specified
endcase
endcase
end
end

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 83
 CASE Statements
Verilog Directives (cont.)

l parallel_case indicates that all cases listed are mutually

exclusive to prevent priority-encoded logic

always
always @(SEL
@(SEL oror AA or
or BB or
or C)
C)
begin
begin
case
case (SEL)
(SEL) //synopsys
//synopsys parallel_case
parallel_case
AA :: OUT <= 3’b001;
OUT <= 3’b001;
BB :: OUT
OUT <=
<= 3’b010;
3’b010;
Infers a multiplexer
CC :: OUT <= 3’b100;
OUT <= 3’b100;
endcase
endcase
end
end

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 84
 CASE Statements
“CASE” vs. “IF-ELSE IF”

l Use IF-ELSE for 2-to-1 multiplexers

l Use CASE for n-to-1 multiplexers where n > 2
l Use IF-ELSE IF for priority encoders
l Use CASE with //synopsys parallel_case when conditions are
mutually exclusive
l Use CASE with //synopsys full_case when not all conditions are
specified
l Use CASE with //synopsys full_case parallel_case for one-hot Finite
State Machines (FSMs)

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 85
 CASE Statements
FSM Encoding

l Use CASE statements to describe FSMs

l Use //synopsys parallel_case to indicate mutual exclusivity
l Use //synopsys full_case when not all possible states are covered
(one-hot)
l Do not use default unless recovery state is desired

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 86
 CASE Statements
FSM Encoding (cont.)
module EXAMPLE (RESET, CLK, OUT);
module EXAMPLE (RESET, CLK, OUT);
input RESET, CLK;
input RESET, CLK;
output [1:0] OUT;
l Use parameter statements to
output [1:0] OUT;
parameter IDLE=4’b0001, GO=4’b0010, YIELD=4’b0100,
parameter IDLE=4’b0001, GO=4’b0010, YIELD=4’b0100,
define state values
STOP=4’b1000;
Use CASE statements and
STOP=4’b1000;
reg [3:0] CURRENT_STATE, NEXT_STATE; l
reg [3:0] CURRENT_STATE, NEXT_STATE;
always @(CURRENT_STATE)
always @(CURRENT_STATE) // synopsys parallel_case
begin: COMBO
begin: COMBO full_case to describe FSM
case (CURRENT_STATE) // synopsys full_case parallel_case
case (CURRENT_STATE) // synopsys full_case parallel_case
IDLE: begin NEXT_STATE = GO; OUT <= 2’b01; end
IDLE: begin NEXT_STATE = GO; OUT <= 2’b01; end
GO: begin NEXT_STATE = YIELD; OUT <= 2’b11; end
GO: begin NEXT_STATE = YIELD; OUT <= 2’b11; end
YIELD: begin NEXT_STATE = STOP; OUT <= 2’b10; end
YIELD: begin NEXT_STATE = STOP; OUT <= 2’b10; end
STOP: begin NEXT_STATE = IDLE; OUT <= 2’b00; end
STOP: begin NEXT_STATE = IDLE; OUT <= 2’b00; end
CURRENT_STATE
endcase
endcase
end
end
always @(posedge CLK or negedge RESET) NEXT_STATE
always @(posedge CLK or negedge RESET) STATE
begin: SEQUENTIAL AND OUTPUT
begin: SEQUENTIAL VECTOR
if (~RESET) DECODING
if (~RESET)
CURRENT_STATE <= IDLE;
CURRENT_STATE <= IDLE;
else
else
CURRENT_STATE <= NEXT_STATE
CURRENT_STATE <= NEXT_STATE
end
end
endmodule
endmodule

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 87
 CASE Statements
Watch for Unintentional Latches

l Completely specify all branches for every case and if statement

l Completely specify all outputs for every case and if statement
l Use //synopsys full_case if all desired cases have been specified

What’s wrong with this example?

( Missing Outputs )
( Missing Case )

always @(SEL)
always @(SEL)
begin
begin
case (SEL)
case (SEL)
2’b00: A <= 1’b1;
2’b00: A <= 1’b1;
2’b01: A <= 1’b0;
2’b01: A <= 1’b0;
2’b10: B <= 1’b1;
2’b10: B <= 1’b1;
endcase
endcase
end
end

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 88
 CASE Statements
Cascade Chain Inference

l Using cascade chains improves QoR significantly for

multiplexers
l Completely specify all possible cases for cascade chains to
be inferred
always @(SEL)
always @(SEL)
begin
begin
case (SEL)
case (SEL)
3’b000: OUT <= A;
3’b000: OUT <= A;
3’b001: OUT <= B;
3’b001: OUT <= B;
3’b010: OUT <= C;
3’b010: OUT <= C;
3’b011: OUT <= D;
3’b011: OUT <= D;
3’b100: OUT <= E;
3’b100: OUT <= E;
3’b101: OUT <= F;
3’b101: OUT <= F;
3’b110: OUT <= G;
3’b110: OUT <= G;
3’b111: OUT <= H;
3’b111: OUT <= H;
endcase
endcase
end
end

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 89
 Multiplexers
l Use IF or continuous assignment when select is a single-bit
signal
always
always @(SEL
@(SEL or
or AA or
or B)B)
if
if (SEL)
(SEL) B 0
DD <= D
<= A;
A; A 1
else
else
DD <=
<= B;
B;
-----------------------
----------------------- SEL
assign
assign DD == SEL
SEL ?? AA :: B;
B;

l Use CASE statements when select is a multi-bit bus

always @(SEL or A or B
always @(SEL or A or B
or C or D) A
or C or D) 00
begin
begin 01
case (SEL)
case (SEL)
B OUT
2’b00 : OUT <= A; 10
2’b00 : OUT <= A; C
2’b01 : OUT <= B;
2’b01 : OUT <= B; 11
2’b10 : OUT <= C; D
2’b10 : OUT <= C;
2’b11 : OUT <= D;
2’b11 : OUT <= D;
endcase
endcase
2
end SEL
end

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 90
 Operators
l Operators inferred from HDL
• Adder, Subtractor, AddSub (+, -), Multiplier (*)
• Comparators (>, >=, <, <=, ==, !=)
• Incrementer, Decrementer, IncDec (+1, -1)
l Example
module
module add
add (sum,
(sum, a,
a, b);
b);
output
output [15:0]
[15:0] sum;
sum;
input
input [15:0]
[15:0] a,
a, b;
b;
Design indicates two adders.
assign
assign sum
sum == aa ++ bb ++ 1’b1;
1’b1;
endmodule
endmodule

module add (sum, a, b);

module add (sum, a, b);
output [15:0] sum;
output [15:0] sum;
input [15:0] a, b;
input [15:0] a, b;
wire temp;
wire temp;
FE infers one adder with
assign {sum, temp} = {a, 1’b1} + {b, 1’b1};
assign {sum, temp} = {a, 1’b1} + {b, 1’b1}; carry chain.
endmodule
endmodule

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 94
 Operators
Operator Sharing
l Operators can be shared within an always block by default
l Users can disable sharing

A
+ Z

aring C
Sh MUX
always @(SEL or A or
th
B or C) Wi B
begin SEL Smaller
if (SEL)
Z = A+B;
else Wi A
tho
Z = A+C; ut S +
end har B
ing MUX Z
A
+ SEL
C
Larger

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 96
 Operators
Operator Balancing
l Use parenthesis to guide synthesis

A*B*C*D (A*B)*(C*D)

CIC Training Manual HDL Coding Hints: Generic Coding Techniques & Considerations - 98