IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO.

1, JANUARY 2012 41

Low Group Delay 3.1–10.6 GHz CMOS

Power Amplifier for UWB Applications
Rohana Sapawi, Student Member, IEEE, Ramesh K. Pokharel, Member, IEEE,
Sohiful A. Z. Murad, Student Member, IEEE, Awinash Anand, Nishal Koirala, H. Kanaya, Member, IEEE, and
K. Yoshida, Member, IEEE

Abstract—This letter proposes the design of a low group delay

ultra-wideband (UWB) power amplifier (PA) in 0 18 m CMOS
technology. The PA design employs a three-stage cascade common
source topology that has a different design concept from other
multi-stage topology to provide a broad bandwidth characteristic,
gain flatness of 11 48 0 6 dB, and low group delay variation
of 85 8 ps. A resistive shunt feedback technique is adopted at
the first stage of the amplifier to achieve good input matching,
which controls the upper frequency of the UWB system. The
third stage realizes the gain at the lower corner frequency and the
second stage is used to smooth the flatness of the gain curve. By
Fig. 1. Illustration of stagger-tuning concept for a three stage broadband PA.
using this method, the proposed design has the lowest group delay
variation among the recently reported CMOS PAs for 3.1 to 10.6
GHz applications.
Index Terms—Cascade topology, CMOS power amplifier (PA),
group delay, resistive shunt feedback, ultra-wideband (UWB).

I. INTRODUCTION
ECENTLY, ultra-wideband (UWB) technology has at-
R tracted great interest in both academia and industry to in-
vestigate more issues on related technology since the Federal
Communication Commission (FCC) officially released the reg-
ulation for UWB technology with the allocated frequency band
of 3.1–10.6 GHz. One of the most important UWB PA specifi-
cations, not given much attention for wideband communication,
is the group delay which is used as criteria to evaluate the phase
nonlinearity. It is very important to keep a small group delay
variation in the frequency band because this implies that if the
group delay varies with frequency, the time domain waveform
becomes distorted especially for UWB system using impulse
Manuscript received May 12, 2011; revised September 24, 2011; accepted
November 06, 2011. Date of publication December 19, 2011; date of current
version January 11, 2012. This work was supported in part by a grant of Regional
Innovation Cluster Program (Global Type 2nd Stage) from the Ministry of Ed-
ucation, Culture, Sports, Science and Technology (MEXT), by a Grant-in-Aid
for Scientific Research from JSPS (KIBAN-B), and by the VLSI Design and
Education Center (VDEC), the University of Tokyo in collaboration with CA-
DENCE Corporation and Agilent Corporation.
R. Sapawi is with the Graduate School of Information Science and Electrical
Engineering, Kyushu University, Fukuoka 819-0395, Japan and also with
the Department of Electronic, Faculty of Engineering, University Malaysia
Sarawak, Malaysia (e-mail: rohana@yossvr3.ed.kyushu-u.ac.jp).
R. K. Pokharel is with the EJUST Center, Kyushu University, Fukuoka 819-
0395, Japan (e-mail: pokharel@ed.kyushu-u.ac.jp).
S. A. Z. Murad, A. Anand, N. Koirala, H. Kanaya, and K.Yoshida are
with the Graduate School of Information Science and Electrical Engineering,
Kyushu University, Fukuoka 819-0395, Japan (e-mail: sohifula@yahoo.
com, anand@yossvr3.ed.kyushu-ac.jp, koirala@yossvr3.ed.kyushu-ac.jp,
kanaya@ed.kyushu-u.ac.ip; yoshida@ed.kyushu-u.ac.jp).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2011.2176475
1531-1309/$26.00 © 2011 IEEE
Fig. 2. Proposed UWB PA schematic.
signal [1]. It means that output does not retain its original iden-
tity without a PA withsmaller group delay.
Up to now, a number of UWB Pas have been reported with
CMOS technology for frequency bands 3.0–5.0 GHz [2],
3.0–7.0 GHz [3] and 6.0–10.6 GHz [4] implemented with var-
ious topologies such as common source inductive degeneration,
current-reused technique,and inter-stage wideband impedance
transformer, respectively. In the current-reused technique im-
plemented in UWB PA to reduce the power consumption, it is
very hard to satisfy the gain and wide range frequency band
from 3.1–10.6 [3]. To the authors’ best knowledge, another
UWB PA reported in [5] is the only one UWB PA that covers
the frequency band 3.1–10.6 GHz using artificial transmission
line topology. However, this fabricated UWB PA has high
group delay. Even previous reported works have shown that
increase in frequency bandwidth has tendency to deteriorate the
group delay. Therefore, in this letter, an excellent group delay
CMOS PA for 3.1–10.6 GHz by adopting three-stage cascade
common source with resistive shunt feedback technique is
proposed. To the best of our knowledge, the proposed UWB PA
implemented in technology has obtained an excellent
group delay, average gain flatness, and has the smallest chip
area so far as compared to other works reported for full band
UWB CMOS PAs.
II. CIRCUIT DESIGN
Multi-stage cascade topology was implemented in a low noise
amplifier (LNA) [6], but good flatness could not be achieved by
42
Fig. 3. Small signal circuit.
Fig. 4. Effect of inductor, L and L on the group delay variation.
Fig. 5. Chip micrograph of the proposed PA (0:88 mm x0:78 mm).
using this approach. Here, the proposed PA adopts three cas-
cade transistors and it has different design concept from other
multi-stage topology to provide a broad bandwidth character-
istic, gain flatness and low group delay. The stagger-tuning tech-
nique is employed and frequency responses of the three stages
are designed as shown in Fig. 1. Fig. 2 shows the proposed UWB
design. By using different center frequencies in various gain
stages, wide bandwidth is achieved. It is observed that both the
first stage and the third stage have a narrowband characteristic.
The first stage is a simple common source composed of and
to enhance the gain at the upper end of the desired frequency
(i.e., 10.6 GHz). In the third stage, the inductor, , is used as in-
ductive peaking to cut off the lower frequency (i.e., 3.1 GHz). In
order to improve the gain flatness in the middle frequency band,
the second stage is designed to have narrowband with flat gain
with optimized value of . When the signal division or nonide-
alities of the systems component occurs in this configuration, it
degrades the gain performance of the individual stage resulting
in the smaller output voltage swing and poor flatness. Hence,
the shunt peaking inductors and resistors are used at the indi-
vidual stage to enhance the gain over a wide bandwidth and to
flatten the band of all stages. The values of all the shunt peaking
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 22, NO. 1, JANUARY 2012
inductors and resistors are optimized to achieve 60% bandwidth
with an optimum group delay as desired to maximize pulse fi-
delity in this broadband system [7]. Resistive shunt feedback at
the first stage is to help to achieve good impedance over the re-
quired bandwidth. Hence, in this design, optimum value of the
feedback resistance, , is chosen to meet the matching and the
bandwidth of interest. A simple LC filter with and is em-
ployed to achieve input matching network. also serves
as dc blocking capacitor. is added to improve the broadband
output impedance of matching over the entire bandwidth.
III. GROUP DELAY VARIATION
Group delay is defined as the derivative of the phase of the
transfer function with respect to angular frequency as expressed
(1)
Here is the phase delay, a function of omega and is a variable in
the transfer function. As UWB PAs are supposed to transmit the
signal at short distance with very low power, the transfer func-
tion of the circuit can be determined using small signal equiva-
lent as shown in Fig. 3. Assuming that the NMOS output capac-
itance is negligible because it is too small, the overall transfer
function, H(s) can be expressed
(2)
where , ,
, , ,
, . From (2), at
and , the numerator has two zeros
in imaginary part which results in the group delay peaking
[8], [9], and the denominator is the third order polynomial
consisting of one real pole and two complex poles,
. The group delay performance for overall
transfer function H(s) can be derived as
(3)
and (4) as shown at the bottom of the page.
The requirement on group delay is to obtain linear response or
flat group delay i.e., small group delay in the passband. The (3)
indicates that small group delay variation for overall circuit can
be achieved if the value of the group delay in the denominator
is large enough. Hence, from (4) the best way to minimize the
value of group delay is to decrease the value of . Since the value
of is inversely proportional to and , increasing the value
of inductor and will result in the smallest possible group
(4)
SAPAWI et al.: LOW GROUP DELAY 3.1–10.6 GHZ CMOS PA 43

of the proposed PA is shown in Fig. 5. The chip size is

.
The measured S-parameter is shown in Fig. 6. As can be
seen, the measured gain of the proposed PA has high gain of
from 3.1 to 10.6 GHz while maintaining a 3 dB
bandwidth of 2.2 to 11.86 GHz.The input return loss of
and the output return loss of
, indicating a very broadband input and output matching
characteristic, are achieved. The total power consumption of the
proposed PA is 100 mW. As illustrated in Fig. 7, excellent phase
linearity (i.e., group delay variation) of ps is obtained
across the entire band. Fig. 8 shows the measured 1 dB com-
Fig. 6. Measured S-parameters. pression point (P1 dB). A good linearity, i.e., output 1 dB com-
pression point of 4.3 and 5 dBm are achieved at 5 and 6 GHz.
Table I summarizes the performance of recently published
UWB PAs [10]. As can be seen that the proposed UWB PA has
obtained average gain flatness, excellent group delay, and has
the smallest chip area so far compared to other works reported
on the full band UWB PAs. However, this PA design suffers
from high power consumption to achieve wide bandwidth and
good linearity simultaneously.
V. CONCLUSION
A 3.1 to 10.6 GHz ultra-wideband (UWB) power amplifier
(PA) was designed and implemented in m CMOS tech-
nology. By employing three cascade common source topology
Fig. 7. Comparison of measured and simulated group delay.
and resistive shunt feedback, the measurement results show that
the proposed design has excellent group delay variation, average
gain flatness, and has a small chip area. Furthermore, good lin-
earity is achieved across the entire band of interest.
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