ISSCC 2019 / SESSION 9 / HIGH-FREQUENCY TRANSCEIVERS FOR RADAR AND COMMUNICATIONS / 9.
9.4 A 145GHz FMCW-Radar Transceiver in 28nm CMOS
Akshay Visweswaran, Kristof Vaesen, Siddhartha Sinha, Ilja Ocket,
Miguel Glassee, Claude Desset, Andre Bourdoux, Piet Wambacq
imec, Leuven, Belgium
Indoor radar applications detecting people, vital signs and minute gestures require
a high range resolution. This paper presents a 145GHz FMCW radar transceiver
with on-chip antennas in 28nm bulk CMOS. An RF bandwidth of 13GHz yields an
11mm range resolution, and the high RF carrier permits greater velocity and
MIMO-angular resolution. An external chirp signal at 16.1GHz is upconverted to
145GHz via a cascade of two frequency triplers in the RX and TX. For MIMO
operation, a central chirp signal from a sub-sampling PLL integrated in 28nm
CMOS [1] is distributed to multiple TRX chips on a PCB, eliminating mm-wave
signal routing. The radar operates over a 0.15-to-10m range using fast sawtooth
chirps of 5-to-50μs duration. The beat frequency at IF fits between 400kHz and
15MHz. The on-chip TX leakage produces a strong beat near DC, suppressed via
active highpass filtering. However, group delays of the PA and LNA can shift the
beat into the RX passband. This is overcome by delaying the 16.1GHz RX chirp
on chip. The chip dissipates 500mW in continuous mode, with the option of a
low-power, duty-cycled FM transmission mode (for close ranges) enabled via fast
powering built into the transceiver.
Despite operation at approximately fT/2, thin metallization and substrate losses
affecting passives, and stringent density rules, the TX EIRP is 11dBm. The RX
achieves a noise figure and maximum conversion gain of 8dB and 84dB,
respectively. Beyond 100GHz, interfacing off-chip antennas on high-frequency
laminates via flip-chip or wire-bonding gets prohibitive due to insertion loss,
limited bandwidth, and lack of reproducibility. To overcome these, advanced
packaging technologies (e.g., eWLB, FO-WLP, InFO) and on-chip antennas are
viable solutions. This work explores sub-arrayed dipoles on chip that mitigate
deleterious substrate modes when driven in-phase, yielding an efficiency of 62%
compared to 52% for a single dipole.
The TX (see Fig. 9.4.1(a)) contains a PA driven by a cascade of transformer-
coupled gain stages and two triplers. The 16GHz pre-drivers are current-biased
differential amplifiers. Phase inversion for outer-code sequencing in the MIMO
configuration is implemented in stage A0 (Fig. 9.4.2(a)) driving the first tripler;
and is enabled by the selection of diff-pair sets M1,2 or M3,4 via switches MS1 and
MS2, respectively. The 48GHz amplifier (A1) is a pseudo-differential stage operating
in Class-AB. The two triplers (see Fig. 9.4.2(b)) are based on harmonic self-mixing
and circumvent the selectivity of injection-locked LC multipliers. The Class-AB
operation of M1,2 generates a second-harmonic (2f0) voltage on node ‘x’,
maximized via inductance Lss resonant at 2f0. The differential f0 drive at the gates
of M1,2, and the 2f0 swing at node ‘x’ generate antiphased 3rd-harmonic signals in
each device via their nonlinear transfer. The fractional bandwidth for both triplers
is 15%. A common-mode trap at the transformer load (see Fig. 9.4.2(b))
eliminates drain-modulation of transistor currents at 2f0 and ensures a clean
supply distribution.
The 145GHz PA and LNA comprise four transformer-coupled, neutralized, pseudo-
differential stages (see Fig. 9.4.2(c)). MOM capacitors, Cn, are chosen for
unconditional stability over process corners at the expense of GMAG. The PA,
characterized standalone, has a Psat of 7dBm. The LNA, optimized for noise
(antenna customized to its Zopt of 42Ω) and 1dB compression, is stagger-tuned
for a flat frequency response. The PA and LNA draw 130mA and 30mA,
respectively.
The sub-arrayed dipoles are drawn in the Al-passivation layer (see Fig. 9.4.2(d)).
An artificial magnetic conductor is formed by the pattern metal-filled oxide, 100um
thick substrate, and PCB reflector. It is optimized for phase coherence of direct
and reflected paths. Partial cancellation of the dominant substrate modes is
achieved when the dipoles, separated by 450μm, are driven in phase. TX and RX
antennas are kept 3.7mm apart to minimize crosstalk (see Fig. 9.4.2(e)).
Minimized bondwires and supply-decoupling networks on the back of the PCB
reduce interference. The chip is surrounded by a 250μm thick RF absorber
(Emerson and CumingTM BSR-1, 25).
The RX (see Fig. 9.4.1(a)) comprises the 0.9V RF front-end, analog processing at
IF and a replica of the TX buffering and upconversion. The LNA is interfaced to
the RX mixer via transformer T1 (see Fig. 9.4.3(a)). The switching quad (M3-6) is
168 • 2019 IEEE International Solid-State Circuits Conference
loaded by a voltage-regulation loop that high-pass filters the TX-leakage beat and
suppresses DC offsets due to limited mixer port isolation at 145GHz. The
impedance of M7,8 is lowered by the loop gain (illustrated in Fig. 9.4.3(c)), forming
a first-order highpass filter. The dominant pole in this loop is at the output of
folded-cascode amplifiers A1,2, using Miller capacitance Cc. The RX passband
corner frequency is 400kHz. Correlated noise from VCM is subtracted at the
differential output. The mixer drives a Gm stage (see Fig. 9.4.1(b)), which is AC-
coupled to shunt-feedback amplifier AF1. This interface prevents NF degradation,
increases filtering, and transitions seamlessly from a 0.9V to a 1.8V supply. The
Gm stage comprises an NMOS differential pair with PMOS loads. The AC-coupling
is also designed for 400kHz, yielding an overall 40dB/dec filter roll-off (see Fig.
9.4.3(b)). AF1 is a two-stage opamp (see Fig. 9.4.3(c)). The degenerated CMFB
amplifier introduces a zero (RCMCCM) to stabilize the loop. Because of AC-coupling,
when VCM is zero at startup, M1 & M2 are cut off. Ramping VCM does not turn on
AF1. Current bleeders (M3 and M4), placed across the input pair trigger the CMFB
loop with an increase of VCM, and subsequently bias M1,2 via the resistive feedback.
The DAC frequency of the digital PLL (chirp generator) and off-chip ADC/DSP is
80MHz. The aliases and noise above 40MHz are suppressed by a fully differential,
6th-order Butterworth filter. The implementation and simulated performance of the
filter are shown in Fig. 9.4.3(d), which uses the amplifier of Fig. 9.4.3(c) (sans
current bleeders) for its three stages. Feedback stages AF1 and AF2 cumulatively
provide an 8-bit gain programmability of 60dB. The programmable delay, τ, in
Fig. 9.4.1(b) (0 to 80ps, 13ps steps) is designed at 16GHz using multiplexed
inverters (see Fig. 9.4.4(a)) to compensate the LNA and PA delays. Delaying the
reference chirp prior to mixing eliminates the TX-leakage tone by shifting it to a
lower frequency with sufficient suppression.
The radar transceiver (see Fig. 9.4.7) is characterized using the KeysightTM PNAx
and VdiTM D-band extension module. Far-field measurements at 145GHz of power
versus distance, r, are shown in Fig. 9.4.4(b), and agree with the expected 1/r2
gradient. The average EIRP is 11dBm with a ±0.5dB spread. The TX operates with
a saturated PA and Fig. 9.4.4(b) shows a 3dB bandwidth of 127 to 154GHz.The
RX response of Fig. 9.4.5(a), measured at 10MHz IF, shows a 3dB bandwidth of
138 to 151GHz. Different gain settings show a programmability of 57dB (±1dB).
The measured TX-RX isolation is shown in Fig. 9.4.4(d). The RX noise is
expressed as the effective isotropic noise figure (EINF) [2] since measuring the
antenna standalone at 145GHz is not a trivial undertaking. The EINF is ~6dB at
10MHz IF. Adding the simulated antenna gain of 2.5dBi shows good agreement
with the simulated RX NF of 8dB. The NF at 400kHz is 5dB higher due to flicker
noise. The IF response measured with a 145GHz carrier is shown in Fig. 9.4.5(b).
MIMO captures (2×2 assembly, Fig. 9.4.1(c)) of a heartbeat emulator at 2m using
a 10GHz chirp signal are shown in Fig. 9.4.5(c). The speaker diaphragm driven
by a Raspberry-PiTM board has a 1mm displacement and is excited at 1Hz and 5Hz
as seen from the ADC-ZedboardTM-MatlabTM capture. The phase-angle variation is
limited by fixed objects in the same range bin, as explained in the inset. MIMO
experimentation along the azimuth is shown in Fig. 9.4.5(d). The angle of
incidence of three closely spaced objects is evaluated using the MUSIC
classification algorithm.
Compared to state-of-the-art integrated radars (see Fig. 9.4.6), this work shows
a superior EIRP and NF with a low power consumption.
Acknowledgement:
The work is supported by Panasonic and the EC H2020 grant 783119.
References:
[1] Q. Shi et al., “A Self-Calibrated 16GHz Subsampling-PLL-Based 30μs Fast
Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error,” ISSCC,
Paper 26.1, Feb. 2019.
[2] K. Khalaf et al., “A 60-GHz 8-Way Phased-Array Front-End With T/R Switching
and Calibration-Free Beamsteering in 28-nm CMOS”, IEEE JSSC, vol. 53, no. 7,
pp. 2001-2011, July 2018.
[3] J. Grzyb et al., "A 210–270-GHz circularly polarized FMCW radar with a single-
lens-coupled SiGe HBT chip," IEEE Trans. THz Sci. Technol., vol. 6, pp. 771-783,
2016.
[4] B. Ginsburg et al., “A 160GHz Pulsed Radar in 65nm CMOS,” IEEE JSSC., vol.
49, no. 4, pp. 984-995, April 2014.
[5] B. Ginsburg et al., “A Multimode 76-to-81GHz Automotive Radar Transceiver
with Autonomous Monitoring,” ISSCC, pp. 158-159, 2018.
[6] H.J. Ng et al., "Miniaturized 122 GHz System-on-Chip Radar Sensor with On-
Chip Antennas Utilizing a Novel Antenna Design Approach," IEEE MTT-S Int.
Microwave Symp., 2016.
978-1-5386-8531-0/19/$31.00 ©2019 IEEE
 ISSCC 2019 / February 19, 2019 / 10:15 AM

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Figure 9.4.2: Circuit diagram of (a) phase inversion stage, A0, of Fig. 9.4.1(a),
Figure 9.4.1: Block diagram of the 145GHz FMCW transceiver, showing (a) the (b) frequency tripler (c) PA and LNA. (d) Cross section of the sub-arrayed dipole,
transmitter, (b) the receiver, and (c) the 2×2 MIMO assembly on a PCB. (e) 3D view of the chip-mount and packaging.

Figure 9.4.3: Circuit diagram of (a) RX mixer and TX-leakage suppression filter, Figure 9.4.4: (a) Programmable on-chip delay for leakage suppression, (b) far-
(b) Illustration of the RX frequency response, (c) two-stage amplifier, AF1, of field measures of EIRP for varying distance (c) transfer characteristic of the
Fig. 9.4.1(b), (d) 6th-order Butterworth filter and simulation results. transmitter, (d) TX-RX leakage measurement.

Figure 9.4.5: (a) RX gain and EINF, (b) IF response of the receiver, (c) MIMO
capture of heartbeat emulator at 2m, with 1mm displacement, (d) MIMO
experiment showing angular resolution of targets using the MUSIC algorithm. Figure 9.4.6: Table comparing this work with state-of-the-art integrated radars.

DIGEST OF TECHNICAL PAPERS • 169

 ISSCC 2019 PAPER CONTINUATIONS

Figure 9.4.7: Die micrograph and zoomed-in view of the MIMO assembly board show-
ing the three TRX chips.

• 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE