IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO.

10, OCTOBER 2015 2533

A 65 nm CMOS Power Amplifier With Peak PAE

above 18.9% From 57 to 66 GHz Using Synthesized
Transformer-Based Matching Network
Wanxin Ye, Student Member, IEEE, Kaixue Ma, Senior Member, IEEE, Kiat Seng Yeo, Senior Member, IEEE,
and Qiong Zou, Member, IEEE

Abstract—Maintaining good power performance in a large

bandwidth continues to challenge the design of millimeter-wave
(mm-wave) power amplifiers (PAs), including mm-wave PAs with
transformer-based matching networks (TMNs). With a TMN
synthesizing method which is proposed based on the derived
matching equations of TMN, this challenge is addressed in this
paper for wideband mm-wave PAs by designing both inter-stage
matching networks and output matching network with small
mismatch in the entire operating bandwidth. A 60 GHz PA with
synthesized TMNs is designed in a 65 nm bulk CMOS technology,
achieving smaller degradation of power performance in the 9 GHz
bandwidth compared to reported works in more advanced CMOS
technologies. From 57 to 66 GHz, the PA is measured with satu-
rated output power of 13.94 to 14.35 dBm, of 10.81
to 11.68 dBm, and peak power added efficiency (PAE) of 18.9% to
21.1%. The PA is capable of delivering 16QAM modulated signal
with output power larger than 10.8 dBm and PAE higher than
10.1% in all the 4 channels of 802.11ad when EVM is 8.91%.
Index Terms—CMOS, millimeter-wave, power amplifier, syn-
thesize, transformer-based matching network (TMN), 60 GHz.

I. INTRODUCTION

T HE LARGE bandwidth available at millimeter-wave

(mm-wave) frequency empowers wireless communi-
cation standards such as 802.11ad at the 60 GHz unlicensed
frequency band to achieve data rates of multi-Gbps [1]–[3].
However, at such a high frequency, the design of power am-
plifiers (PAs) becomes very challenging, especially when PAs
are implemented in CMOS technologies which suffer from
low supply voltage, lossy substrate, and low gain of transis-
Fig. 1. (a) Maximum peak PAE, and the ratio of minimum peak PAE over max-
tors at mm-wave. To achieve larger output power and higher imum peak PAE from 57 to 66 GHz for 60 GHz PAs in CMOS. (b) Measured
efficiency against the low supply voltage and lossy substrate, peak PAE of this work from 57 to 66 GHz.
transformer-based matching networks (TMNs) are widely used
in mm-wave PAs [4]–[17]. TMNs offer convenient realization swing at transistor output and allows the output power of PAs to
of pseudo-differential architecture, which doubles the voltage be increased by a factor of 4 for the same load impedance [18].
Besides, TMNs have potentially less insertion loss compared
Manuscript received April 25, 2015; revised July 07, 2015; accepted August
to LC matching networks [19], and can be used for power
17, 2015. Date of current version September 25, 2015. The authors would like combining [8]–[17] to further increase the output power of PAs
to thank the foundry support provided by Global Foundries. This paper was for long distance communication.
recommended by Associate Editor R. Gomez-Garcia. To take full advantage of the large bandwidth available at
W. Ye and Q. Zou are with the IC Design Centre of Excellence
(VIRTUS), School of Electrical and Electronic Engineering, Nanyang mm-wave, PAs should have good power performance over the
Technological University, Singapore 639798 (e-mail: wanxinye@ieee.org; entire operating bandwidth rather than just at certain frequency
zouqiong@ntu.edu.sg). points. This, however, still remains as a challenge for CMOS
K. Ma is with University of Electronic Science and Technology of China,
PAs at mm-wave due to the low gain of transistors. As will be
Chengdu 610054, China (e-mail: kxma@ieee.org).
K. S. Yeo is with the IC Design Centre of Excellence (VIRTUS), School of explained in Section II of this paper, when the gain of tran-
Electrical and Electronic Engineering, Nanyang Technological University, Sin- sistor is low, the power performance of PA is not only related
gapore 639798, and also with Singapore University of Technology and Design, to the power performance of the output stage, but also highly
Singapore 487372 (e-mail: kiatseng_yeo@sutd.edu.sg).
Color versions of one or more of the figures in this paper are available online
dependent on that of the driver stages. Consequently, similar to
at http://ieeexplore.ieee.org. the situation where PA's output matching network is required
Digital Object Identifier 10.1109/TCSI.2015.2476315 to provide optimum load impedance [20] for transistors

1549-8328 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2534 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 10, OCTOBER 2015

in the output stage, the inter-stage matching networks are also

required to provide for transistors in driver stages. Unfor-
tunately, due to the large gate capacitance loaded on inter-stage
matching networks, it is much more challenging for an inter-
stage matching network to provide with small mismatch in
a large bandwidth, resulting large degradation of power perfor-
mance for wideband mm-wave PAs. Fig. 1(a) shows the peak
power added efficiency (PAE) achieved by prior-art 60 GHz
CMOS PAs designed using TMN [4]–[6], [11]–[15]. The op-
timization of output matching network has facilitated some of
them to achieve maximum peak PAE above 20% at some fre-
quency points. However, it is observed that the minimum peak
PAE in the bandwidth of 57 to 66 GHz are only around 70% or
even 40% of their maximum peak PAE.
In this work, the TMNs for both output matching and inter-
stage matching of a 60 GHz PA are designed to provide for
transistors in the entire operating bandwidth of 57 to 66 GHz.
As shown in Fig. 1(b), the designed PA in 65 nm CMOS has
achieved peak PAE of 18.9% to 21.1% in the 9 GHz bandwidth, Fig. 2. PAE of a two-stage PA affected by output stage gain and driver stage
PAE. (a) Block diagram of a two-stage PA. (b) PAE of the PA with
corresponding to a minimum peak PAE that is up to 89.6% of variations of and . and are assumed.
the maximum peak PAE. To achieve wideband matching with
TMN, the matching equations of TMN are derived and a TMN gain compression should happen at the output stage. However,
synthesizing method is proposed based on the modeling and the small gain compression of the driver stage is at the cost of
analysis of the matching mechanism of TMN. The solution of low , which as indicated by (1), will cause to be
the matching equations gives all the possible values of trans- much smaller than when is low.
former parameters that can realize matching for a TMN with At 60 GHz, the maximum available power gain of transistors
given source and load, enabling the comparison and selection in 65 nm CMOS is only around 10 dB [6], [17]. Considering
of transformer parameters according to the TMN bandwidth. the insertion loss of the output matching network and the gain
Based on the matching equations, the proposed TMN synthe- compression when PA is driven into its high efficiency region,
sizing method provides a systematic design flow to build a trans- the gain of the output stage will be even lower. Fig. 2(b) plots
former according to the bandwidth requirement, where an ad- of the two-stage PA as a function of and
ditional capacitor is also considered as a design freedom to im- based on (1), where and are
prove the TMN bandwidth or make the selected transformer pa- assumed. It can be seen that when is 10 dB or lower, a
rameters easier to realize with metal layers available in a given small will cause to be much smaller than .
technology. For example supposing when the PA is driven
This paper is organized as follows. Section II discusses the into saturation, a driver efficiency of will result
design issues of mm-wave PA and design challenges of TMNs. , reducing to only half of .
The modeling, matching mechanism, matching equations, and Due to load-pull effect, a transistor requires an optimum
the synthesizing of TMN are then introduced in Section III. Sec- load impedance to be provided at its output in order
tion IV shows the design of a 60 GHz PA using the proposed to achieve large output power and high efficiency [20]. To
TMN synthesizing method. Section V gives the measurement improve the efficiency of driver stages for mm-wave PA, the
result and Section VI concludes the paper. inter-stage matching networks need to be designed such that
II. DESIGN ISSUES OF MM-WAVE PAs WITH TMN is provided for driver stage transistors, which is similar to
the requirement that output matching network should provide
A. Effect of Driver Stage Power Performance at mm-Wave for output stage transistors. However, due to the large gate
Fig. 2(a) shows a simplified two-stage PA containing one capacitance of CMOS transistors, the load quality factor
driver stage and one output stage. Assuming the power gain of inter-stage matching networks is much higher than that of the
( ) and PAE of the two stages are , , and , output matching network where the load is a 50 resistance.
respectively, the PAE of the PA can be derived as Therefore, it is much more challenging to design inter-stage
matching networks with large bandwidth. When inter-stage
matching networks can only provide for transistors with
small mismatch in part of the operating bandwidth, the power
(1) performance of driver stages, and consequently the power
performance of the mm-wave PA, will degrade obviously in
Also, of the PA is given by the operating bandwidth.
(2)
B. Mismatch and Degradation of Power Performance
Equation (2) indicates that in order to achieve high In order to know the allowed mismatch with respect to ,
, the PA should be designed with load-pull simulations were performed at 60 GHz for transistors
, namely as the gain of PA compresses, most of the with sizes of 20 , 40 , and 90 at their . The
YE et al.: A 65 NM CMOS POWER AMPLIFIER WITH PEAK PAE ABOVE 18.9% FROM 57 TO 66 GHz
Fig. 3. Mismatch to and the degradation of transistor power performance.
(a) Load-pull simulation result of a transistor with size of 40 at its
(b) Maximum degradation of power performance that may be caused by given
mismatches.
contours of and PAE for the transistor with size of 40
are shown in Fig. 3(a) on a Smith chart. Because load-pull con-
tours are more like ellipses [21] whereas curves representing
impedances with a constant mismatch to are circles, im-
pedances with the same mismatch may correspond to different
degradations of power performance. Fig. 3(b) plots the max-
imum degradation of power performance that may be caused by
impedances with given mismatches. It is observed that the rela-
tionship between the degradation of power performance and the
mismatch with respect to is independent of transistor size,
also the degradation of power performance increases rapidly as
the mismatch with respect to increases. For the degrada-
tion of to be less than 0.75 dB and the degradation of PAE
to be less than 5%, the mismatch with respect to needs
to be smaller than 12 dB. When the operating bandwidth is
large, e.g., the 9 GHz bandwidth of 802.11ad, maintaining mis-
match below 12 dB can be very challenging, especially for
inter-stage matching networks with high . of each matching network, which can be transistor input/output
C. Challenges of TMN Design
When a TMN is used for the inter-stage matching or the
output matching of a mm-wave PA, a suitable transformer
should be designed according to the source and load of the
TMN in order to achieve small mismatch (e.g., 12 dB)
in the entire operating bandwidth. Transformers can be built
flexibly at mm-wave by varying the structure, the metal layers
used, the trace width and dimension of each winding, the
distance between windings, and also the turn number of each
winding. Besides transformer, the matching of TMN may also
be adjusted by an additional capacitor added on the source
or load side [4], [14]. The flexibilities of transformer and the
additional capacitor provide many freedoms for the design of
TMN and increase the bandwidth that can be achieved for a
2535
Fig. 4. (a) A simplified schematic of a PA using TMNs for input, inter-stage,
and output matching. (b) A TMN model including source, transformer, and load.
TMN with given source and load. However, with so many pos-
sible variations, the design of TMN becomes very challenging
and complicated. To find the proper transformer and addi-
tional capacitor, it often requires a tremendous amount of EM
simulations for transformers which are very time consuming.
Satisfying the bandwidth requirement, especially for inter-stage
matching networks with high , may need the transformer to
. have a specific inductance, coupling coefficient and turn ratio,
however, the value of these parameters that can be realized is
related to the structure of transformer and is often limited by
the metal layers available in a given technology. To address
these problems, a systematic analysis and design method of
TMN is highly demanded.
III. PROPOSED TMN SYNTHESIZING METHOD
To improve the power performance of wideband mm-wave
PAs with TMN, in this section a TMN synthesizing method
is proposed based on matching equations derived according to
the modeling and the analysis of the matching mechanism of
TMN. The proposed TMN synthesizing method is demonstrated
through an inter-stage matching network which achieves mis-
match below 12 dB in the target bandwidth of 57 to 66 GHz
despite a large of 6.22.
A. TMN Modeling
Fig. 4(a) shows a simplified schematic of a PA using TMNs
for input, inter-stage, and output matching. Resistors and ca-
pacitors in gray lines represent the source and load impedance
impedance, the 50 source/load of PA, or possibly some ca-
pacitance additionally added. To analyze the matching of these
TMNs, a model of TMN is given in Fig. 4(b). The transformer
model included is based on the model reported in [22], where
is the inductance of the primary winding, is the magnetic
coupling coefficient, is the turn ratio defined by
( is the inductance of the secondary winding), and
are the parasitic resistances of the primary and the sec-
ondary winding. The transformer circled by blue dashed line in
the model is an ideal transformer with turn ratio of .
and are two capacitors added in the TMN model to char-
acterize the parasitic capacitances of transformer.
It is worth noting that the transformer in TMN is modeled
without using center-tap, and the effects of all parasitic capac-
itances including inter-winding capacitance, winding to sub-
2536 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 10, OCTOBER 2015

strate capacitance and winding-self capacitance are contributed

to and . To make such simplification while maintaining
enough accuracy of the model for matching analysis, the miller
effect of inter-winding capacitance is considered. As can be seen
from Fig. 4(a), the connections of transformers are different
when they are used in different matching networks. In inter-
stage matching networks, both windings of transformer are con-
nected differentially with center-taps being AC-ground. In input Fig. 5. The model of TMN redrawn for matching analysis.
or output matching networks, the transformer is used as a balun
where one winding is differentially connected with center-tap
being AC-ground, whereas the other winding is connected to
a single-ended 50 impedance with center-tap being floating.
When the connection of a transformer changes, the voltage dis-
tribution on its windings will change as well, causing a variation
of the equivalent capacitance at the two ports of transformer due
to the miller effect of inter-winding capacitance. In this work,
to characterize this phenomenon while maintaining the model
simple for matching analysis, the transformer model included in
Fig. 4(b) is adopted while the value of parameters in the model
are extracted separately for each connection. Because the ef-
fect of inter-winding capacitances are contributed to and
, their values will have relatively large variation when con-
Fig. 6. Matching mechanism of TMN.
nection changes. Other parameters including , , , ,
and also have small variations, which is due to skin effect As shown in Fig. 5, by separating the TMN model into two
and proximity effect [23] as voltage distribution in transformer parts from the reference plane, the left part only contains
changes. Compared to transformer models with center-tap and parameters and of the transformer, while the parameter
inter-winding capacitance [22], [24], [25], the model in Fig. 4(b) only appears in the ideal transformer contained in the right
contains much less parameters and allows easier analysis of the part. Since ideal transformers change impedance only for its
matching of TMN. magnitude while keeping the ratio between its imaginary part
For the source and load of TMN, in the model they are all and real part a constant, when the TMN in Fig. 5 is matched in
simplified as R and C in parallel. To maintain high accuracy conjugate, there is
in a wide frequency range, generally the output impedance of
MOS transistor is modeled as R and C in parallel, but the input (4)
impedance of MOS transistor is modeled as R and C in series. (5)
In this work, in order to simplify the TMN matching analysis,
the series RC model for input impedance is converted to parallel where parameter is defined for any impedance Z as the ratio
RC model as well [26], so that the parasitic capacitance of the between its imaginary part and real part.
transistor and the parasitic capacitance of the transformer are
(6)
in parallel connection and can be viewed as one capacitor. The
conversion does not introduce any error to the calculation of
It can be seen that has the same magnitude as quality factor
transformer parameters for matching, as long as the conversion
, but the difference is that is always positive
and the calculation of transformer parameters are performed at
whereas can be positive or negative, corresponding to Z being
the same frequency.
inductive or capacitive.
B. Matching Mechanism and Matching Equations of TMN The matching mechanism of TMN, as shown in Fig. 6, can
be viewed as accomplished in the following two steps:
Fig. 5 redraws the TMN model for matching analysis. As
Step 1: of is changed by induc-
analyzed in Section II, the design target of inter-stage matching
tors and , such that
networks and output matching network is to provide for
the transistors they are connect to. With and retrieved
This step is shown in Fig. 6 as the red line
according to transistor's load-pull characteristics, the target
and the green line, and it requires the value of
for these matching networks to provide is equivalent to
to be selected correspondingly for each value of
achieving reflection coefficient in Fig. 5. It is noted that
. Solving (5) gives the first matching equa-
is also the target of input matching network, except that
tion of TMN as shown by (7), at the bottom of
is a 50 resistance for an input matching network.
the next page, in which and
Because the source side of the matching network is either
.
transistor output or a 50 resistance, it can be expected that
Step 2: The magnitude of is adjusted by the ideal
is much lower than of the transformer in practical designs.
transformer such that
Therefore, the parasitic resistance of transformer only has
As shown by the blue line in Fig. 6, in this step
small effect on the source side, and there is
the impedance is changed along a constant curve
(3) on Smith chart, which is also a constant curve.
YE et al.: A 65 NM CMOS POWER AMPLIFIER WITH PEAK PAE ABOVE 18.9% FROM 57 TO 66 GHz 2537

With a turn ratio of for the ideal transformer,

there is relationship that
(8)

Solving equations (4) and (8) gives the second

matching equation of TMN as shown by (9), at the
bottom of the page. For each value of , there is
also a corresponding value of for the TMN to be
matched.
Specially, if , the two matching equations
can be simplified as

(10)

(11)

Because can never be larger than 1, the value of is

required to be larger than a minimum value which is given by
(12) if and are not zero, or by (13) if
. (See (12) and (13) at the bottom of the page.)
By using matching equations (7) and (9), the required and
for each value of can be directly calculated. With the help
of a CAD software, the bandwidth of TMN with smaller
than a specific value can be calculated and compared for trans-
formers with all possible values of and the corresponding
values of and , enabling the selection of TMN solutions ac-
cording to the required bandwidth. A TMN synthesizing method
can then be developed, enabling the transformer and additional
capacitor in TMN to be designed systematically, and facilitating
Fig. 7. Flow chart of TMN synthesizing based on the derived matching equa-
mm-wave PAs based on TMNs to achieve good power perfor- tions of TMN.
mance in the entire operating bandwidth.
suitable structure and size, and the additional capacitor which
C. TMN Synthesizing Procedure may be added on the source or load side of the TMN, can be de-
Fig. 7 shows the design flow of the proposed TMN synthe- signed according to the operating bandwidth of the mm-wave
sizing method. By following the design flow, a transformer with PA.

(7)

(9)

(12)

(13)
2538 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 10, OCTOBER 2015

Fig. 9. Bandwidth with for of 40 to 200 pH. Adding of

Fig. 8. and calculated according to (7) and (9) for of 40 to 200 pH. additional 10 fF capacitor on the source side makes the calculated parameters
easier to realize.
When designing transformers according to the calculated
, and , generally the structure of transformer is mostly
determined by , while the size and turn number of each
transformer winding are mostly determined by and .
Depending on the metal layers available in a given technology,
some parameter values may be difficult to realize. In such case,
an additional capacitor can be added on the source or load side
and its value can be adjusted so that a different solution can be
selected. A more flexible realization of selected , and
using a series connection of transformer and inductor can also
Fig. 10. (a) Metal layers available in the 65 nm CMOS technology. (b) Con-
be utilized, as will be shown in Section IV for the design of the centric transformer designed for the TMN synthesizing example.
input matching network of the 60 GHz PA.
It is worth noting that at the beginning of the synthesizing, the
parasitics of transformer ( , , , ) are unknown.
In order to calculate and , these parasitics are assumed with
some typical values at the beginning, because the variation of
these parasitics and their effects on matching of TMN are rela-
tively small compared to those of , , and . To ensure small
differences between the parasitics used for calculation and the
parasitics of the synthesized transformer, several times of iter-
ation may be required by using the parasitics of the designed
transformer for the next round of calculation.
To demonstrate the TMN synthesizing method, suppose an
inter-stage matching network needs to be designed for a 60 GHz
PA and the related transistors are modeled as , Fig. 11. Simulated S-parameters of the TMN matched by the synthesized con-
centric transformer.
, , . From EM simulation and
modeling of transformers for 60 GHz PA, it is known that typical
values of parasitics for transformers in concentric architecture
are , , when
both windings are connected differentially.
With matching equations (7) and (9), the required and for
in the range of 40 to 200 pH are calculated and plotted in
Fig. 8. Based on the calculated and , the bandwidth of the
TMN for , as plotted in Fig. 9, is simulated in
a CAD software for transformers with in the same range.
When no additional capacitor is added, a TMN with
, , can achieve a bandwidth of 9
GHz. To design a transformer with relatively small and ,
concentric architecture can be a good choice, where the trace Fig. 12. Simulated S-parameters of the TMN matched by a stacked transformer
width and the gap between the outer and the inner winding can .
be adjusted to achieve a wide range of and . However for this
solution, requires a large gap between windings such To make the selected parameters easier to realize, a 10 fF
that the inductance of the inner winding is much smaller than capacitor is added on the source side .
the inductance of the outer winding With the 10 fF capacitor, the corresponding and for
. Such a large gap reduces coupling between windings each is re-calculated, and the 9 GHz bandwidth for
and makes the realizable much smaller than 0.37. can be satisfied by a new solution with
YE et al.: A 65 NM CMOS POWER AMPLIFIER WITH PEAK PAE ABOVE 18.9% FROM 57 TO 66 GHz 2539

Fig. 13. Schematic of the 60 GHz PA.

, , . According to the metal

layers available in the technology (Fig. 10(a)), a concentric
transformer with , , ,
, , ,
is designed. Fig. 10(b) shows the 3D structure of the de-
signed transformer, which has , ,
and . The top two thick metal layers
available in the technology are used together to construct the
transformer in order to reduce its parasitic resistance, and the
dimension of the transformer is adjusted for its , and
Fig. 14. Connections and transistor sizes of active stages.
to approach the selected values as much as possible. The
differences between the parasitics of the transformer and the
parasitics used for calculation are acceptable, therefore no IV. A 60 GHz PA WITH SYNTHESIZED TMNs
iteration is needed. Using the TMN synthesizing method proposed in Section III,
Fig. 11 shows the simulated S-parameters of the synthesized a 60 GHz PA is designed in a 65 nm bulk CMOS process.
TMN, where the solid lines represent the simulation results of In order to achieve good power performance from 57 to 66
the EM-simulated transformer and the dashed lines represent GHz, matching networks of the PA are designed with
the simulation results of the TMN model with parameter values for inter-stage matching and for output
extracted from the designed transformer. It can be seen that the matching in the 9 GHz bandwidth.
TMN model agrees well with EM simulation, and the synthe- Fig. 13 shows the schematic of the PA. The PA utilizes 3
sized TMN has achieved from 56.8 to 66.1 GHz stages to achieve a gain around 20 dB, and each stage is designed
(9.3 GHz bandwidth), as indicated by the shaded area in Fig. 11. with transistors and connections as shown in Fig. 14. Transistors
By using the proposed TMN synthesizing method, the structure and are connected in common source for signal ampli-
and size of transformer, and the value of the added capacitor, fying, while transistors and are used to neutralize
are determined systematically according to the required band- of and so that the PA is unconditionally stable
width of the TMN. A tremendous amount of EM-simulations [6]. Due to the fact that for transistors and
are avoided because the calculated , and give enough , the optimal size of and is around half the
information for the structure and size of the transformer. The size of and for the neutralization. According to simu-
required bandwidth of 57 to 66 GHz in which lation, the size of and for each stage is selected
is achieved successfully despite a large of 6.22 as shown in Fig. 14, corresponding to the minimum of
. each stage. Compared to neutralization using metal capacitors,
As a comparison, Fig. 12 shows the simulated S-parameters the capacitance of and can track of and
of a solution with for the same source and load. Without under PVT variation, which enhances the stability and re-
the proposed TMN synthesizing method, this solution is highly duces gain variation of the PA under PVT variation [7]. Gate
possible to be adopted because can be realized by trans- bias is applied to and through resistors , and the
formers in stacked structure, which is a structure widely used secondary winding of transformers used in matching circuit.
by transformers in mm-wave PAs [4], [8], [9], [13]. It can be Compared with bias schemes where bias voltages are applied
seen that the transformer ( , , ) through transformer center-taps, the stability of the PA is im-
matches the given source and load well at 61.2 GHz, but the proved in common mode by keeping the center-taps of trans-
bandwidth for is only 5.5 GHz, as indicated by formers floating in inter-stage matching networks [13]. With a
the shaded area in Fig. 12 and shown by the gray point in Fig. 9. supply voltage of 1.2 V, the transistors for amplifying are biased
If this solution is selected for the inter-stage matching network, in Class-A with a current density of 0.35 for optimum
the 60 GHz PA will show clearly larger degradation of power to maximize the linear output power.
performance in the 9 GHz bandwidth compared to the PA with After the active stages are designed, the input and output im-
the synthesized inter-stage matching network. pedances of each stage are simulated and modeled as R and C
2540 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 10, OCTOBER 2015

Fig. 16. Photomicrograph of the 60 GHz PA.

Fig. 15. of synthesized TMNs in the 60 GHz PA.

in parallel. Following the TMN synthesizing flow chart shown

in Fig. 7, the parameters , and of each matching net-
work are calculated using the derived matching equations and
selected according to the required bandwidth. Based on the thick
metal layers available in the CMOS technology, transformers
are built with parameter values and 3D structures shown in Fig.
13. Either an additional capacitor is added or a series connec- Fig. 17. S-parameters and stability factor of the PA.
tion of transformer and inductor is used when the selected ,
and are difficult to realize.
For the output matching network, due to the low Q of source (15)
and load ( , ), a bandwidth of 9 GHz
with or even lower can be satisfied with a
wide range of . In such a scenario, transformers in stacked (16)
structure are preferred due to the advantage of low insertion loss
[8]. According to the synthesized parameter values, a capacitor In this matching network, the inductor , and the
of 34 fF is added on the load side of the TMN, and a transformer modeled parameters of the transformer and inductor together are
in stacked structure is constructed using the top two metal layers , , .
which have a distance of 1.45 in between. From 57 to 66 The designed PA is simulated with a peak gain of 21.7 dB
GHz, the designed transformer matches the given source and and a 3 dB bandwidth of 10.6 GHz from 56.1 to 66.7 GHz.
load with as shown in Fig. 15, and the insertion From 57 to 66 GHz, the simulated is 14.2 to 14.5 dBm
loss of the matching network is 0.82 to 0.89 dB. and peak PAE is 20.5% to 23.6%, achieving the design target of
For the two inter-stage matching networks, due to the high good power performance in the 9 GHz bandwidth. The proposed
of the load ( , for inter-stage matching be- TMN synthesizing method enables the matching networks of
tween stage 1 and stage 2, , for inter-stage the PA to be designed systematically, and is shown to be of great
matching between stage 2 and stage 3), the value of must importance for the inter-stage matching networks to achieve
be carefully selected such that can be satisfied mismatch in the required bandwidth.
in the 9 GHz bandwidth. The design of the inter-stage matching V. MEASUREMENT RESULTS
network between stage 2 and stage 3 is explained in Section II
The PA is fabricated in a 65 nm bulk CMOS process, with a
as the TMN synthesizing example. For the inter-stage matching
core area of 0.088 and a total area of 0.22 including
network between stage 1 and stage 2, a concentric transformer
pads. Fig. 16 shows its photomicrograph. Measurements are
is used as well, and the large value of is realized by de-
performed for the PA using on-wafer probing.
signing the primary winding with two turns.
The S-parameters of the PA are measured from 10 MHz to 67
The input matching network is synthesized using the same
GHz using an Agilent N5247A vector signal analyzer. Fig. 17
method but with frequency shifted such that the 3 dB bandwidth
shows the simulated and measured S-parameters. With a supply
of the PA covers the frequency range of 57 to 66 GHz with some
voltage of 1.2 V and DC current of 105 mA, the PA achieves a
safety margin. Due to the small value of but relatively large
maximum of 20.9 dB at 61.7 GHz, and has a 3 dB bandwidth
value of and required, the transformer for this matching net-
of 9.7 GHz extending from 57.2 to 66.9 GHz. In the frequency
work is realized by a strongly coupled stacked transformer and
range of 57 to 66 GHz, the measured is below 13.5 dB
an inductor connected in series. Constructed using two metal
and is below 8.2 dB. Good agreement is achieved between
layers with a distance of only 0.6 in between, the trans-
the measured and simulated S-parameters. In the measured fre-
former has parameter values of , ,
quency range of 10 MHz to 67 GHz, the PA is unconditionally
. When connected in series with an inductor on the
stable with stability factor larger than 12.6. The measured
secondary side, the transformer and the inductor is equivalent
from 50 to 67 GHz is shown in Fig. 17.
to a new transformer with , , and given by
The large signal behavior of the PA is characterized from
57 to 66 GHz in steps of 1 GHz. R&S NRP-Z57 power meter
(14) which has a measurement uncertainty less than 0.248 dB below
YE et al.: A 65 NM CMOS POWER AMPLIFIER WITH PEAK PAE ABOVE 18.9% FROM 57 TO 66 GHz 2541

TABLE I
PERFORMANCE COMPARISON OF THE DESIGNED PA AND OTHER PRIOR ART CMOS PAs WITH TMNs AT 60 GHz

Data of [4], [5], [11], [15] is for bandwidth of 57 to 65 GHz; data of [6] is for bandwidth of 58 to 65 GHz; data of [12] is for bandwidth of
59 to 67 GHz
PAE from 57 to 66 GHz of [13] is obtained from [27] in its Class-A mode
Estimated from graphic
-Data not provided
Area including pads

Fig. 18. Measured and from 57 to 66 GHz, and measured of Fig. 19. Measured gain, output power, and efficiency of the PA at 61 GHz.
a 16QAM modulated signal with EVM of 8.91% in the 4 channels of 802.11ad.

67 GHz is used to calibrate the input power and measure the

output power of the PA. As shown in Fig. 18 and Fig. 1(b),
from 57 to 66 GHz the PA is measured with of 10.81
to 11.68 dBm, of 13.94 to 14.35 dBm, and peak PAE of
18.9% to 21.1%. Benefiting from the proposed TMN synthe-
sizing method, the degradation of output power is only 0.87 dB
for and 0.41 dB for , and the minimum peak PAE is
as high as 89.6% of the maximum peak PAE. Fig. 19 shows the
measured gain, output power, and PAE of the PA at 61 GHz. By Fig. 20. Equipment setup for EVM measurement.
using the proposed TMN synthesizing method for inter-stage
matching networks to increase the driving power, the is
only 2.67 dB lower than and the PAE at is 12.2%.
To measure the PA's output power and efficiency when de-
livering modulated signal, a 16QAM modulated signal with a
symbol rate of 1.76 GS/s is applied to the PA using equipment
setup shown in Fig. 20. By tuning the variable attenuator con-
nected at the PA's input, the input power of the PA can be varied
and the EVM corresponding to different output power of the
PA is measured at the 4 channels of 802.11ad. Fig. 21 shows
the measured EVM at different power back-offs from at
channel 2 (60.48 GHz). At a 3.3 dB back-off, the PA is able to
deliver an output power of 11.1 dBm with PAE of 10.7% while Fig. 21. Measured EVM for 16QAM modulated signal at different power back-
achieving an EVM of 8.91% ( 21 dB), which is the EVM re- offs from at 60.48 GHz.
quired for 802.11ad to support the data-rate of 4.62 Gbps. For
all the 4 channels, the EVM of 8.91% is supported by the PA The performance of the PA is summarized in Table I and
with output power of 10.8 to 11.1 dBm (Fig. 18) and PAE of compared to other prior-art CMOS PAs with TMNs at 60 GHz.
10.1% to 10.7%, further demonstrating the good power perfor- It is observed that the degradation of power performance in the
mance of the PA in the entire operating bandwidth. operating bandwidth of reported 60 GHz PAs is highly related
2542 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 62, NO. 10, OCTOBER 2015
to the CMOS technologies they used. For example, the ratio
of the minimum peak PAE over the maximum peak PAE in
the 9 GHz bandwidth is improved from around 40% for 60
GHz PAs in 90 nm CMOS [4], [5], to around 65% for 60 GHz
PAs in 65 nm CMOS [6], [11], and to around 70% for 60 GHz
PAs in 40/28 nm CMOS [12]–[15]. As explained in Section II,
the increased gain of transistors in more advanced CMOS
technologies has largely contributed to this improvement at
mm-wave. However, by using the proposed TMN synthesizing
method to design both inter-stage matching networks and
output matching network with small mismatch in the 9 GHz
bandwidth, the 60 GHz PA designed in a 65 nm bulk CMOS
technology has achieved the smallest degradation of , with
, and peak PAE even compared to other works in more
advanced technologies.
VI. CONCLUSION
Based on the modeling and the analysis of matching mech-
anism of TMN, this work derives the matching equations of
TMN and proposes a TMN synthesizing method. The method
enables the design of both inter-stage matching networks and
output matching network of mm-wave PAs to provide for
transistors with small mismatch in a large bandwidth. A 60 GHz
PA with synthesized TMNs is designed in a 65 nm bulk CMOS
technology. From 57 to 66 GHz, the PA is measured with small
degradations of 0.87 dB for and 0.41 dB for , and
the minimum peak PAE is as high as 89.6% of the maximum
peak PAE, demonstrating the capability of the TMN synthe-
sizing method to help wideband mm-wave PAs overcome the
challenge brought by the low gain of transistors at such high
frequency.
ACKNOWLEDGMENT
The authors would like to thank Mr. Lim Wei Meng for his
help on measurements.
REFERENCES
[1] N. Saito, T. Tsukizawa, and N. Shirakata et al., “A fully integrated
60-GHz CMOS transceiver chipset based on WiGig/IEEE 802.11ad
with built-in self calibration for mobile usage,” IEEE J. Solid-State
Circuits, vol. 48, no. 12, pp. 3146–3159, Dec. 2013.
[2] K. Okada, R. Minami, and Y. Tsukui et al., “A 64-QAM 60 GHz
CMOS transceiver with 4-channel bonding,” in IEEE ISSCC Dig. Tech.
Papers, Feb. 2014, pp. 346–347.
[3] V. Vidojkovic, G. Mangraviti, and K. Khalaf et al., “A low-power
57-to-66 GHz transceiver in 40 nm LP CMOS with 17 dB EVM at 7
Gb/s,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2012, pp. 268–270.
[4] D. Chowdhury, P. Reynaert, and A. M. Niknejad, “Design considera-
tions for 60 GHz transformer-coupled CMOS power amplifiers,” IEEE
J. Solid-State Circuits, vol. 44, no. 10, pp. 2733–2744, Oct. 2009.
[5] T. LaRocca, J. Y. C. Liu, and M. C. F. Chang, “60 GHz CMOS am-
plifiers using transformer-coupling and artificial dielectric differential
transmission lines for compact design,” IEEE J. Solid-State Circuits,
vol. 44, no. 5, pp. 1425–1435, May 2009.
[6] W. L. Chan and J. R. Long, “A 58–65 GHz neutralized CMOS power
amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State
Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2009.
[7] E. Cohen, O. Degani, and S. Ravid et al., “Robust 60 GHz 90 nm and
40 nm CMOS wideband neutralized amplifiers with 23 dB gain 4. 6 dB
NF and 24% PAE,” in Proc. IEEE Silicon Monolithic Integr. Circuits
RF Syst. Top. Meet., Jan. 2012, pp. 207–210.
[8] J. Chen and A. M. Niknejad, “A compact 1 V 18. 6 dBm 60 GHz power
amplifier in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2011, pp. 432–433.
[9] S. Aloui, B. Leite, and N. Demirel et al., “High-gain and linear 60-GHz
power amplifier with a thin digital 65-nm CMOS technology,” IEEE
Trans. Microw. Theory Tech., vol. 61, no. 6, pp. 2425–2437, Jun. 2013.
[10] J.-F. Yeh, J.-H. Tsai, and T.-W. Huang, “A 60-GHz power amplifier
design using dual-radial symmetric architecture in 90-nm low-power
CMOS,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 3, pp.
1280–1290, Mar. 2013.
[11] A. Larie, E. Kerherve, and B. Martineau et al., “A 1. 2 V 20 dBm 60
GHz power amplifier with 32. 4 dB gain and 20% Peak PAE in 65
nm CMOS,” in Proc. Eur. Solid State Circuit Conf., Sep. 2014, pp.
175–178.
[12] S. Kulkarni and P. Reynaert, “A push-pull mm-wave power amplifier
AM-PM distortion in 40 nm CMOS,” in IEEE ISSCC Dig.
Tech. Papers, Feb. 2014, pp. 252–253.
[13] D. Zhao and P. Reynaert, “A 60- GHz dual-mode class ab power am-
plifier in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 10,
pp. 2323–2337, Oct. 2013.
[14] S. V. Thyagarajan, A. M. Niknejad, and C. D. Hull, “A 60 GHz drain-
source neutralized wideband linear power amplifier in 28 nm CMOS,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 8, pp. 2253–2262,
Aug. 2014.
[15] A. Larie, E. Kerherve, and B. Martineau et al., “A 60 GHz 28 nm UTBB
FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18. 2
dBm P1 dB and 74 mW PDC,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2015, pp. 1–3.
[16] O. Juntaek, K. Bonhyun, and H. Songcheol, “A 77- GHz CMOS power
amplifier with a parallel power combiner based on transmission-line
transformer,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 7, pp.
2662–2669, Jul. 2013.
[17] Q. J. Gu, Z. Xu, and M. C. F. Chang, “Two-way current-combining
W-band power amplifier in 65-nm CMOS,” IEEE Trans. Microw.
Theory Tech., vol. 60, no. 5, pp. 1365–1374, May 2012.
[18] T. Johansson and J. Fritzin, “A review of watt-level CMOS RF power
amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 62, no. 1, pp.
111–124, Jan. 2014.
[19] I. Aoki, S. Kee, and R. Magoon et al., “A fully-integrated quad-band
GSM/GPRS CMOS power amplifier,” IEEE J. Solid-State Circuits,
vol. 43, no. 12, pp. 2747–2758, Dec. 2008.
[20] S. C. Cripps, RF Power Amplifiers for Wireless Communications, 2nd
ed. Norwood, MA, USA: Artech House, 2006.
[21] F. H. Raab, P. Asbeck, and S. Cripps et al., “Power amplifiers and trans-
mitters for RF and microwave,” IEEE Trans. Microw. Theory Tech.,
vol. 50, no. 3, pp. 814–826, Mar. 2002.
[22] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE
J. Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
[23] Y. Cao, R. A. Groves, and X. Huang et al., “Frequency-independent
equivalent-circuit model for on-chip spiral inductors,” IEEE J. Solid-
State Circuits, vol. 38, no. 3, pp. 419–426, Mar. 2003.
[24] D. Kehrer, W. Simburger, and H. D. Wohlmuth et al., “Modeling of
monolithic lumped planar transformers up to 20 GHz,” in Proc. IEEE
Custom Integr. Circuit Conf., May 2001, pp. 401–404.
[25] L. F. Tiemeijer, R. M. T. Pijper, and C. Andrei et al., “Analysis, design,
modeling, characterization of low-loss scalable on-chip transformers,”
IEEE Trans. Microw. Theory Tech., vol. 61, no. 7, pp. 2545–2557, Jul.
2013.
[26] B. Razavi, RF Microelectronics, 2nd ed. Upper Saddle River, NJ,
USA: Pearson Educ. Int., 2012.
[27] D. Zhao, S. Kulkarni, and P. Reynaert, “A 60 GHz dual-mode power
amplifier with 17. 4 dBm output power and 29. 3% PAE in 40-nm
CMOS,” in Proc. ESSCIRC, Sep. 2012, pp. 337–340.
Wanxin Ye received the B.Eng. degree from Univer-
sity of Electronic Science and Technology of China
in 2009. From 2009 to 2011, he was with TP-LINK
Tech. Co., Ltd., as an RF Engineer. He is currently
working towards the Ph.D. degree at Nanyang Tech-
nological University, Singapore.
His research interest is RF/mm-wave IC design,
with focus on power amplifiers.
YE et al.: A 65 NM CMOS POWER AMPLIFIER WITH PEAK PAE ABOVE 18.9% FROM 57 TO 66 GHz
Kaixue Ma (M’05–SM’09) received the B.E. and
M.E. degrees from Northwestern Polytechnical
Univ. (NWPU), China, and the Ph.D. degree from
Nanyang Technological Univ. (NTU), Singapore.
From August 1997 to December 2002, he was
with China Academy of Space Technology (Xi’an),
where he became Group Leader of millimeter-wave
group for space-borne microwave & mm-wave
components and subsystem for satellite payload
and VSAT ground station. From September 2005 to
September 2007, he was with MEDs Technologies
as an R&D Manager. From September 2007 to March 2010, he was with ST
Electronics (Satcom & Sensor Systems) as R&D Manager, Project Leader and
Technique Management Committee of ST Electronics. Since March 2010, he
is with NTU as a Senior Research Fellow and Millimeter-wave RFIC team
leader for 60 GHz Flagship Chipset project. As a PI/Technique Leader, He did
projects with fund more than S$12 million (excluding projects done in China).
His research interests include satellite communication, software defined radio,
microwave/MM-wave circuits and system using CMOS, MEMS, MMIC, and
LTCC. He has eight patents, two patents in pending, and authored/coauthored
over 80 referable international journal and conference papers in the related
area. He received best paper awards from IEEE SOCC2011, IEEK SOC
Design Group Award, excellent paper award from International Conference
on HSCD2010, chip design competition bronze award of ISIC2011. He is a
reviewer for several international journals.
2543
Kiat Seng Yeo received the B.Eng. (EE) and
Ph.D. (EE) degrees from Nanyang Technological
University (NTU), Singapore, in 1993 and 1996,
respectively. Associate Provost (Graduate Studies
and International Relations) at Singapore University
of Technology and Design (SUTD) and Member of
Board of Advisors of the Singapore Semiconductor
Industry Association, Prof. Yeo is a widely known
authority in low-power RF/mm-wave IC design and
a recognized expert in CMOS technology. Before
his appointment at SUTD, he was Associate Chair
(Research), Head of Division of Circuits and Systems and Founding Director
of VIRTUS of the School of Electrical and Electronic Engineering at NTU. He
has published 6 books, 5 book chapters, over 500 international top-tier refereed
journal and conference papers, and holds 35 patents. Dr. Yeo holds/held
key positions in many international conferences as Advisor, General Chair,
Co-General Chair and Technical Chair. He was awarded the Public Adminis-
tration Medal (Bronze) on National Day 2009 by the President of the Republic
of Singapore and was also awarded the distinguished Nanyang Alumni Award
in 2009 for his outstanding contributions to the university and society.
Qiong Zou received the B.Eng. degree in electronic
science and technology from Huazhong University
of Science and Technology (HUST), China, in 2008.
She is currently working toward the Ph.D. degree
in electrical and electronic engineering at Nanyang
Technological University, Singapore.
Her research interests include the RF and mil-
limeter-wave front-end IC design.