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Beyond Scaling - Realizing Value Through The Integration of Memory and Autonomic Chip Features
Beyond Scaling - Realizing Value Through The Integration of Memory and Autonomic Chip Features
Chip Features
Subramanian S. Jyer
IBM Corporation, Systems & Technology Group,
2070 Route 52, Hopewell Junction, NY 12533. USA.
email: ssiyer(us.ibm.com
Autonomic Chips
Another important development is the building of
autonomic capabilities into the chip. Most advanced
SOCs employ Built-in Self Test (BIST). BIST engines
are dedicated engines of increasing versatility that can
apply a wide range of test vectors to functionality test a
wide variety of IP blocks including memory, logic and
analog functions. In the case of memory, BIST can be
combined with Redundancy Allocation Logic (RAL) to fix
the defects using redundant elements. Advances in the
development of electrical fuses (eFUSE) that can be
programmed on chip allow us to combine BIST, RAL
and eFUSE to form a Built-in Self Repair (BISR) system.
Additional sophistication is possible through the use of
Fuse string compression, hierarchical repair where
repair solutions are augmented at wafer level, module
level, and even multiple instances of field repair.
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