ARCHITECTURE OF COMPUTERS

Vistula University
Lab 1
 Data representation in computer systems

• we reminded ourselves that the datapath and control are the

two components that come together to be collectively known
as the processor.
• Datapath consists of the functional units of the processor.
• Elements that hold data.
• Program counter, register file, instruction memory, etc.
• Elements that operate on data.
• ALU, adders, etc.
• Buses for transferring data between elements.

•Control commands the datapath regarding when and how to route

and operate on data.
To start, we will look at the datapath elements needed by every
instruction.
First, we have instruction memory.
Instruction memory is a state element
that provides read-access to the
instructions of a program and, given
an address as input,
supplies the corresponding instruction
at that address.
DATAPATH

Next, we have the program counter or PC.

The PC is a state element that holds
the address of the current instruction.
Essentially, it is just a 32-bit register
which holds the instruction address
and is updated at the end of every
clock cycle.
Normally PC increments sequentially except for
branch instructions

The arrows on either side indicate

that the PC state element is both
readable and writeable.
 DATAPATH

Lastly, we have the adder.

The adder is responsible for

incrementing the PC to hold the
address of the next instruction.
It takes two input values, adds them
together and outputs the result.
 DATAPATH

So now we have instruction memory, PC, and adder datapath elements. Now, we can
talk about the general steps taken to execute a program.

• Instruction fetching: use the address in the PC to fetch the current instruction from
instruction memory.

• Instruction decoding: determine the fields within the instruction

• Instruction execution: perform the operation indicated by the instruction.
• Update the PC to hold the address of the next instruction.
 DATAPATH

• Fetch the instruction at

the address in PC.

• Decode the instruction.

• Execute the instruction.
• Update the PC to hold the
address of the next
instruction.
 To support R-format instructions, we’ll need to add a state element
called a register file. A register file is a collection readable/writeable
registers.
•Read register 1 – first source
register. 5 bits wide.
•Read register 2 – second
source register. 5 bits wide.
•Write register – destination
register. 5 bits wide.
•Write data – data to be written
to a register. 32 bits wide.
At the bottom, we have the RegWrite
input. A writing operation only occurs when
this bit is set.

The two output ports are:

• Read data 1 – contents of source register

1.
• Read data 2 – contents of source register
2.
To actually execute R-format instructions, we need to
include the ALU element.
The ALU performs the operation indicated by the
instruction. It takes two operands, as well as a 4-bit
wide operation selector value. The result of the
operation is the output value.
ALU operation is a part of the control.

We have an additional output specifically for

branching – we will cover this in a minute.
Here is our datapath for R-format
instructions.
1. Grab instruction address from PC.
Here is our datapath for R-format
instructions.
2. Fetch instruction from instruction
memory.
3. Decode instruction.
 DATAPATH
Here is our datapath for R-format
instructions.
4. Pass rs, rt, and rd into read register and
write register arguments.
Here is our datapath
for R-format
instructions.
5. Retrieve data from
read register 1 and
read register 2 (rs
and rt).
 DATAPATH

Here is our datapath

for R-format
instructions.
6. Pass contents of rs
and rt into the ALU
as operands of the
operation to be
performed.
 DATAPATH

Here is our datapath

for R-format
instructions.
7. Retrieve result of
operation performed by
ALU and pass back as
the write data argument
of the register file (with
the RegWrite bit set).
 DATAPATH

Here is our datapath

for R-format
instructions.
8. Add 4 bytes to the
PC value to obtain
the word-aligned
address of the next
instruction.
DATAPATH

The data memory element implements the functionality for reading and
writing data to/from memory.
There are two inputs. One for the address of
the memory location to access, the other
for the data to be written to memory if
applicable.
The output is the data read from the
memory location accessed, if
applicable.
Reads and writes are signaled by MemRead
and MemWrite, respectively, which must be
asserted for the corresponding action to take
place.
 Logic Gates - Building an ALU

We are going to use four

logic gates: AND, OR,
NOT and XOR. You
should Below are the
icons for each, and their
truth table.
Registers usage conventions

Registers usage conventions in computer architecture, especially in RISC (Reduced Instruction Set
Computer) architectures like MIPS, are standardized guidelines for how registers should be used
in a program. These conventions ensure consistency and compatibility between different parts of
a program (e.g., functions or procedures) and between different software components (e.g.,
libraries or system calls). Common conventions for MIPS architecture include
Registers usage conventions
1. Registers are like Temporary Storage: Think of registers as small, fast, and temporary
storage spaces inside a computer's processor.

2. Naming Registers: Registers have names like $t0, $s0, etc. Each has a purpose:

– $t0-$t9 are for temporary data.

– $s0-$s7 are for saving important data (must be preserved during function calls).

– $a0-$a3 are for passing function arguments.

– $v0-$v1 are for returning results from functions.

– $0 is always zero.

3. Temporary Registers: Use $t0-$t9 for calculations inside a function. They can change freely,
but you should save their original values if needed.
4. Saved Registers: Use $s0-$s7 to hold important data that must be preserved across function
calls. Save and restore their values if you modify them in a function.

5. Argument Registers: $a0-$a3 are for passing arguments to functions. They can change
during a function call, so save them if necessary.
Registers usage conventions

• Result Registers: $v0-$v1 are used to return results from functions. Typically, use $v0 for
returning values.

• Stack Pointer: $sp points to a stack in memory, useful for managing function call information
and local variables.
• Frame Pointer: $fp helps access local variables and function parameters within a function's
stack frame.

• Zero Register: $0 always contains the value 0 and cannot be changed.

 RISC architecture features

RISC (Reduced Instruction Set Computer)

architecture is a computer design
philosophy that emphasizes simplicity and
efficiency in instruction execution. RISC
processors have several key features that
distinguish them from CISC (Complex
Instruction Set Computer) architectures.
Here are some of the prominent features of
RISC architecture
 RISC architecture features

• Simple Instruction Set: RISC processors have a small and straightforward set of instructions.
These instructions typically perform basic operations like load, store, arithmetic, and logic
operations. Complex operations are broken down into multiple simple instructions.

• Fixed-Length Instructions: Instructions in RISC architectures are typically of fixed length. This
simplifies the instruction fetch and decode stages of the pipeline, making them more predictable
and efficient.

• Load/Store Architecture: RISC architectures often follow a load/store model. This means that
data must be loaded from memory into registers before it can be operated on, and the results
must be stored back into memory if necessary. Only load and store instructions access memory
directly.

• Register-Centric: RISC architectures heavily rely on registers for data manipulation. They have a
large number of registers available (e.g., MIPS has 32 registers), and most operations involve
data transfers between these registers.
 RISC architecture features

• Single-Cycle Execution: RISC instructions are typically designed to execute in a single clock cycle.
This makes the processor's behavior more predictable and simplifies pipeline design.

• Hardwired Control Unit: RISC processors often use a hardwired control unit, which means that
the control signals for executing instructions are directly generated by the processor's hardware
logic. This contributes to faster instruction execution.

• Pipelining: RISC architectures are well-suited for pipelining, a technique that divides the
instruction execution process into stages. Each stage can work on a different instruction at the
same time, increasing throughput.

• Reduced Addressing Modes: RISC architectures typically have a limited number of addressing
modes, simplifying instruction decoding and execution. Common addressing modes include
immediate (constants), register direct, and indexed addressing.

• Efficient Compiler Support: RISC architectures work well with optimizing compilers. The
simplicity and regularity of the instruction set make it easier for compilers to generate efficient
machine code.
 RISC architecture features

• Favor Performance over Code Size: RISC architectures prioritize instruction execution speed
over the size of the code. This is based on the assumption that memory is becoming cheaper and
larger, making code size less critical.

• No Microcoding: RISC processors usually do not employ microcode, which is used in CISC
processors for complex instruction decoding. This simplifies the processor design but may
require more complex compiler support.

• Fewer Instruction Formats: RISC architectures often have a limited number of instruction
formats, which simplifies decoding and execution. MIPS, for example, has just three instruction
formats.
 MIPS Assembler and Runtime Simulator

https://circuitverse.org/users/199531/projects/circuits-by-dr-tariq
End of Lecture