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 FALL 2017
VOL. 9 • NO. 4
www.ieee.org/sscs-news

features
18 Fully Depleted Silicon
on Insulator Devices CMOS
By Andreia Cathelin

27 Digital Circuits for Mobile Computing

By Alice Wang and Hugh Mair

34 Low-Power Wireless Systems about this image:

for Hospital Patient Monitoring Security is important in IC design, to prevent instances such as this gray
box attacker model. Find out more in the article “Security Adds an Extra
By Alison Burdett Dimension to IC Design.”

41 Security Adds an Extra Dimension

to IC Design
By Ingrid Verbauwhede

46 Designing Hardware for Machine Learning columns/departments

By Vivienne Sze 3 contributors
4 EDITOR’S NOTE
55 Embedded Deep Neural Network Processing 5 President’s Corner
By Marian Verhelst and Bert Moons
7 ASSOCIATE EDITOR’S VIEW
8 china connection
66 Innovation, Startups, and Funding 10 circuit intuitions
in the Age of Accelerations
By Terri S. Fiez, Mar Hershenson, Lucy Sanders,
13 A Circuit for All Seasons
and Catherine Ashcraft 17 guest editorial
98 Chapters
73 Nanoscale MOSFET Modeling 125 People
By Christian Enz, Francesco Chicco, 133 SOCIETY news
and Alessandro ­Pezzotta 136 conference reports
145 IEEE NEWS
82 Neutralization Techniques 148 CONFERENCE CALENDAR
for High-Frequency Amplifiers
By Payam Heydari

90 Challenges of Physiological Signal

Measurements Using Electrodes
By Long Yan and Joonsung Bae

Digital Object Identifier 10.1109/MSSC.2017.2738741

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 1

 Administrator, Abira Sengupta Terms to 31 Dec. 2018
IEEE SSCS, 445 Hoes Lane Mike Beunder, Hideto Hidaka, Bezhad Razavi,
IEEE solid-state Piscataway, NJ 08854 USA Ali Sheikholeslami, Zhihua Wang
circuits magazine Tel: +1 732 562 2676 Terms to 31 Dec. 2019
Editor-in-Chief Administrator, Lauren Caruso Jan Craninckx, Terri Fiez, Tadahiro
R. Jacob (Jake) Baker IEEE SSCS, 445 Hoes Lane Kuroda, Ingrid Verbauwhede, Alice Wang
rjacobbaker@gmail.com Piscataway, NJ 08854 USA Region 7 Representative
Tel: +1 732 562 3871 Ali Sheikholeslami
Tutorials Editor
Willy Sansen SSC Administrative committee Region 8 Representative
willy.sansen@esat.kuleuven.be President, Jan Van der Spiegel Bram Nauta
University of Pennsylvania
TECHNOLOGY EDITOR Region 10 Representative
Vice-President, Bram Nauta
Open University of Twente Hideto Hidaka
Secretary, Mike Beunder Chairs of Standing Committees
Associate Editor for the far east Awards—John J. Corcoran
Zhihua Wang TD Shepherd & Co.
Chapters—Stefan Rusu
zhihua@tsinghua.edu.cn Treasurer, Wanda Gass Education—Ali Sheikholeslami
Design, Connect, Create Meetings—Bill Bowhill
ASSOCIATE EDITOR FOR
EUROPE AND AFRICA Past President, Bill Bidermann Membership—Patrick Yue
Marcel Pelgrom BK Associates Nominations—Bill Bidermann
pelgromconsult@kpnmail.nl Other Representatives Publications—John Long
Representative to Sensors Council
ASSOCIATE EDITOR Darrin Young
Ali Sheikholeslami
ali@eecg.utoronto.ca Representative to CAS from SSCS IEEE Periodicals/
Shanthi Pavan
Magazines Department
CONTRIBUTING EDITORs Representative to SSCS from CAS
Behzad Razavi Andrei Vladimirescu Senior Managing Editor
razavi@ee.ucla.edu Geraldine Krolin-Taylor
Representatives to EDA Council
Tom Lee Bryan Ackland, Vivek Tiwari senior Art Director
tomlee@ee.stanford.edu Janet Dudar
Representatives to ISSCC
Anantha Chandrakasan ASSOCIATE Art Director
News Editor Gail A. Schnitzer
Abira Sengupta Representative to CICC
abira.sengupta@ieee.org Ramesh Hijani production coordinator
Representative to IEEE YP Program Theresa L. Smith
MAGAZINE ADVISORY COMMITTEE
Chair: Rakesh Kumar. Jake Baker, Emre Ayranci Staff Director, Publishing Operations
Bill Bidermann, Glenn Gulak, Representatives to Nanotechnology Council Fran Zappulla
Erik Heijne, ­Hideto Hidaka, Ian Young Editorial Director
Richard Jaeger, Michael Kelly, Representative to Technical Committee on RFID Dawn M. Melley
Tom Lee, Marcel Pelgrom, Jeffrey Walling Production Director
Willy Sansen, Abira Sengupta,
Representative to Engineering Technology Peter M. Tuohy
Ali Sheikholeslami, Lewis Terman,
Management Society Advertising Production Manager
Alice Wang, Patrick Yue
Mike Beunder Felicia Spagnoli
Representative to Biometrics Council Director, Business
Bruce Hecht Development—Media & Advertising
Representative to Internet of Things (IoT) Mark David
IEEE solid-state Andreia Cathelin +1 732 465 6473, FAX: +1 732 981 1855
circuits society Representative to IEEE 5G m.david@ieee.org
Aarno Pärssinen www.ieee.org/ieeemedia
Executive Director, Michael Kelly
IEEE SSCS, 445 Hoes Lane Elected AdCom Members at Large IEEE prohibits discrimination, harassment,
Piscataway, NJ 08854 USA Terms to 31 Dec. 2017 and bullying. For more information,
Tel: +1 732 981 3400 Andreia Cathelin, Pavan Hanumolu, visit http://www.ieee.org/web/aboutus/
sscs-staff@ieee.org Kofi Makinwa, Roland Thewes, Patrick Yue whatis/policies/p9-26.html.

SCOPE: Each issue of IEEE Solid-State Circuits Magazine is envisioned as a self-contained

resource for fundamental theories and practical advances within the field of integrated cir-

“Why Diversity Matters” ©NCWIT, used with permission.

cuits (ICs). Written at a tutorial level and in a narrative style, the magazine features articles
by leaders from industry, academia and government explaining historical milestones, current
trends and future developments.
contact information: See the “Contact Us” page on SSCS Web site: http://ewh.ieee.
org/soc/sscs/index.php?option=com_content&task=view&id= 10&Itemid=3.
IEEE Solid-State Circuits Magazine (ISSN 1943-0582) (SCMOCC) is published quarterly by The
Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor,
circuit pattern—footage firm, inc.

New York, NY 10016-5997, USA +1 212 419 7900. Responsibility for the contents rests upon
the authors and not upon the IEEE, the Society, or its members. The magazine is a member-
ship benefit of the IEEE Solid-State Circuits Society, and subscriptions are included in Society
fee. Replacement copies for members are available for US$20 (one copy only). Nonmembers
can purchase individual copies for US$183.00. Nonmember subscription prices are available
on request. Copyright and Reprint Permissions: Abstracting is permitted with credit to the
source. Libraries are permitted to photocopy beyond the limits of the U.S. Copyright law for
private use of patrons: 1) those post-1977 articles that carry a code at the bottom of the first
page, provided the per-copy fee indicated in the code is paid through the Copyright Clearance
Center, 222 Rosewood Drive, Danvers, MA 01970, USA; and 2) pre-1978 articles without fee.
For other copying, reprint, or republication permission, write to: Copyrights and Permissions
Department, IEEE Service Center, 445 Hoes Lane, Piscataway NJ 08854 USA Copyright © 2017
by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Periodicals about the cover:
postage paid at New York, NY, and at additional mailing offices. Postmaster: Send address The first seven articles in this issue were
changes to IEEE Solid-State Circuits Magazine, IEEE, 445 Hoes Lane, Piscataway, NJ 08854 USA. written by women in leadership roles in the
Canadian GST #125634188 Printed in USA
IEEE Solid-State Circuits Society, highlighting
Digital Object Identifier 10.1109/MSSC.2017.2767838 the wide-ranging contributions of the Society.

Promoting Sustainable Forestry

SFI-01681

2 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE


Andreia Cathelin
h a s b e en w it h S T-
Microelectronics,
Crolles, France, since
1998, where she is
now a fellow in Tech-
nology R&D.
Alice Wang is an
assista nt genera l
ma­­nager in high-per-
formance processor
technolog y at Me-
diaTek and chair of
the IEEE Solid-State Circuits Society
Women in Circuits Committee.
H u g h M a i r is a n
a ssist a nt g e n e r a l
­m a ­­n a g e r i n h ig h -
performance proces-
sor te c h n olog y at
M e d i aTek
Alison Burdett is
the chief scientific
officer of Sensium and
has over 30 years of
experience in elec-
tronic engineering and
semiconductor design.
INGRID V ER B A U -
W HEDE h e ads t h e
embedded systems
and hardware team
of the research group
COSIC at KU Leuven,
Belgium.
Digital Object Identifier 10.1109/MSSC.2017.2745918
Date of publication: 16 November 2017
contributors
Vivienne Sze is an LUCY SANDERS is
associate ­professor in chief executive offi-
the Electrical Engi­­ne­ cer and cofounder of
e­ring and Computer the National Center
Science Department at for Women and Infor-
the Massachusetts In- mation Technology,
stitute of Technology. Boulder, Colorado.
MArian Verhelst CATHERINE ASHCRAFT
is an assistant profes- is a senior research
sor at the Micro-Elec- scientist w ith t h e
tronics and Sen­­­­s ors National Center for
Laborator­­i es of the Women and Informa-
Electrical ­Engineer­ing tion Technology at the
Department at KU Leuven, Belgium. University of Colorado, Boulder.
Bert Moons is a Christian Enz is
research assistant with the Swiss Fed-
with the Micro-Elec- eral Institute of Tech-
tronics and Sensors nology (EPFL), where
Laboratories of the he is currently a pro-
Electrical Engineer- fessor, director of the
ing Department, KU Leuven, Belgium. Institute of Microengineering, and
head of the IC Lab.
Terri S. Fiez is the Francesco Chicco
vice chancellor for is work ing toward
research and inno- his Ph.D. degree as a
v at ion at t h e Un i- member of the IC Lab
versity of Colorado, at EPFL.
Boulder.
MAr Hershenson Alessandro Pez-
is a cofounder and zotta joined EPFL’s
managing partner IC Lab in 2016 as a sci-
at Pejman Mar Ven- entist, where he works
tures, a seed-stage on semiconductor de-
in­­v estment firm in vice modeling.
Palo Alto, California.
(continued on p. 12)
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 3
 editor’s note
R. Jacob Baker
Welcome to the Fall 2017 Issue of
IEEE Solid-State Circuits Magazine!
T
This issue of IEEE Solid-State Circuits
Magazine offers seven articles from
members of the IEEE Solid-State Cir-
cuits Society (SSCS) Women in Cir-
cuits Committee. Guest Editor Wanda
Gass has assembled an impressive
set of tutorials to highlight contribu-
tions of female leaders in the SSCS.
These articles focus on the design
challenges of the following:
■■ 28-nm fully deplete silicon on insu-
lator by Andreia Cathelin
■■ mobile c ­ omputing by Alice Wang
and Hugh Mair
■ ■ p at ie nt monitoring by A lison
Burdett
■■ security circuits for the Internet
of Things by Ingrid Verbauwhede
■■ machine learning by Vivienne Sze
■■ neural networks by Marian Ver-
helst and Bert Moons.
The last article in this special sec-
tion is an interview in which Terri Fiez
explores the startup landscape for
IC products with venture capitalist
Mar Hershenson and discusses the
business case for the diversity of
startups with Lucy Sanders and Cath-
erine Ashcraft of the National Center
for Women and Information Tech-
nology. The mix of articles in this
issue underscores the wide-ranging
contributions of our members that
make the world a better place by ad­­­
vancing the s ­tate of the art in the
solid-state circuits industry.
Digital Object Identifier 10.1109/MSSC.2017.2745879
Date of publication: 16 November 2017
4 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Additional articles of interest
in this issue include 1) part 2 of the
article on nanoscale MOSFET mod-
eling for the design of low-power
analog and RF circuits by Chris-
tian Enz, Francesco Chicco, Alessan-
dro Pezzotta, 2) Payam Heydari’s
article on neutralization techniques
for high-frequency amplifiers, and
3) an article on the challenges of
physiological signal measurements
using electrodes by Long Yan and
Joonsung Bae.
We also have the regular, and ever-
popular, editorials/tutorials from
Marcel Pelgrom, Ali Sheikholeslami,
and Behzad Razavi in this issue.
Marcel’s article discusses the impor-
tance of wasting time, a forgotten
art he would argue. As always, his
article is a great read. Ali’s column is a
thought-provoking look at sinusoidal
circuits. The article pro­­vides, as the
series of his article name indicates,
circuit intuitions when looking at res-
onant, that is LC, circuits.
Behzad’s series, “A Circuit for All
Seasons,” points the spotlight on the
decision feedback equalizer (DFE).
The article is an i­ntroduction to equal-
ization, and why it’s need ­­­ed, fol-
lowed by why DFE is used. Behzad’s
thought f ul selection of topics in
this series gives a concise introduc-
tion to a great variety of circuits
and their uses while, at the same
time, providing a good summary
of techniques for those look ing
at refreshing their knowledge or,
perhaps, a different way of looking
at things for those already working
in the field.
The goal of the magazine contin-
ues to be to provide Society news
and information as well as a series
of self-contained resources to keep
SSCS members current with changes
in technology while, at the same time,
providing reviews of circuit design
concepts. This includes contributions
from experts describing the current
state of affairs and evolution of a
particular IC technology. We will also
continue to feature articles focused
on the contributions of luminaries.
Of course, suggestions from readers
are always welcome.
This issue marks end of my third
year as editor-in-chief (EIC) of the
magazine. While I have signed-up
for another three years, until the
fall of 2020, I would like to publicly
thank the people I work closely with on
every issue for their contributions,
including Geri Krolin-Taylor (and
her crew!), Abira Sengupta, Behzad
Razavi, Ali Sheikholeslami, Marcel Pel-
grom, and Rakesh Kumar. I greatly
enjoyed reading the magazine when
Mary Lanzerotti and Dick Jaeger were
EIC and chair of the SSC Magazine
Advisory board, respectively, and I
am proud to attempt to continue their
good work today. As always we hope
you enjoy reading IEEE Solid-State Cir-
cuits Magazine.


Reflections
T
The IEEE Solid-State Circuits Soci-
ety (SSCS) has always, and will con-
tinue to have, a profound and positive
impact on me, both in my career
and personal life. So allow me to
begin my final “President’s Corner”
column with a heartfelt and sincere
thank you—to you, my fellow mem-
bers—for allowing me the honor
and pri­­­vilege to have served as our
Society’s president.
Looking back over the last two
years, I am filled with a sense of
deep satisfaction, pride, and ap­­
preciation for the progress and hard
work achieved by our team of volun-
teers on the Administrative Commit­­tee
(AdCom), our g rassroots leader-
ship, and our administrative staff.
We have experienced two banner
years of growth, membership ser-
vice, new product development, and
engagement activity. I would like
to thank our Chapter chairs, volun-
teers, and leaders for their tireless
dedication and hard work.
Several major programming ini-
tiatives and added member benefits
were launched over the past two
years that we can all be proud of and
enjoy for many years to come. Work-
ing in line with the Society’s 2020
strategic plan, your volunteers and
I have spent time on understand-
ing where our priorities should be
and on what the Society needed to
focus. The underlying mission of
the strategic plan was to serve and
Digital Object Identifier 10.1109/MSSC.2017.2746159
Date of publication: 16 November 2017
President’s Corn er
Jan Van der Spiegel
recognize professionals active in the Branch Chapters located worldwide.
field of solid-state circuits. This number continues to grow due
Thanks to the work of SSCS Mem- to the efforts of Stefan, who facilitates
bership Chair Patrick Yue, we enjoyed Chapter chair meetings at regional
a steady incremental growth in our SSCS conferences to share informa-
membership. But more importantly, tion, encourage participation, and cel-
we see a balancing between indus- ebrate our Chapter activities.
try and the academic memberships. Our Women in Circuits (WiC) Pro-
Membership programs created in gram, which started with the founda-
2016 and 2017 included the de- tion of a standing committee in 2016,
velopment of the SSCS mobile app, supports our inclusion and diversity
IEEE Volta, to inter- initiatives from the
est students in elec- 2020 strategic plan to
trical engineering and increase female mem-
Several major
circuit design as a ber recruitment, re-
programming
career path, to ensure tention, and advance­­
initiatives and
a future workforce for ment into leadership
added member
our global profession. roles within the Soci-
benefits were
In addition, a series et y. SSCS welcomed
launched over the
of campaigns was set four new female Ad-
past two years
up to enhance and Com members this
that we can all
in­­­­­c rease our overall past year to our Board.
be proud of and
SSCS membership. For Highlights from 2017
enjoy for many
example, a senior mem- activities include great
years to come.
bership campaign was programs such as the
undertaken to increase June Bay Area WiC net-
and support the eleva- working luncheon,
tion of IEEE Members to Senior Mem- which featured speakers from Apple
ber status. Details on qualifications a n d the University of California,
and how to become a Senior Mem- Berkeley. Networking events were also
ber are outlined on the SSCS website: held at the 2017 International Solid-
http://sscs.ieee.org/membership/ State Circuits Conference (ISSCC), VLSI
become-a-senior-member. Symposium 2017, and 2017 European
I would also like to recognize the Solid-State Circuits Conference. Thanks
achievements and efforts of Stefan to the efforts of Alice Wang, our WiC
Rusu, our SSCS Chapters chair. Under committee chair, and Wanda Gass,
h i s l e a d e r s h ip, t h e r e h a s b e e n our WiC vice committee chair, we have
a steady increase in our Chapters and seen a 25% growth in female members
engagement activities at the grass- since 2016.
roots level. We now have 106 Chap- Our Society launched a new web-
ters, Joint Chapters, and Student site, which debuted at ISSCC 2016
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 5
and brought the first Xplore-ready to assist students with travel to
mobile reader to IEEE by exclusively SSCS-supported conferences to aid
contracting with FirstIron to license in their educational needs. Addition-
BrowZine. BrowZine is a tablet and ally, we have also implemented new
smartphone-based e-reader that pro- programs, including the Society’s
vides members with a convenient massive open online course (MOOC)
and easy way to read articles from series. The MOOCs were produced in
current and past issues of IEEE Jour- concert with our flagship conferences
nal of Solid-State Circuits and IEEE and will help to build career aware-
Solid-State Circuits Magazine. ness in circuit design. VLSIx was
Along with my fellow SSCS lead- launched in 2016 and is now available
ers and the AdCom, our Society has on the SSCS Resource Center. CICCx
worked diligently to build program- will be available later this year.
ming and services to enhance member The SSCS Resource Center provides a
recognition and re­­ centralized location
ward the loyalty of to house all of the
our almost 10,000 Society’s educational
members. In this mag-
Let me be the mater ia l, ­i ncluding
azine, you may have
first to welcome short courses, tutor i-
noticed a new feature
our incoming als, and webinars. These
in the “People” column
president, Prof. resources are avail-
called “In Step with,”
Bram Nauta, and able to SSCS mem­­bers
in which we highlight
pledge my support at no cost.
an SSCS member. This
to his presidency The SSCS webinar
column has focused
as he takes over program has grown
on profiles from Chap-
the reigns on 1 immensely these past
ter chairs and AdCom
January 2018. two years thanks to
members to young the leadership of
professionals and stu­­ Michael Perrott and
dent members; it is a way for the his team of webinar coordinators—
Society to celebrate the individual and Alvin Loke, Filip Tavernier, and
reinforce that all our member seg- Hoi-Jun Yoo. Another exciting proj-
ments are valued. ect was undertaken through a part-
Under the stewardship of Emre nership with Rivers Publishing to
Ayranci, our SSCS Young Profession­ launch a tutorial-style book series in
als (YP) chair, we have built a strong conjunction with our flagship con-
YP program. SSCS YP mentoring ferences. I’d like to thank Ali Sheik-
events held at conferences have holeslami, SSCS Education chair, for
provided the opportunity for our his great efforts and continued ini-
student and young professional tiatives to bring more educational
members to connect with our more resources to our members.
senior members. T he mentor- On the publications front, we are
ing event at ISSCC 2017 attracted planning to launch IEEE Solid-State
more than 140 attendees, making it Circuits Letters, a fast-paced publica-
one of the most successful SSCS YP tion of original contributions empha-
events ever held. At the 2017 Cus- sizing the transistor-level de­­­­­sign
tom Integrated Circuits Conference of ICs. The first issue is scheduled
(CICC), we were pleased to pres- to be available in 2018. Congratula-
ent two prestigious guest speak- tions to John Long, SSCS Publica-
ers from Si l icon Labs at the SSCS tions chair, for being the dri­­ving
mentoring event; they provided force behind this new publication,
the future generation of the Society and Behzad Razavi, who will be the
with counsel and direction for their editor-in-chief. In 2016, we celebrated
career journey. the 50th anniversary of IEEE Journal
In the area of education, we con­­ of Solid-State Circuits and de­­dicated
tinued to provide student travel an entire magazine issue to this cel-
grants and predoctoral fellowships ebration. Please read about the 50th
6 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
anniversary in the Fall 2016 issue of
IEEE Solid-State Circuits Magazine and
on the SSCS website.
The SSCS conference portfolio
remains a vital service and engage-
ment activity for our global commu-
nity and membership. Of particular
note was CICC 2017, held in Austin,
Texas. The conference was a great
success, with more than 300 people
in attendance. There was a wide array
of techn ic a l s ession s , a r ivet i ng
plenary session, and networking op­­
portunities. The conference was a
perfect blend of information gather-
ing and learning. Additional infor-
mation about CICC 2017 can be found
in the summer issue of IEEE Solid-
State Circuits Magazine.
The progress made within our
Society is an indicator of our contin-
ued promise of delivering excellence
while serving our members and com-
munity faithfully. As one in a long
line of stewards that came before me,
I can look back with a deep sense of
admiration and pride at all we have
accomplished together. I would like
to take this opportunity to offer my
sincere thanks for the support and
dedication of our AdCom members
and Society professional staff.
In closing, let me be the first to
welcome our incoming president,
Prof. Bram Nauta, and pledge my
support to his presidency as he takes
over the reigns on 1 January 2018.
Many of you will know Bram from his
body of work, as a professor at the
University of Twente, and from hav-
ing served the Society with distinc-
tion as editor-in-chief of IEEE Journal
of Solid-State Circuits (2007–2010). I
have every confidence that Bram will
continue the good work and prog-
ress gained from the foundation that
my predecessors gifted to me. I am
proud to hand off the presidency to my
good friend, Bram, knowing the Soci-
ety is in excellent hands.
I wish you all the best in your
endeavors, both personal and pro-
fessional. Thank you once again for
entrusting me with the great honor
of serving as SSCS president.


Wasted Time
T
Three teams of young managers were
staring at a helicopter constructed of
LEGO bricks. Each team had to build a
copy of the helicopter. Team 1 start­
­ed right in, directly laying down the
landing skids and working its way up.
Team 2 divided the tasks, and every­
one started building their part. And
Team 3 reflected on the task, inspect­
ing the example thoroughly. Halfway
through the allotted time, the Team 1
helicopter was close to completion.
Team 2 had already finished the major
building blocks of the machine. Poor
Team 3, they were still hovering around
the example.
But during the second half, the tide
turned. Somehow Team 1 had used
essential parts of the rotor assem­
bly for the horizontal stabilizer.
Confusion followed by disassembly!
Team 2 had finished all subblocks,
but these did not fit together. Crisis!
And the slow starters? Team 3 built
the helicopter straightaway and fin­
ished ahead of time! The supposedly
wasted time had not been wasted
after all.
Wasting time and feeling bored are
curial for all intellectual and creative
processes. Our brains require time
for absorbing, structuring, and con­
solidating new information. Everyday
issues need to be put aside so the
deeper levels of one’s awareness can
connect the new data into the men­
tal framework we call consciousness.
Reflection reveals deeper thoughts
or an unexpected solution to a prob­
lem. It’s hard to explain these neces­
Digital Object Identifier 10.1109/MSSC.2017.2745920
Date of publication: 16 November 2017
a ssoc iate editor’s vie w
sary mental pauses to a 21st century
audience, with its social media and
unlimited distractions. When bored,
smart­­phones or other gadgets will
entertain them!
Time efficiency is all around us,
starting as early as childhood. Modern
parents allow their children every­
thing except boredom. Dealing with
bored children is a horrifying pros­
pect to millennials! When school is
over, the family leaves preferably
that same night for their holiday
vacation. Electronic gadgets prevent
boredom during the trip, and the
next morning, a full day of sched­
uled activities awaits the children.
The parents follow their own over­
filled program. What if they were
left alone together, without a smart­
phone or tablet? Would the couple start
talking and realize how isolated
spouses in modern marriages have
b e co m e? Wa st i ng t i m e to get h e r
strengthens every relationship, with
family, friends, neighbors, and col­
leagues. Dining, playing, or just stroll­
ing together forms life-long bonds
between people.
The new CEO of a consolidated
semiconductor company took the
new management team for two weeks
into the desert without any commu­
nication devices. Some managers col­
lapsed while wasting their time in
a tent; they went home and left the
company. The remaining team grew
the market cap by sevenfold in a few
years’ time.
In industry, wasting time violates
every economic principle. Especially
in our high-tech world, strict sched­
ules are irresistible. New IC designs
IEEE SOLID-STATE CIRCUITS MAGAZINE
Marcel Pelgrom
are first laid out not in silicon, but in
weeks, days, and hours. “Make sure
we have customer samples ready in
week 24!” Successfully designing a
complex IC starts with sitting back
and questioning what needs to be
done. Without thinking through the
fundamentals of a design, a redesign
becomes unavoidable. And often that
redesign is started without taking
sufficient time for evaluating and
reflecting on the first one, already
necessitating the second redesign.
Speeding up the process turns into a
nightmare for all.
Managers walking around and talk­
ing at ease to people can spot signs of
delays earlier than the Excel generals.
Preventive management pays off.
Today’s authors don’t waste any
time either. In 1656, the French sci­
entist Blaise Pascal apologized for his
long letter to a friend: “I would have
written a shorter letter, but I did not
have the time.” Summarizing the essen­
tials of a scientific endeavor into a
concise, stylish description requires
time. Older publications often are
marvels of style and depth because
the authors had time to reflect. Edit­
ing required manually rewriting the
text several times. The process was
so slow that there was ample time to
reflect on how each sentence was best
phrased. Modern authors edit faster
than they can think.
Technology has reduced the time
mankind has to spend on dull, seem­
ingly unproductive tasks. But somehow
we forget to use the freed-up time in a
productive way. What a waste!

fa l l 2 0 17 7

C. Patrick Yue Tian Lu
China’s Latest Overseas M&A in the Semiconductor Industry
T
The historic flood of merger and
acquisition (M&A) agreements that
swept through the semiconductor
industry during the past two years
has slowed to a trickle. The com-
bined value of about a dozen trans-
actions announced in the first half
of 2017 was US$1.4 billion, accord-
ing to the market research firm IC
Insights [1]. That is a significant drop
from US$4.6 billion in the first half
of 2016 and a whopping US$72.6 bil-
lion in the first half of 2015. Despite
the slow start to M&As in 2016, sev-
eral large transactions announced
during the second half of the year
pushed the total value of deals to
near US$100 billion, within s­ triking
distance of the all-time record of
US$107.3 billion set in 2015. Despite
the e
­ xistence of several pending or
rumored deals, including the pend-
ing sale of Toshiba’s memory chip
business, it is unlikely that a second
half of M&A surge will emerge to
bring the value of ­transactions for
the year anywhere close to either
2016 or 2015, IC Insights said.
Dilemma: Restrictions on the
­Overseas M&As of Chinese Capital
The acquisition of overseas semicon-
ductor enterprises with key technical
capability is part of China’s strategy
to improve the domestic semicon-
ductor industry chain. The M&A boom
in the semiconductor industry is the
general trend of consolidation and
Digital Object Identifier 10.1109/MSSC.2017.2748298
Date of publication: 16 November 2017
8 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
china con n ection
economic restructuring. Chinese com-
panies are becoming a major force in
the expansion of the global semicon-
ductor industry, and the growth of
China’s semiconductor industry will
have a profound impact on the global
semiconductor industry. In the past
two years, China has spent a lot of
money and effort on its semiconduc-
tor industry, including independent
construction and overseas M&As.
According to the incomplete statis-
tics of Jiweinet, the total volume of
transactions of China’s semiconductor
overseas M&As ­(completed) so far has
exceeded US$11 billion.
The successful cases of China’s semi-
conductor overseas M&As in­­clude the
following most notable transactions:
■■ Beijing Jianguang Asset M ­ anagement
(JAC Capital) bought NXP Semicon-
ductor’s Standard Products business
for US$2.75 billion and its RF Power
business for US$1.8 billion.
■■ Jiangsu Changjiang Electronics Tech
Company bought STATS ChipPAC
for US$780 million.
■■ Shanhai Capital completed its ac-
quisition of Analogix Semiconduc-
tor for US$500 million.
■ ■ Integrated Silicon Solution Inc.
(ISSI) was acquired by Uphill Invest-
ments for US$731 million.
■■ CITIC Capital Holdings, Hua Capi-
tal Management, and investment
Goldstone bought OmniVision for
US$1.9 billion.
■■ Nantong Fujitsu Microelectronics
(NFME) bought Advanced Micro
Devices’ (AMD’s) semiconductor
assembly and testing services for
US$371 million.
■■ Tsinghua Unigroup bought New
H3C Group (New H3C) for US$2.5
billion.
There are also a number of failed
attempts: Fujian Grand Chip Invest-
ment planned to buy Aixtron for
€670 million, Ingenic Semiconductor
to buy OmniVision for ¥12.62 bil-
lion, Gigadevice to buy ISSI for ¥6.5
billion, Zhejiang Wansheng to buy
Analogix Semiconductor for ¥3.75
billion, China Reform Holdings Cor-
poration to buy Lattice for US$1.3
billion, and China Reform Holdings
Corporation to buy MEMSIC Inc. for
¥1.65 billion.
IC Insights pointed out that govern-
ments around the world are scrutinizing
these deals, which is playing a role in
reducing the number of completions.
Based on the political climate in the
United States and other western nations,
Chinese entities are going to have a
hard time buying Western semicon-
ductor firms, which may make them
hesitant to throw their hat in the ring
on possible deals. For instance, Germany
introduced new rules in July such
that trading in sensitive sectors would
be halted if the country’s interests were
to be affected.
China has bought some semicon-
ductor business overseas in the past,
but the semiconductor industry is
a sensitive industry. The approval pro-
cess is complicated, and hence the
number of acquisition cases have
been reduced. In addition, the Com-
mittee on Foreign Investment in the
United States (CFIUS) has objected to
at least nine foreign takeovers of
U.S. companies so far this year. This
further suggests that, under the cur-
rent administration, CFIUS is acting
more cautiously. CFIUS is responsible
for reviewing whether foreign take-
overs pose a risk to U.S. national secu-
rity. Therefore, Chinese ­companies and
investors that focus on U.S. assets may
hit a snag. Meanwhile, as Chinese
companies have made frequent pur-
chases overseas, the Chinese govern-
ment has also restricted domestic
capital outflows.
“What China’s integrated circuit
industry needs is the experience of
overseas M&A. Since there was no
capital or technology accumulation,
there was no condition for overseas
M&A,” stresses Prof. Shaojun Wei, the
leader of Technological Development
“Core electronic device, High-end
general chip and Fundamental soft-
ware products” and director of the
Institute of Microelectronics of Tsin-
ghua University. Funds are a great
challenge for the “go out” M&As of
China’s IC industry.
China’s IC industry development
had a late start relative to the United
States, Japan, and the European Union
countries as it largely depended on
financing and loans to grow the busi-
ness and thus still lacks sufficient
accumulation of capital to forge M&As
on its own. Thus, it is necessary for
China to use high leverage. For exam-
ple, China Electronics Technology
Group Corporation had to withdraw
its proposal for a merger with Atmel
Corporation after considering various
investment risks, including financial
stress. Prof. Ming Zhang, director of
the Department of International Invest-
ment at the Institute of World Econom-
ics and Politics, Chinese Academy of
Social Sciences, explains in “Report
of China’s Overseas Direct Investment
in Q2 2016” that the overseas M&As of
Chinese enterprises (especially state-
owned ones) mainly rely on external
financing, especially the support of
domestic banks, which brings heavy
debt burden and operational risks.
How to Go Public After Successful
Acquisitions Is Also a Problem
China’s overseas M&As typically take
two steps. First, acquire overseas
assets. Second, list assets in the main-
land. Semiconductor overseas M&As
are being strictly scrutinized because
of the “purchase restriction” of all par-
ties. Meanwhile, how to list acquired
assets at home is a problem. Even if
the M&As are completed, there are still
doubts about whether the advanced
technology can be transferred to domes-
tic enterprises and if new technologies
can be further developed based on cur-
rent technologies.
So far, only Tsinghua Unigroup’s
acquisition of H3C and NFME’s acqui-
sition of AMD’s semiconductor assem-
bly and testing services are regarded
as successful by industry insiders.
Jiangsu Changjiang Electronics Tech
Company completed its acquisition
of STATS ChipPAC but is now faced
with the problem of how to digest its
large operation loss. Ingenic Semicon-
ductor’s acquisition of OmniVision,
Uphill Investments’ acquisition of
ISSI, Zhejiang Wansheng’s acquisi-
tion of Analogix Semiconductor, and
HC SemiTek’s acquisition of MEMSIC
were all thwarted from the China
Securities Regulatory Commission.
NXP as well as other projects that
JAC ­ Capital acquired have not go
public, and the company’s future
remain unclear.
“Compared with other aspects,
the lack of follow-up funds, espe-
cially the R&D investment support-
ing re-innovation will badly restrict
the development of China’s inte-
grated circuit industry. In this case,
the advanced technology purchased
overseas may not be able to pay its
way. With domestic implementation
of deleverage and the tightening of
foreign direct investment, the Chinese
IC industry, which still has a long way
to go, needs new design of policy sup-
port,” says Prof. Tianchun Ye, leader of
national integrated circuit technology
development and director of Institute
of Microelectronics at Chinese Acad-
emy of Sciences.
In fact, the IC industry is a “bottom-
less pit” that requires huge amounts
of continuous investment. Gartner
analysts point out that IC companies
need to compete with industry devel-
opment; namely, the output of the
IEEE SOLID-STATE CIRCUITS MAGAZINE
investment needs to maintain the
investment of technology research
and development in the next round.
If there is no output after dispos-
able investment, additional funds are
needed to catch up with the evolving
technology. Now, quite a number of
Chinese overseas IC acquisitions are led
by capital firms, which generally have
reserves after M&As. However, when
the understanding for product develop-
ment is not thorough, reserve funds may
be insufficient and the predicted invest-
ment period can be prolonged, result-
ing in a huge funding gap. Although the
state strongly financially supports the
development of the IC industry, the big-
gest limitation of financial input is that
it is disposable, which means that the
follow-up support for the same project
is limited.
On the one hand, the international
political and M& A environments
become increasingly complex, and
domestic capital overseas M&As turn
more difficult. On the other hand, the
local IC investment remains popular,
and multiple forms of cooperation
between domestic and international
companies are increasing. With the
establishment of the national funds
and the implementation of various poli-
cies, local governments have been
proactive. Beijing, Wuhan, Shanghai,
and Sichuan have established IC local
funds in the past two years.
The heat wave of investment in
the IC industry will continue in the
foreseeable future. The investment
in production lines, industrial parks,
and public service platforms will like-
ly accelerate. Due to the restriction of
the international situation, industrial
capital will turn to the merger and in-
tegration of domestic enterprises, and
the upstream and downstream indus-
try ecology will be built based on plat-
form enterprises. At the same time,
overseas M&As may start to shift to
different forms of cooperation, such
as establishing joint ventures between
international enterprises and domes-
tic enterprises and searching oppor-
tunities for M&As of high-quality
(continued on p. 12)
fa l l 2 0 17 9
 C ircu it Intu itions
Ali Sheikholeslami
Reinventing the Wheel
W
Welcome to the 15th article in this
column series. As the title suggests,
each article provides insights and
intuitions into circuit design and
analysis. These articles are aimed
at undergraduate students but may
serve the interests of other read-
ers as well. I would appreciate your
comments and feedback as well as
your requests and suggestions for
future articles in this series. Please
send your comments to ali@ece
.utoronto.ca.
In the column in the Spring 2017
issue, we discussed why sinusoids
are so important to circuit design-
ers. In this article, we explore meth-
ods of generating sinusoids, trying
to make intuitive sense of sinusoi-
dal waveforms.
Generating Sinusoids
The real sinusoids, such as cos ^~t h
and sin ^~t h, appear far more com-
plicated when compared to rectan-
gular and triangular waveforms. In
fact, a rectangular waveform is just
a derivative with respect to time of
a triangular waveform. The deriva-
tive of a rectangular waveform is
mostly zero, except at discontinui-
ties. In contrast, cos ^~t h is a very
smooth function; its derivative is
well defined, and its second-order
derivative resembles the original
function. If we were to create a sinu-
soidal function in a one-dimensional
space, we would soon find that it is
almost impossible. However, this
same function is easily understood
Digital Object Identifier 10.1109/MSSC.2017.2745921
Date of publication: 16 November 2017
10 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
and constructed if one resorts to a
y
two-dimensional space.
Consider a ball moving at a con-
stant speed on a circle, as shown in e jθ
Figure 1(a). The constant speed is sin(θ )
captured by a triangular waveform θ x
representing the angle of rotation
cos(θ )
as a function of time [see Figure 1(b)].
If we project the movement of this
ball along the x-axis (or the y-axis),
i.e., a one-dimensional space, we (a)
will have a sinusoid, as shown in θ
Figure 1(c). This is how a sinusoid 2π
is defined using Euler’s formula:
cos ^~t h = Re " e j~t , . It is also how
a sinusoid is generated by an ac (b) Time
generator, powering up buildings
and cities. x (t ) y (t )
In an ac generator, as pictorially
shown in Figure 2, the windings of
a coil are rotated in a circle in the pres-
Time
ence of a constant magnetic field.
Alternatively, a magnet can be rotated
in the middle of a coil. In either case,
there is a projection of a circular mag- (c)
netic field along the winding of the
Figure 1: (a) A point moving at a constant
coil. This is indeed Euler’s formula in
speed on a circle, (b) i as a function of time,
action, where the vector represent- and (c) projection of the point movement
ing the winding area (A) is rotating in along the x-axis and y-axis as functions
a circle and being projected along the of time.
magnetic field vector.
The presence of circular move-
ment is essential in creating a sinu- tor is charged to an initial voltage,
soidal waveform. It is not always V0, closing the switch will create a
obvious, however, that there is a current through the inductor. The
circle behind the creation of every inductor current initially discharges
sinusoid. We look at LC oscillators to the capacitor, reducing its voltage to
illustrate this point. zero. When this occurs, the current
Figure 3 shows a simplified ver- in the inductor will be at its peak,
sion of an LC oscillator consisting charging the capacitor in the op ­­
of an ideal capacitor and an ideal posite direction. The current in the
inductor, with no resistive losses inductor then reverses direction,
in either of the two. If the capaci- and the same trend continues in the
 θ = ωt t=0

C vc (t ) iL (t ) L
θ B
A –
N S

Figure 3: An LC circuit with no resistive

loss and an initial voltage V0 across the
resistor is known to produce a sinusoidal
voltage across the capacitor.
R

Figure 2: A coil rotating at a constant speed in the presence of a magnetic field produces a
iL(t )
sinusoidal voltage at its terminals.

opposite direction. This description or simply

ωt vC (t )
is consistent with the basic equa-
2 2
tions that govern the capacitor and 1/2Cv C + 1/2Li L = constant. (8)
the inductor behavior:
This equation tells us that the
(a)
v C = L di L (1) sum of the stored energy in the
dt √L /2 iL(t )
capacitor and the inductor is con-
dv C √C /2 V0
i L =-C .(2) stant, i.e., it does not change with
dt
time. This energy is equal there-
We can combine the two equa- fore to the initial energy we stored
tions to find a second-order differen- in the capacitor (1/2CV02) . In ad­­ ωt
tial equation for the voltage across dition, (8) tells us that the voltage √C /2 vC (t )
the capacitor: across the capacitor and the current
of the inductor form an ellipse, or
d2 vC
LC + v C = 0.(3) a circle w ith proper scaling fac-
dt 2
tors, as shown in Figure 4(a) and (b)
This equation is known to have a (b), respectively. In other words, the
sinusoid as its solution. In fact, it voltage across the capacitor and the Figure 4: (a) The trajectory of the voltage
turns out that the voltage across the current in the inductor (with proper across the capacitor and the current through
capacitor and the current through scaling factors) will always lie on a the inductor is an ellipse. (b) When properly
the inductor will be of the forms: circle, such that the energy in the scaled, the trajectory becomes a perfect
circle. The square of the radius of this circle
system remains constant. What we
represents the energy stored in this circuit.
v C = V0 cos ^~t h (4) really observe as the voltage across
i L = I 0 sin ^~t h, (5) the capacitor is only the projection
of the state of the system (voltage- eral derivation of v C and i L can be
where ~ = 1/ LC and I 0 = C/L V0 . current pair) along the voltage axis found in most introductory text-
Clearly, the voltage across the ca­­ (for the voltage across the capacitor) books such as in [1]. Here, we sim-
pacitor and the current through the and along the current axis (for the ply plot, in Figure 5(b), the energy
inductors are sinusoids, as found by inductor current). stored in the capacitor, the energy
solving the differential equation, but L et us now e x plor e wh at h ap - stored in the inductor, and the sum of
where is the circle in this solution? pens if we add a resistor in parallel the two energies. The energy moves
If we multiply the opposite sides with the LC circuit, as shown in Fig­­­ back and forth between the capacitor
of (1) and (2), we will have ure 5(a). We assume the resistor is and the inductor but loses its value
large enough (R > 0.5 L/C ) to cre- in each cycle. The total energy in the
dv C
Cv C + Li L di L = 0.(6) ate an underdamped behavior. In system is monotonically decreasing
dt dt
this case, the resistor will begin to as time progresses.
In other words: deplete the stored energy by turn- It is also helpful to plot a trajec-
1 d ^Cv 2 + Li 2h = 0, (7) ing it into heat. What happens to our tory of the scaled versions of the
C L
2 dt state variables v C and i L ? The gen- voltage across the capacitor and the

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 11

 will sustain the oscillation longer;
t=0
√L /2 iL(t ) the radius reduces at a slower rate.
A smaller resistor will attenuate the
+
oscillation faster and beyond a cer-
C vc (t ) iL (t ) L R tain value (R # 0.5 L/C ) will not
– allow any oscillation, corresponding
√C /2 vC (t ) to the overdamped circuit behavior.
(a) In summar y, we have claimed
that there is always a circle behind
Energy

Stored Energy in C
every sinusoid. Identifying such cir-
Stored Energy in L
Total Stored Energy
cles may seem like reinventing the
Figure 6: The voltage-current trajectory wheel but this often leads to a new
of a leaky LC oscillator can be a spiral, intuition and understanding of cir-
signifying the loss of stored energy as time cuit behavior.
progresses.
Time
(b) Reference
[1] R. E. Thomas, A. J. Rose, and G. J. Tous-
current in the inductor. Figure 6 saint, The Analysis and Design of Linear
Figure 5: (a) An LC circuit with a resistive shows that this trajectory is a spiral, Circuits, 7th ed. New York: Wiley, 2012.
loss in parallel. (b) The stored energy in this
circuit flows back and forth between the
a circle whose radius is diminish-
inductor and the capacitor, losing its value ing with time, signifying the energy
to heat in the resistor with time. loss to the resistor. A larger resistor 

contributors (continued from p. 3)

Payam Heydari is L o n g Ya n i s w i t h Joonsung Bae is

a full professor of Samsung Electronics, with Kangwon Na­
electrical engineer- Korea, where he leads ti­o nal University,
ing at the University of analog interface cir- where he is an assis-
California, Irvine, and cuit developments tant professor in the
is noted for his work for next-generation Department of Elec-
in silicon-based millimeter-wave and biosensors. trical and Electronics Engineering.
terahertz IC design. 

china con n ection (continued from p. 9)

product lines after the integration References 4ef2d4531b90d6c85ec3a87c24028905f85

[1] IC Insights. (2017). Value of semiconduc-
of international giants. tor industry M&A deals slows dramati-
In short, the M&A activities may cally in 1H17. [Online]. Available: http://
w w w.icinsights.com/news/ bulletins/
look sweet at first but some of them Va l u e - O f- S e m i c o n d u c t o r - I n d u s t r y -
taste bitter. More importantly, the MA-Deals-Slows-Dramatically-In-1H17-/
[2] CCIDWISE. (2017). Six trends of semicon-
acquired technology and asset may be ductor industry In 2017 [Online]. Avail-
hard to digest. able: https://wenku.baidu.com/view/5ac
4a.html
[3] Business Wire. (2017). Shanhai Capital
completes acquisition of analogix semi­­
conductor [Online]. Available: http://
w w w.businessw ire.com/news/
home/20170 406006025/en/Sha n ha i-
Capital-Completes-Acquisition-Analogix-
Semiconductor


12 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 A C ircu it for All Seasons

Behzad Razavi

The Decision-Feedback Equalizer

T
The decision-feedback equalizer (DFE)
dates back to the 1960s [1] and be­­gan
to appear in high-speed wireline com­­
munication systems in the early 2000s.
In this article, we study the properties
of this circuit and describe its “ana-
log” implementations.
The Need for Equalization
As high-speed random data propa-
gates through a medium with a lim-
ited bandwidth (also called a “lossy”
medium), it is dispersed. That is, the
data edges become slower, possi-
bly disallowing full transition if a
010 or 101 sequence occurs [Fig-
ure 1(a)]. This sluggishness of the
channel also makes the zero crossing
times of the data a function of the bit
amp­­litudes, causing significant jitter.
Both degradations increase the bit-
detection error rate. In the frequency
domain, the channel attenuates the
high-frequency content of the data
[Figure 1(b)].
say the equalizer provides a high-
frequency “boost” to compensate for
the channel loss.
The Need for Decision-Feedback
Equalization
While intuitively appealing, linear
equalization faces three issues. First,
since it requires a large amount of
boost for very lossy channels, it sig-
nificantly amplifies high-frequency
noise, corrupting the data. Second,
a high boost demands multiple
stages, each one inevitably limiting
the bandwidth and consuming con-
siderable power. Third, the inverse
response provided by a linear equal-
Din
Tb
Channel Response
izer does not suffice in most prac-
tical cases. Specifically, a typical
channel introduces, in the signal
path, i mp e d a n ce discontinuities
(mismatches) resulting from connec-
tors and other physical interfaces
between boards, cables, etc. Such
discontinuities manifest themselves
as deep notches in the channel’s fre­­
quency response (Figure 2) that would
be difficult to compensate by a lin-
ear equalizer.
To appreciate the beauty of DFEs,
we first return to the time domain and
view the data waveform as the superposi-
tion of random steps shifted in time by
integer multiples of Tb [Figure 3(a)].
Dispersive
Dout
Channel
t
(a) t
Spectrum of

The frequency-dependent chan- Random Data

nel loss depicted in Figure 1(b) can
be undone by means of a circuit
having the inverse response, i.e., a
high-pass filter (HPF). As illustrated
in Figure 1(c), if subjected to such a
response, the received data assumes (b) f
its original, undispersed shape and Dispersive
more easily lends itself to detec- Channel HPF
tion. This HPF exemplifies a “linear”
equalizer as it can be approximated
by a finite impulse response filter t t
incorporating only linear stages (delay
(c)
units and scaling coefficients). We
Figure 1: (a) The dispersion of random data in a lossy channel, (b) the channel frequency
Digital Object Identifier 10.1109/MSSC.2017.2745939 response showing attenuation of high-frequency components, and (c) the use of an HPF to
Date of publication: 16 November 2017 equalize the channel.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 13

 [Figure 1(b)] or as narrowband rejec-
Channel tion (Figure 2). We surmise that ISI can
Response
be suppressed if we reconstruct the
tail values and subtract them from the
next bit(s).
Let us implement this idea for
f canceling the first postcursor in Fig-
ure 3(b). We must delay the present
Figure 2: Notch in frequency response due bit by one bit period, scale this result
to impedance discontinuity. by a factor equal to h 1, and subtract
it from the next bit. Figure 4(a) shows
Due to the channel imperfections, such an arrangement.
each output bit is broadened, exhib- If we consider D in as the pres-
iting a tail that interferes with the ent bit, D out holds the previous bit
next bit(s). Called intersymbol inter- and D F a scaled copy thereof. Thus,
ference (ISI), this phenomenon is D in-D F is free from the first post-
more clearly seen in the impulse c ur sor, whet her it is cr e ated by
response of the channel [Figure 3(b)]. wideband loss or impedance discon-
We observe that the tail values at Tb, tinuities. With a linear delay element,
2Tb, etc., (called the “postcursors”) this loop is still a “linear” equalizer.
respectively represent the ISI intro- A side effect is that the amplitude
duced in the next bit, the bit after it, noise at the output is scaled by a fac-
and so on. In general, energy removal tor of h 1 and added to the input data,
from a signal’s spectrum causes ISI, degrading the signal-to-noise ratio of
whether it occurs as wideband loss each bit.
Din
t Main
Dout Cursor h0 Postcursors
t h1
Dispersive h2
Dout Channel
t 0 Tb 2Tb
t Higher-order postcursors can
(a) (b)
Figure 3: (a) Random data viewed as superposition of steps and (b) the impulse response of
a lossy channel.
This issue can be remedied if
the delay element is followed by a
limiter, also known as a “slicer,” so
as to remove the amplitude noise
[Figure 4(b)]. The loop thus stops
the noise from circulating and acts as
a nonlinear equalizer. For robust op­­
eration, we replace the delay stage
and the slicer with a f lipf lop ( F F )
[Figure 4(c)], recognizing that typi-
cal FFs provide both a one-period
delay and limiting action on the ampli-
tude. We can say the loop feeds the
FF’s decision back to the input, hence
the term DFE. As illustrated in Fig-
ure 4(d), the summer output, D sum,
is free from the first postcursor, mak-
ing greater voltage excursions with
less jitter and allowing better de­­
tection. Sensed by the flipflop, this
output is the most critical node in
the circuit.
In the DFE loop of Figure 4(c), two
parameters must be adjusted to reach
optimum performance. First, the clock
sampling edges must occur at the
peaks of D sum, necessitating a clock
recovery circuit. Second, the first “tap”
value, h 1, must be chosen according
to the actual channel response. This
is typically accomplished by moni-
toring the eye diagram at the summer
output and adjusting h 1 to maximize
t its height.
also be removed by a DFE. Depicted
in Figure 5, a two-tap realization
returns scaled copies of the last two
bits to the input.

Slicer Design Issues

Din Tb Dout Din Tb Dout In addition to clock phase alignment
+ +
–
and proper setting of the feedback
– h1 h1
tap, the DFE shown in Figure 4(c) must
DF DF also deal with the total loop delay.
(a) (b) We predict that, at a sufficiently high
Summer FF Din
data and clock rate, the circuit begins
Din
to incur errors.
D Q Dout
+ Dsum Dsum t To study the DFE speed limitations,
–
consider the differential top­ology in
CK t Figure 6 and suppose the slave latch
h1 Dout
in the FF enters the sense mode on
DF the falling edge of the clock, at t = t 1 .
t
(c) (d) The slave output requires a certain
Figure 4: (a) A feedback loop canceling the first postcursor, (b) the addition of a slicer to amount of time to change state, called
suppress amplitude noise, (c) the use of an FF as a delay element and a slicer, and (d) the the “clock-to-Q” delay, TCK -Q = t 2 - t 1 .
resulting ­waveforms. This t­ransition ­propagates through

14 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

the scaling stage and causes a change
at the summing node. This node
has a finite time constant, introduc- Din D Q D Q Dout
+
ing its own delay, TFB = t 3 - t 2 . When –
–
CK goes high, the master latch enters
the sense mode and must change its
CK CK
output according to the new value of
h1
D sum before CK goes low again. The
necessary time for this change is the
setup time of the FF, Tsetup = t 5 - t 4 . h2
Thus, TCK -Q + TFB + Tsetup must not
exceed one clock cycle and hence one
bit period:

Figure 5: A two-tap DFE architecture.

TCK -Q + TFB + Tsetup # Tb .(1)

Master Slave
Similar speed limitations exist in other
Latch Latch
variants of this architecture as well (see Dsum DM
the “DFE Variants” section). Din D Q D Q Dout
Three other nonidealities affect +
–
the performance of the DFE. First,
the data input port of the summer in
CK CK
Figure 6 cannot be arbitrarily non-
linear because the dispersed data’s h1
amplitude carries information about DF
the channel and must not experience
CK
significant limiting. We can see intui-
tively that, if the D in waveform in
Figure 4(d) is greatly amplified and Dout
sliced, then all of the bits exhibit a Dout
full swing but the jitter introduced
by the channel remains. As a guide- Dsum
line, we choose the 1-dB compression Dsum
point of this port to be greater than
DM
the main cursor amplitude [2] so that
the nonlinearity negligibly increases DM
the ISI. t1 t2 t3 t4 t5 t
Second, the input offset of the
FF, VOS, shifts the net voltage sensed
Figure 6: A DFE with differential signal paths.
at the summing node, D sum, equiv­­
alently deg rading the volt age
m a r gin for the negative or posi-
tive data values sampled by the FF.
Third, the total noise in D sum, Vn, +
yields a finite bit error rate. This –
noise includes that produced by
the summer and the stages preced- +h1
ing the DFE and the input-referred
MUX

Din D Q Dout
noise of the FF. As a rule of thumb,
–h1
w e e n s u r e t h a t 8 (4VOS + Vn, rms)
r em a in s less t h a n the peak data
–
swing D sum. The factor of eight is +
Select
CK
chosen to ensure error rates on the
order of 10 -12 and the factor of four
represents the four-sigma variance
of the offset. Figure 7: An unrolled DFE architecture.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 15

DFE Variants
A multitude of DFE architectures have CK1/2 CK1/2
been proposed to ease the design
tradeoffs. We study some here.
D Q Deven Din D Q Deven
It is possible to transform the +
– –
feedback loop of Figure 4(c) to a pre- h1 h1

dictive or “unrolled” topology. Sup-
pose D in and D out swing between –1
and +1. Since we wish to compute
D in - h 1 D out, we can equivalently
consider D in - h 1 and D in + h 1 as the
only two possible levels that must
reach the FF. The selection between
these two values can be made by
the previous bit. Figure 7 shows the
resulting “unrolled DFE” [3]. Here,
the previous bit available at D out
decides whether D in - h 1 or D in + h 1
must travel through the multiplexer
and be sliced by the FF. We note that
the summing nodes lie outside the
feedback loop, which is the princi-
pal advantage of this arrangement.
The timing budget is now given by
TCK -Q + Tsetup + TMUX 1 Tb, where TMUX
denotes the delay from the select
input of the multiplexer to its out-
put. In some cases, TMUX is less than
TFB in (1). However, the D out signal
must be level shifted and/or ampli-
fied to properly switch the multi-
plexer, leading to additional delay.
At very high speeds, it is desir-
able to drive the DFE with a half-
rate clock, CK 1/2, which is simpler
to generate and distribute. Fig-
ure 8(a) shows a half-rate DFE [4],
where the FFs are clocked by CK 1/2
and CK 1/2, thereby demultiplexing
the data by a factor of two. Each out-
put bit lasts for 2Tb seconds and,
after subtraction from D in, is fed
to the FF in the other branch. This
topology nonetheless does not re­­­­­­­lax
the loop timing budget given by
(1). It also consumes about twice as
much power as the full-rate DFE of
Figure 4(c).
Another half-rate DFE architecture
is depicted in Figure 8(b) [5]. Here,
the half-rate outputs are multiplexed
so as to reconstruct the full-rate data,
with the result serving as the feed-
back signal. While using only one
summer, this method adds the mul-
tiplexer delay to TCK -Q + TFB + Tsetup,
degrading the speed.
Din
h1
–
+
D Q
CK1/2
(a)
Figure 8: Half-rate DFE architectures with (a) two summers and (b) one summer and one
multiplexer.
I1
X Y
Vin1 M1 M2
CK MCK1
Figure 9: A comparator input stage based on two differential pairs.
At very high speeds, the sum-
ming node and the FFs can incorpo-
rate inductive peaking for a greater
bandwidth and a smaller loop delay.
This improvement comes at the cost
of a more complex layout and signal
distribution difficulties.
Questions for the Reader
1) Can the delay stage and the ­slicer
in Figure 4(b) be realized as a sin-
gle limiting differential pair?
2) Can the unrolled DFE of Figure 7
­accommodate a second tap?
Answers to Last Issue’s Questions
1) In Figure 9, why can we not apply
Vin1 and Vin2 to M 1 and M 2 and
Vr1 and Vr2 to M 3 and M 4 ?
In such a case, each differential
pair can experience a large input
difference even when the compar-
ator is making a critical decision.
MUX
D Q Dodd
Dodd
CK1/2
(b)
I2
Vr 1 Vr 2 M3 M4 Vin2
CK MCK2
As a result, the transconductance
of the two pairs falls considerably,
making the offsets of the subse-
quent stages significant.
2) How does the characteristic shown
i n Fig u r e 10 ( b) c h a nge i f the
front-end comparator has an off-
set equal to 1.5 least-significant
bits (LSBs)?
In the ideal case, we have
V +F -V -F = V +in -V -in if V +in - V -in 2 0
a n d V +F - V -F = - (V +in - V -in) i f
V +in - V -in 1 0. With a compara-
tor offset of 1.5 LSBs, the former
holds if V +in - V -in 2 1.5 LSBs and
the latter, if V +in - V -in 1 1.5 LSBs.
That is, the circuit negates the
differential input even for values
reaching = 1.5 LSBs. The result-
ing characteristic is shown in
Figure 10(c).
(continued on p. 132)

16 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 guest editorial

Wanda Gass

Women in Circuits

I
In 2016, Jan Van der Spiegel, presi- ■■ Ingrid Verbauwhede, AdCom mem- VLSI Symposium, the Asian Solid-State
dent of the IEEE Solid-State Circuits ber and IEEE Fellow Circuits Conference, and ESSCIRC,
S o c i e t y (SSCS), com m issioned a ■ ■ Marian Verhelst, IEEE Journal in addition to ISSCC. They have also
n e w committee, Women in Circuits of Solid-State Circuits Editorial organized Chapter events in which
(WiC), to improve the recruitment, Board member and Distinguished local female speakers were invited to
retention, and advancement of fe­­ Lecturer present. The first one was in the San
male members within the Society. ■■ Alice Wang, AdCom member and Francisco Bay Area, where Apple Vice
To increase the visibility of women in WiC chair. President Kate Bergeron and Rikky
volunteer leadership positions in the I hope you enjoy reading this collec- Muller, cofounder of Cortera Neuro-
SSCS, this issue offers a series of tuto- tion of tutorials. technologies, made presentations that
rials, written by women in our Soci- Last year, the WiC Committee had were open to all Chapter members.
ety, covering several emerging trends its first meeting at ISSCC and started by (Read more about this luncheon in the
in our industry. counting the number “Society News” column
The following SSCS members were of women in the SSCS, in this issue.) More in­­
invited to write these tutorials: at each membership formation about WiC
■■ Alison Burdett, Program vice-chair level, over the past To increase the vis- can be found on the
of the International Solid-State several years to see if ibility of women in SSCS website un­­d e r
Circuits Conference (ISSCC) the new activities will volunteer leader- t h e W o m e n i n Cir-
■■ Andreia Cathelin, SSCS Adminis- in­­­crease the number ship positions in cuits tab.
trative Committee (AdCom) mem- of female Society mem-
the SSCS, this issue In 2018 at ISSCC,
ber and Steering Committee chair bers. In 2017, Alice
offers a series of the WiC ­C om m it tee
of the European Solid-State Cir- Wang be­­came chair of
tutorials, written will be hosting a work-
cuits Conference (ESSCIRC) the WiC Committee
by women in our shop on Sunday eve-
■■ Terri Fiez, AdCom member and and has enlisted volun-
Society, covering ning that will be open
IEEE Fellow teers toorganize sev-
several emerg- to all conference at­­
■■ Vivienne Sze, associate profes- eral activi­­ties. These
ing trends in our tendees. The theme
sor of Electrical Engineering and activities include part­­­
industry. of the workshop is Cir-
Computer Science at the Massa- ner­­­­­ing with the SSCS cuits for Social Good
chusetts Institute of Technology Young Professionals and will feature key-
Committee to provide more opportunities notes and invited talks from 6 p.m.
for networking and mentoring. to 7:30 p.m. I hope to see you there!
Digital Object Identifier 10.1109/MSSC.2017.2748299 Many volunteers stepped up to orga-
Date of publication: 16 November 2017 nize networking events in 2017 at the 

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 17

 Andreia Cathelin

T
he race on the
C o m plement a r y
Metal–Oxide–Semi-
conductor (CMOS)
More Moore integra-
t ion sc a le h a s br oug ht to light
several major limitations for effi-
cient planar process integration
starting with the 40 nm technology
node. The transistor channel was
more and more difficult to control
in terms of electrostatics, and many
process engineering methods (such
as, for example, Silicon strain) were
used to provide transistors with
good carrier speed and decent elec-
trical characteristics. Starting from
the 28-nm node, the obvious solu-
tion for transistors with increased
electrical performances was the
use of fully depleted devices. Two
integration methods have been
identified by the semiconductor
industry for these fully depleted
devices: Fully Depleted Silicon on
Insulator (FD-SOI) CMOS and Fin-
FET CMOS devices. While the fun-
damental carrier semiconductor
equations are similar, the process
integration is very different. This
a r t icle fo c uses on pla n a r F D -
SOI CMOS technology features as
integrated by STMicroelectronics

Fully Depleted Silicon on

Insulator Devices CMOS
The 28-nm node is the perfect technology for analog,
RF, mmW, and mixed-signal system-on-chip integration

Digital Object Identifier 10.1109/MSSC.2017.2745738

Date of publication: 16 November 2017

18 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

 in the 28-nm node [1], [2], and
its specificities for analog, radio
frequency (RF), millimeter wave
(mmW), and mixed signal system-
on-chip (SoC) integration.
Figure 1 is a generic cross sec-
tion of an FD-SOI CMOS device.
This technology is called Ultra-
Thin Body and Buried Oxide
(UTBB) FD-SOI CMOS as, in the
28-nm node, the active device
has a ultra-thin conduction film
(7 nm) and lays atop a 25-nm
insulation layer of buried oxide
(BOX). This planar topology has
the following direct implications.
Thanks to the SOI BOX layer, the
transistor gets total dielectric
isolation. No channel doping is
needed as, thanks to the thin
silicon film, the channel is fully
depleted. Also enabled by this
technology, no pocket implants
are needed for the source and
drain, which naturally enhances
the analog/RF transistor’s behav-
ior. Another implication of the
thin BOX layer is that the front-
side transistor’s electrostatics
can be controlled from under-
neath the BOX (an area called the
transistor body). By applying a
voltage on the transistor body,
one can change or modulate the
threshold voltage of the main
(front side) transistor. We can see this
device as well as a planar dual-gate
device: the front gate is the regular
one (like in bulk technology) and the
second one comes from the body tie,
with the BOX as the back-side gate
oxide. As the thickness ratio of the
front and back gate oxides is about
ten, the front-side transistor’s trans-
conductance Gm is ten times bigger
than the one on the back-side gate.
In terms of manufacturing, the
28-nm FD-SOI CMOS process from
STMicroelectronics shares most of
process steps with the equivalent
28-nm bulk technology from STMi-
croelectronics. It is a modified bulk
28-nm high-K metal gate low-power Figure 2 is a cross section of
(LP) process using the same back end N - type MOS (NMOS) and P-type MOS
of the line and gate module. Several (PMOS) transistors in a regular bulk
process steps, specifically channel CMOS technology. A threshold voltage
implants, halo implants, and mask- (VT ) modulation can be obtained by
ing levels, are removed compared to body bias tuning (VBBN and VBBP).
the traditional 28-nm bulk technol- This is very limited by the thresh-
ogy thanks to the presence of the old voltage of the parasitic source/
undoped FD-SOI channel. There is drain diodes toward the respective
less than a 20% change with respect transistor body. As this voltage is about
to a classical CMOS bulk flow; the two 0.6 V, the effective safe body-biasing
extra steps are related to the hybrid- (BB) voltage range spans from 0 to
ization and raised source/drain epi- ~ 0.3 V (modulus). The body factor
taxy. At this node, more than 10% of in bulk technologies is also quite lim-
the process steps and seven masks ited (25 mV/V); hence the total possible
are saved, resulting in an overall ma­­ variation of the threshold voltage is
nufacturing process cost saving of limited in bulk technologies to only a
10% [3]. This process offers the effi- few tens of millivolts.
ciency of fully depleted devices along Fig u r e 3 pr e s e nt s c r o s s s e c-
with the manufacturing yield of pla- tions of the NMOS and PMOS tran-
nar technologies. sistors in the 28-nm UTBB FD-SOI
technology. The darker side of the
FD-SOI Devices and Body Biasing N-wells corresponds to the deep-N-
Opportunities well layer.
For good understanding of the spe- Regarding the regular VT (RVT)
cific features of different FD-SOI transistors [see Figure 3(b)], one can
transistors, let’s first start with a observe the specific UTBB FD-SOI
small reminder from planar bulk topology, with the raised sources and
CMOS transistors. drains and the thin BOX isolating
FBB
0 3V
Gate
Source Drain
Ultra-Thin Buried Oxide
Total Dielectric Isolation
No Channel Doping
No Pocket Implant
Figure 1: A generic cross section of an UTBB FD-SOI transistor.
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 19
 Starting from the 28-nm node, the obvious very efficient body biasing on these
RVT devices, called here reverse body
solution for transistors with increased biasing (RBB), with the effective bias-
electrical performances was the use ing voltage range from roughly 0 to
3 V (modulus).
of fully depleted devices. Let’s now focus on the low VT
(LVT) devices, as depicted on the
the front-side transistor from its for NMOS and respectively embed- upper part of Fig ure 3(a). These
body. In this case, for VT modula- ded P-well to deep N-well for PMOS devices are also called “flipped-
tion through body biasing, the only devices. These are Zener-type diodes, well” devices, as in order to obtain
limiting parasitic diodes are those with an opening voltage around the lower VT characteristics, the
between deep N-well to P-substrate modulus of 3 V. Hence, we can do a process engineering has proposed
a solution where the NMOS devices
lay on an NWell body, and respec-
tively the PMOS on a PWell body.
NMOS PMOS In an equivalent way, we can apply
G G forward body biasing (FBB) on these
S S VBBP devices, with also an equivalent
VBBN D D
body voltage variation from roughly
0 V to 3 V (modulus).
The body factor for both families
P-Well N-Well
of transistors (RVT and LVT) is much
larger in FD-SOI than in an equi­
P-Sub valent body node, in 28 nm being
~85 mV/V, for the thin oxide devices.
This argument together with the
Figure 2: A cross section of CMOS transistors in a regular bulk technology. very wide body biasing range result

NMOS PMOS

Nominal
G G
VBB Biasing Mode
D S D S
VBBN VBBP
LVT
NMOS GND FBB
Box Box
P-Well –3 –0.3 3
N-Well

LVT
PMOS GND FBB
P-Sub
–3 +0.3 3
(a)
PMOS NMOS

G G
D S D S
VBBP VBBN
RVT RBB
PMOS VDD
Box Box
P-Well –3 VDD/2 –0.3 3
N-Well

RVT RBB
NMOS GND
P-Sub –3 VDD/2 +0.3 3
(b)

Figure 3: A cross section of 28-nm UTBB FD-SOI CMOS transistors: (a) LVT transistors and (b) RVT transistors.

20 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

in an unprecedented wide variation
of the threshold voltage of around
0.6 RBB
250 mV, as depicted in Figure 4.
0.4
FBB
FD-SOI Transistors 0.2 NLVT

Analog Features
When we were following the his-
torical nanometer downscaling of
the CMOS bulk road map, the ana-
log designers had to get used to the
fact that the analog behavior of the
respective transistors was getting
worse and worse with the down-
scaled technology node. This was
inherent from the planar CMOS bulk
transistor topology, in the race for
faster and faster digital behavior
and/or low power. Some foundries,
like STMicroelectronics, had over-
come that in the 65-nm node by
introducing a specific analog tran-
sistor called HPA (high performance
analog) that solved this by eliminat-
ing the transistor pockets. In the
28-nm FD-SOI planar technology,
thanks to the thin film structure, we
Vth (V)
0.0
FBB
–0.2
–0.4
–0.6
–3 –2
Figure 4: The threshold voltage (VT) variation with respect to BB voltage for RVT and LVT
devices in 28-nm FD-SOI technology.
do not need transistor pockets, and
we recover native analog behavior
from a “simple” and well-controlled
fully depleted conduction channel.
FD-SOI hence brings several ad­­
vantages for analog designers in
terms of efficient short-channel
devices, improved analog perfor-
mances, and lower noise variability.
NRVT
PLVT
PRVT
RBB
–1 0 1 2 3
VB (V)
In Figures 5–7, we compare the 28-nm
FD-SOI technology with an equiva-
lent 28-nm node LP bulk technology,
both from STMicroelectronics.
Figure 5 shows major improve-
ments of FD-SOI versus bulk solu-
tion regarding analog gain and VT
matching parameter. For example, in
28-nm FD-SOI, an LVT NMOS device

1E+3 5.0
dc Gain-Lin (Gm/Gds) Avt (mV.µm) 28LP Bulk
28FDSOI 4.5 Curves for W = 1 µm

1E+2 4.0
3.5
28LP Bulk
3.0 28FDSOI
1E+1
2.5
2.0
Gate Length (m) Gate Length (m)
1E+0 1.5
1E–8 1E–7 1E–6 1E–5 1E–8 1E–7 1E–6 1E–5
(a) (b)

Figure 5: (a) Analog gain (Gm/Gds) and (b) matching parameter (Avt) for NMOS LVT devices in 28-nm FD-SOI technology (red) compared
with 28-nm LP bulk (blue).

21 140
20 Gm/ld (1/V) 28FDSOI Cgg (fF/µm) 28LP Bulk
120
19 28FDSOI
18 100
28LP Bulk
17 80
16
15 60
14 40
13
12 20
Gate Length (m) Gate Length (m)
11 0
1E–8 1E–7 1E–6 1E–5 1E–8 1E–7 1E–6 1E–5
(a) (b)

Figure 6: Improved analog performance (Gm/Id and total gate capacitance Cgg) for NMOS LVT devices in 28-nm FD-SOI technology (red)
compared with 28-nm LP bulk (blue).

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 21

of a size 1 nm/100 nm can show an ure 7. As an example, for an LVT NMOS If we talk about RF operation frequency
excellent analog performance with of 1 nm/120 nm bi a s e d at a 1 nA below 10 GHz, we can then work with a
a DC gain of 80 and a sigma(VT ) of drain current, we get 1.5 dB lower 1/f transistor length of 100 nm. Perfor-
only 6 mV. noise in an FD-SOI than in bulk. This is mances such as a maximum available
Figure 6 shows that FD-SOI pro- a typical value of main branch current gain (MAG) of 12 dB and NFmin of ap-
vides a higher Gm for a given current, for a low-noise amplifier in low giga- proximately 0.5 dB can be obtained for
with respect to the equivalent 28-nm hertz frequencies. a current density 125 nA/nm (here
LP bulk node. This, combined with W = 1 nm). Going higher in frequency
the lower parasitic capacitances com- FD-SOI Transistors will then require working with the
ing inherently from the SOI insula- RF and mmW Features minimum transistor length of 30 nm.
tion, permits the designer to achieve Thanks to the deep submicron li­­ Here, for example, for a 60-GHz op­­­­
higher operation bandwidths for a thography, this technology node eration frequency, a MAG of 12 dB and
given current consumption, or —if provides very fast transistors. The NFmin of approximately 1.3 dB can be
working at constant bandwidth—lower intrinsic devices [front end-of-line obtained, when working at a current
power consumption. (FEOL) plus Metal1 contact] in the density of 200 nA/nm. This value is
The variability in planar FD-SOI LVT flavor, for example here NMOS, 33% lower than in 28-nm LP CMOS bulk.
technologies is improved with re­­ show fT and fmax superior to 300 GHz. In a fully integrated schematic, all
spect to an equivalent LP bulk node, (See Figure 8.) back end-of-line (BEOL) layers have to
thanks to the simpler manufacturing We can distinguish two types of be added atop the intrinsic transistor
process steps. This helps as well for dimensioning and biasing stra­ tegies, to withstand the respective current
the noise behavior, as is shown in Fig- depending on the operation frequency. biasing conditions, respect the metal

3.0E–5 1E–4
Input Ref. Voltage Noise at 1 Hz Input Ref. Voltage Noise at 1 Hz
Noise_Sv at Hz (V/√Hz)

Noise_Sv at Hz (V/√Hz)

for NLVT W = 1 µm/L = 1 µm 9E–5 for NLVT W = 1 µm/L = 120 nm

2.5E–5
8E–5
2.0E–5 7E–5
6E–5
1.5E–5 28LP Bulk
5E–5
1.0E–5 4E–5 28LP Bulk
28FDSOI
Idrain/W (µA /µm) 3E–5 28FDSOI
Idrain/W (µA /µm)
5.0E–6 2E–5
1E–6 1E–5 1E–4 1E–3 1E–2 1E–1 1E+0 1E+1 1E+2 1E–4 1E–3 1E–2 1E–1 1E+0 1E+1 1E+2 1E+3
(a) (b)

Figure 7: Noise behavior for NMOS LVT devices in 28-nm FD-SOI technology (red) compared with 28-nm LP bulk (blue).

400 400

300 300
fmax Meas [E+9]
fT Meas [E+9]

200 200

100 100

0 0
0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0
vgs [E+0] vgs [E+0]
fT Versus vgs (Model = LVTNFET WFING = 5e–07 fmax Versus vgs (Model = LVTNFET WFING = 5e–07
vds = 1 L = 3e–08) vds = 1 L = 3e–08)
(a) (b)

Figure 8: The high-frequency behavior (fT and fmax) of LVT NMOS 0.5 μm/30 nm in 28-nm FD-SOI CMOS.

22 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Top View Cross Section
35

Source
Gate 30

Drain
25 U fmax
20
15 –20 dB/dec
Source 10
Drain

5 m4 m2
0 fT
–5 H21
Gate –10
1E10 1E11 1E12
Frequency (Hz)
(a) (b)

Figure 9: Full ten metal layers BEOL implementation of an NLVT transistor of 16 µm/30 nm, Wfinger = 800 nm for a drain current of
5.2 mA. The initial design kit Pcell stops at Metal 1. Measurements are performed on 10–110 GHz and, respectively, 220–330 GHz test
benches independently.

density rules, and fulfill the electro-

migration current density rules up to 550
a maximum operation temperature. 500 28FDSOI
At the same time, the designers have 450
Slow
to take great care in minimizing the 400
Vth (mV)

full BEOL effects on the effective fT
and fmax degradation. An example of
implementation is given in Figure 9(a)
for a transistor in a mmW oscillator
core, where thin staircase accesses
for low fringe parasitic capacitors
between drain and source have been
implemented, and the gate access
resistance is optimized through a
dual gate access [4]. On-wafer de-
embedded measurements of this
device showed that such a full BEOL
transistor still sustains a very good
mmW performance: fT of 246 GHz
and fmax of 359 GHz, as depicted in
Figure 9(b).
Deep submicron CMOS has the
counterpart of very low and dense
BEOL, with a large number of metal
layers. While this might be seen as
a limiting point for mmW design,
the eight metal layers of this tech-
nology obtain decent values for the
integrated passive devices. This is
enabled by the operation in a low
parasitics environment coming with
the SOI technologies. Several exam-
ples can be cited here: an inductor
of L = 0.5 nH with a Q factor of 18 at
10 GHz, a varactor of C = 50 fF with a
Q factor of 20 at 20 GHz, and a 50-Ω
transmission line of 0.8 dB/mm losses
at 60 GHz.
350
300
250
28LP Bulk
200
150
1E–8
Figure 10: VT process corners for LVT NMOS devices, comparing a 28-nm FD-SOI CMOS and
28-nm LP bulk.
FD-SOI Transistors
Mixed Signal Features
In terms of process variability, we
experience tighter process corners
and less random mismatch in FD-
SOI than in competing processes at
the same lithography node. The ben-
efits become obvious in terms of a
simpler design process and shorter
design cycle, leading to improved
yield or improved performance at
given yield. Figure 10 illustrates this
for the VT parameter.
Reduced VT from body biasing
has also excellent i mpl ic at ion s
for CMOS switches (pass-gates), as
depicted in Figure 11 [5], result-
ing in an unprecedented quality of
analog switches. One can observe
the exceptional flat behavior of the
CMOS switch resistance in the case
of the FD-SOI integration using body
Typ
Fast
Slow
Typ
Fast
1E–7 1E–6 1E–5
Gate Length (m)
biasing, its absolute value being much
lower than the one in bulk. We expe-
rience here compounding benefits:
a smaller resistance yields a smaller
switch with a more compact layout,
hence with lower parasitics, which
finally gives an even smaller switch.
This feature is key for high-per­
formance data converters and other
switched-capacitor circuits.
Lower junction capacitances as
those experienced in FD-SOI make
a substantial difference in high-speed
circuits. They permit drastic reduc-
tion of self-loading in gain stages and
a significant reduction of switches
self-loading. This yields a two-fold
benefit: not only incremental improve­­
ments, but mostly they allow the
de­­­­­­signer to use circuit architectures
that would be infeasible/inefficient
in bulk technologies [6].

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 23

FD-SOI Transistors Features Varia- depend on the body biasing variation Analog/RF FD-SOI Specific
tion with the Body Biasing Tuning for an operation at a given constant Tuning and Trimming Techniques
FD-SOI semiconductor physics pre- current. Figures 12 and 13 illustrate Using Body Biasing
dicts that the main design transistor’s this aspect by providing measure- By taking advantage of the unique
parameters (such as Gm or fT ) do not ment curves for different devices. very wide-band body biasing voltage
range available in FD-SOI technolo-
gies, the state of the art proposes
1,400 several unique techniques bringing
wn = 1 u uncontested chip energy saving and
Switch Resistance (Ω)

1,200
revisiting system performances.
1,000 wp = 2 u A first method consists of gen-
28LP CMOS
800 943 Ω erating and mak ing available on
28FDSOI noBB
28FDSOI FBB±1.8 V chip BB voltages (a pair, for NMOS
600 and PMOS transistors) variable over
400 288 Ω time and process, voltage, and tem-
25 Ω perature (PV T) variations. Start-
200
0 0.2 0.4 0.6 0.8 1 ing from these voltages, we can
Input Voltage (V) cancel system-level PVT variations
by continuously tuning transis-
Figure 11: An LVT CMOS switch resistance variation with respect to input voltage, compar- tors’ respective VT . Several design
ing a 28-nm FD-SOI CMOS and a 28-nm LP bulk. examples can be found in [7]–[9].
As well, reconfiguration at circuit/
block/system depending on appli-
cation operation mode is enabled.
[S]

1.5
Design examples can be found in
[10] (at block level) and [9] (at sys-
gm Meas [E–3]

1.0 tem level). Finally, we can propose

new energy-efficient design tech-
niques for tunable blocks via body
0.5
tie, as in [11].
A second method consists of gen-
0 erating and making available on chip
1E–7 1E–6 1E–5 1E–4 1E–3
fixed body bias voltages. In such
id [LOG] [log A]
cases, the design can efficiently
gm Versus id (W = 1e–06 L = 3e–08 MODEL = Ivtnfet)
enable operation at ULV (0.5 V) and in the
Figure 12: A 28-nm FD-SOI LVT CMOS 1 µm/30 nm transistor measured Gm for different same time increase circuit speed.
drain currents, where Vbody varies from 0 to 2 V, Vds = 1.1 V. Some design examples are [12] and

30 400
[Hz]
[S]

300
20
fT [E + 9]
gm [E + 3]

200

10
100

0 0
0 5 10 15 20 25 0.0 0.2 0.4 0.6 0.8 1.0
id [E–3] [A] id [E–3] [A]
gm Versus id (vds = 1 WFING = 1e–06 fT Versus id (vds = 1 WFING = 1e–06
L = 3e–08 MODEL = Ivtnfet_rf) L = 3e–08 MODEL = Ivtnfet_rf)
(a) (b)

Figure 13: A 28-nm FD-SOI LVT CMOS 1 µmX20 fingers/30 nm transistor* measured Gm and fT for different drain currents, where Vbody
varies from 0 to 2 V, Vds = 1.1 V. ()*: intrinsic device (FEOL plus Metal 1).

24 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

[13]. Another advantageous feature
is the minimization of the switches’
on-resistance value and excursion
for energy efficient and high speed
switched-capacitors circuits (e.g.,
analog-to-digital conver­ters), as in
[14] and [5].
For the first method, on-chip
body bias generators have to be
carefully considered for integra-
tion in terms of power consumption,
ripple, and noise on the generated
control voltages. They may have a
constant over time operation or duty
cycled, depending on the system
op­­eration. And finally, they can ad­­­
dress smaller or larger islands of
transistors to be tuned or control­
led. This consists of a new category
of embedded power management
blocks. For the second method, the
fixed positive BB voltage can come
from a supply (1 or 1.8 V), and the
negative one can be easily gener-
ated by a simple charge-pump volt-
age generator.
A short overview of planar UTBB FD-SOI
technologies has been presented, focusing on
analog, RF, mmW, and mixed signal designs.
Example of Body Bias Fully Enabled
RF-Mixed Signal ULV SoC in
28-nm FD-SOI
The design of an Impulse Radio-
Ultra Wide Band (IR-UWB) Binary
Phase-Shift Keying (BPSK) and Bi­­
nary Position Modulation (BPM) RF
transmitter operated at 0.55 V, IEEE
802.15.4a compliant, is an excel-
lent example of a ULV RF-mixed-
signal SoC implementation in 28-nm
FD-SOI [9]. This chip serves three
emission channels from a single
reconfigurable signal path (3.5, 4.0,
and 4.5 GHz, respectively) and has
configurable data rates of 0.11, 0.85,
1.7, 6.81, and 27.24 Mb/s, respec-
tively. The RF and mixed-signal SoC
features the digital and RF transmit
path and the frequency synthetizer
but also the DC-DC converter (1.2
to 0.55 V) and the body bias gen-
erator (up to ±1.8 V, for variable out-
put voltage).
This design takes full advantage
of FD-SOI body biasing techniques
for tuning, trimming, and loop con-
trol, and this is done at the circuit
and system levels in very elegant
ways (Figure 14). First of all, an ex­­
tremely low power phase-locked
loop-free architecture with aggres-
sive duty cycling is proposed, com-
pensated by on-chip adaptive FBB
for local oscillator tuning and trim-
ming upon the requested trans-
mit frequency. The Digital Power
Amplifier features programmable

31.25 MHz Crystal Clock

Packet-Level
BPSK Pulse-Level
Baseband Symbol-Level Baseband
at 32.25 MHz BPM at 31.25 MHz Baseband LFSR
at 500 MHZ

ENABLE_LO
Packet Encoder CLK_500 MHz
ENABLE_PA

Duty-Cycled Frequency Synthesis at 3.5–4.5 GHz

CALIB

LO Programmable
Frequency Calibration Frequency Divider
Packet Buffer ÷7, ÷8, ÷9
128 B

Power Amplifier Power Amplifier

Synthesized
Full-Custom

and Pulse Shaping

SPI I/F Enabling at 3.5–4.5 GHZ
and
Pulse
Shaping RF_OUT

Pulse Shaping and

Config. Registers

Figure 14: A RF-mixed signal SoC for ULV WSN transmitter (from [9]).

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 25

pulse shaping enabled by body bias
control, meeting U.S. Federal Com-
munications Commission spectral
regulation for all emission chan-
nels. Last but not least, high-speed
and ULV digital implementation
enabled by FBB further improves
energy efficiency.
By summing up these new system
and design features in the 28-nm FD-
SOI 1 mm2 SoC, record energy effi-
ciency improving by 16 the state of
the art has been demonstrated (trans-
mitter only: 14pJ/bit, SoC: 24pJ/bit).
The transmitter is compliant with all
the standard requirements.
Conclusions
A short overview of planar UTBB
FD-SOI technologies has been pre-
sented, focusing on analog, RF,
mmW, and mixed signal designs.
One of the major arguments of such
technologies is the unprecedent­
­e d very wide VT tuning range of
~250 mV for FD-SOI versus ~10 mV
for bulk, in addition to very good
analog intrinsic performances. The
new “tuning knob” obtained from the
body ties brings no parasitic effects
on the signal path, which is a very
attractive feature in the case of tun-
ing schemes, as the feedback signal
is under the BOX of the transistors.
The excellent analog performances
and the contained variability enable
very high-performance energy ef­­
ficient solutions. For RF to mmW
design, atop the previously men-
tioned aspects, excellent fT , fmax are
available, enabled by deep submi-
cron technology features. The BEOL
in an FD-SOI environment permits
the implementation of high-perfor-
mance passive devices, despite the
very dense very-large-scale integra-
tion constraints. For mixed-signal
and high-speed designs, the major
key parameters are improved vari-
ability, remarkable CMOS switches
performance, and reduced para-
sitic capacitances.
The 28-nm FD-SOI CMOS technol-
ogy enables flexible and energy-
efficient SoC solutions for multiple
types of applications in the field
26 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
of Internet of Things (IoT) and 5G
ecosystem [15]. It also permits the
implementation of efficient revisited
tuning and trimming strategies for
process and temperature compensa-
tion, as well as for circuit reconfigu-
ration. And finally, FD-SOI permits
to propose simpler circuits based
on body bias tuned inverters that
revisit state-of-the-art evolution.
References
[1] N. Planes, O.Weber, V. Barral, S. Haendler,
D. Noblet, D. Croain,M. Bocat, P. Sassou-
las, X. Federspiel, A. Cros, A. Bajolet, E.
Richard, B. Dumont, P. Perreau, D. Petit,
D. Golanski, C. Fenouillet-Beranger, N.
Guillot, M. Rafik, V. Huard, S. Puget, X.
Montagner, M.-A. Jaud, O.Rozeau, O. Sax-
od, F. Wacquant, F. Monsieur, D. Barge, L.
Pinzelli, M. Mellier, F. Boeuf, F. Arnaud,
and M. Haond, “28 nm FD-SOI technol-
ogy platform for high-speed low-voltage
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[2] F. Arnaud, N. Planes, O. Weber, V. Bar-
ral, S. Haendler, P. Flatresse, and F. Nyer,
“Switching energy efficiency optimiza-
tion for advanced CPU thanks to UTBB
technology,” in Proc. IEEE Int. Electron De-
vices Meeting Dig., 2012, pp. 3.2.1–3.2.4.
[3] D. Jacquet, F. Hasbani, P. Flatresse, R. Wil-
son, F. Arnaud, G. Cesana, T. Di Gilio, C.
Lecocq, T. Roy, A. Chhabra, C. Grover, O.
Minez, J. Uginet, G. Durieu, C. Adobati, D.
Casalotto, F. Nyer, P. Menut, A. Cathelin, I.
Vongsavady, and P. Magarshack, “A 3 GHz
dual core processor ARM cortex TM -A9 in
28 nm UTBB FD-SOI CMOS with ultra-wide
voltage range and energy efficiency opti-
mization,” IEEE J. Solid-State Circuits, vol.
49, no. 4, pp 812–826, 2014.
[4] R. Guillaume, F. Rivet, A. Cathelin, and Y.
Deval, “Energy efficient distributed-os-
cillators at 134 and 202 GHz with phase-
noise optimization through body-bias
control in 28 nm CMOS FD-SOI technol-
ogy,” in Proc. IEEE Radio Frequency Inte-
grated Circuits Symp., 2017.
[5] A. Kumar, C. Debnath, P. N. Singh, V. Bha-
tia, S. Chaudhary, V. Jain, S. L. Tual, and R.
Malik, “A 0.065 mm2 19.8 mW single chan-
nel calibration-free 12b 600 MS/s ADC in
28 nm UTBB FD-SOI using FBB,” in Proc.
42nd European Solid-State Circuits Conf.,
2016, pp. 165–168.
[6] B. Murmann, “Mixed-signal design in FD-
SOI,” Leti-Days, Grenoble, June 2015.
[7] J. Lechevallier, R. Struiksma, H. Sherry, A.
Cathelin, E. Klumperink, and B. Nauta, “A
forward-body-bias tuned 450 MHz Gm-C
3rd-order low-pass filter in 28 nm UTBB
FD-SOI with >1 dBVp IIP3 over a 0.7-to-
1V supply,” in Proc. IEEE Int. Solid-State
­Circuits Conf. Dig. Tech. Papers, 2015, pp.
1–3.
[8] D. Danilovic, V. Milovanovic, A. Cathelin,
A. Vladimirescu, and B. Nikolic, “Low-
power inductorless RF receiver front-end
with IIP2 calibration through body bias
control in 28 nm UTBB FD-SOI,” in Proc.
IEEE Radio Frequency Integrated Circuits
Symp., 2016, pp. 87–90.
[9] G. de Streel, F. Stas, T. Gurné, F. Durant,
C. Frenkel, A. Cathelin, and D. Bol, “Sleep-
Talker: A ULV 802.15.4a IR-UWB transmit-
ter SoC in 28-nm FD-SOI achieving 14 pJ/b
at 27 Mb/s with channel selection based
on adaptive FBB and digitally program-
mable pulse shaping,” IEEE J. Solid-State
Circuits, no. 99, pp. 1–15, 2017.
[10] A. Larie, E. Kerhervé, B. Martineau, L.
Vogt, and D. Belot, “A 60 GHz 28 nm UTBB
FD-SOI CMOS reconfigurable power am-
plifier with 21% PAE, 18.2 dBm P1dB and
74 mW PDC,” in Proc. IEEE Int. Solid-State
Circuits Conf. Dig. Tech. Papers, 2015,
pp. 1–3.
[11] I. Sourikopoulos, A. Frappé, A. Cathelin,
L. Clavier, and A. Kaiser, “A digital de-
lay line with coarse/fine tuning through
gate/body biasing in 28 nm FD-SOI,” in
Proc. Conf. 42nd European Solid-State Cir-
cuits Conf., 2016, pp. 145–148.
[12] L. Fanori, A. Mahmoud, T. Mattsson, P. Ca-
puta, S. Rämö, and P. Andreani, “A 2.8-to-
5.8 GHz harmonic VCO in a 28 nm UTBB
FD-SOI CMOS process,” in Proc. IEEE Radio
Frequency Integrated Circuits Symp., 2015,
pp. 195–198.
[13] A. Lahiri and N. Gupta, “A 0.0175mm 2
600 µW 32 kHz input 307 MHz output PLL
with 190 psrms jitter in 28 nm FD-SOI,”
in Proc. 42nd European Solid-State Circuits
Conf., 2016, pp. 339–342.
[14] S. Le Tual, P. N. Singh, C. Curis, and P. Dau-
triche, “A 20 GHz-BW 6b 10 GS/s 32 mW
time-interleaved SAR ADC with Master
T&H in 28 nm UTBB FD-SOI technology,”
Proc. IEEE Int. Solid-State Circuits Conf.
Dig. Tech. Papers, 2014, pp. 382–383.
[15] B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R.
Jevtić, B. Keller, S. Bailey, M. Blagojević,
P.-F. Chiu, H.-P. Le, P.-H. Chen, N. Sutardja,
R. Avizienis, A. Waterman, B. Richards,
P. Flatresse, E. Alon, K. Asanović, and B.
Nikolić, “A RISC-V vector processor with
simultaneous-switching switched-capac-
itor DC–DC converters in 28 nm FD-SOI,”
IEEE J. Solid-State Circuits, vol. 51, no. 4,
pp. 930–942, 2016.
About the Author
Andreia Cathelin (andreia.cathelin
@st.com) has been with STMicro-
electronics, Crolles, France, since
1998, where she is now a fellow in
Technology R&D. Her major fields of
interest are in the area of RF/mmW/
THz systems for communications
and imaging, where she is leading
advanced design R&D projects. She
is serving on several IEEE conference
committees, including the Execu-
tive Committee of the International
Solid-State Circuits Conference and
Steering Committee chair of Euro-
pean Solid State Circuits Confer-
ence–European Solid State Devices
Conference (ESSCIRC-ESSDERC). She
received the electrical engineering
degree in 1994 from ISEN Lille and
the Ph.D. degree in 1998 as well as a
habilitation à diriger des recherches
in 2013, both from the University of
Lille, France.

 Digital Circuits for
Mobile Computing
Optimizing power performance
and innovation opportunities
T
oday’s mobile phone
has millions of times
more computing po­­­
wer than all of the
NASA computers that
put two astronauts on the moon. It is
through the progress made by Moore’s
law and the ability of software engi­
neers to take advantage of increased
computing to create new applications
that help our daily life be more effi­
cient. There is enough computational
power available that we are at the prec­
ipice of intelligent robots, autonomous
vehicles, and machine learning for a
smart home/environment/life.
Putting all of this computing into
an increasingly smaller form fac­
tor and limited energy sources cre­
ates innovation opportunity for our
Digital Object Identifier 10.1109/MSSC.2017.2745819
Date of publication: 16 November 2017
1943-0582/17©2017IEEE
Alice Wang and Hugh Mair
industry. We can clock processors at
5+ GHz but cannot use them because
of the thermal limits of users putting
the de­­­­­­v ice in their pockets. We can
drive more performance through
multicore and parallelism but the
user prefers to charge their mobile
once per day. To ship millions of ICs
per day means adding margin for reli­
ability, resulting in wasting power
and performance. New innovation is
needed to provide the optimized power
and performance of these devices.
This tutorial will discuss circuit
innovation opportunities for mobile
computing by being adaptive to the
environment, driving the state of the
art in power delivery and clocking and
then focusing on foundation intellec­
tual property (IP) such as standard cell
library and embedded memory design
for mobile computing. Finally, we will
look into how to co-optimize up the
food chain from circuits to systems
IEEE SOLID-STATE CIRCUITS MAGAZINE
image licensed by ingram publishing
and beyond for the best solution in
mobile computing.
What’s Going on Around Me?
(Adaptive Techniques for
Power/Performance Optimization)
On a given wafer there is a large varia­
tion of maximum central processing
unit (CPU) speed for each IC due to
process variations. However, at the
product level, we need to guarantee a
minimum CPU speed with which each
IC will work over all possible tem­
peratures and variations due to the
environment that the processor could
encounter. In the design closure stage,
we will sign off at the worst condition
of silicon speed, voltage, temperatu­re,
and device lifetime, but in reality
this is also the worst case and causes
power overhead to achieve the speed
target. Therefore, by employing adap­
tive techniques, we can reduce this
power overhead by operating the IC
fa l l 2 0 17 27
 Computing Subsystem (HW)

DET DET
CPU0 CPU1 CPU0 CPU1

TEMP TEMP

Performance-Driven CPU Cluster Energy-Efficient CPU Cluster Vdd

Shader0 Shader1 System

PTP PMIC
Power
Controller
Manager
Power-Efficient GPU Cluster

80 45

70 40
PTP: +23% GHz PTP: –30% Power (avg)

Power Savings (Typ) (%)

35
60
30
50
25
40
20
30
15
20
10
10 5
0 GHz 0
90 100 110 120 130 140 Fast Typ Slow
(%) Silicon Speed

Figure 1: PTP detectors enable adaptive voltage scaling for optimal power/performance of the CPU complex.

the CPU to detect when operating

30 130 conditions have changed. This ad­­
aptive technology allows the device
25 110 to use available voltage margin to
Average Power Saving (%)

boost performance or lower power

Temperature (C)

20 90 With Temperature consumption when possible. A small

Monitoring controller monitors the detector data
15 70 Without Temperature dynamically trimming the device for
Monitoring
dc voltage bias, aging, and tempe­
10 50 Temperature
rature adjustment as the device is
exposed to different conditions. The
5 30
result is 20% megahertz boost or 30%
power savings depending on the sys­
0 10
Time tem-on-chip (SoC) operating condition.
Figure 2 shows the power savings over
Figure 2: Temperature monitors allow for additional power savings across time as the time due to the temperature sensors.
temperature fluctuates. Adjusting the voltage with tempera­
ture can save an additional 5–10% of
at the lowest voltage that still guaran­ staying below the thermal budget power. The technology is IP agnostic,
tees speed and quality [1]. of the chip, as shown in Figure 1. thus all processors and digital logic
The goal of adaptive techniques Power, thermal, and performance in the SoC are able to gain a similar
is to maximize performance while (PTP) detectors are distributed within power savings benefit.

28 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Using back-gate biasing is another
way to adaptively adjust the silicon
for process variation. Forward-body
bias (FBB) increases the performance
of slow silicon by applying 400 mV to
the body of the P-type metal–oxide–
semiconductor transistors in a 28-nm
process node CPU. The body-bias
switch is integrated into the distrib­
uted power switch to ensure even
distribution of all relevant voltages
across the CPU (Figure 3). A careful
power sequence of the voltage rails
is needed to prevent short circuit
current between supplies [2].
Adaptive power allocation is used
to maximize CPU performance within
the currently allocated power bud­
get by instantly reallocating power
from low-activity CPUs to high-activ­
ity ones, thus avoiding performance
throttling on high-activity CPUs. In
scenarios where the cumulative power
of all CPUs exceeds the total clus­
ter budget, automatic clock gating
is introduced as a temporary coun­
termeasure and is achieved by clock
PDB
RET
BIASEN
RVDD
VNWBIAS
PDB
RET
BIASEN
No FBB
Power-Up
Figure 3: A hybrid switch to support body biasing and power sequencing required to prevent short circuit current between supplies.
The goal of adaptive techniques is to maximize
performance while staying below the thermal
budget of the chip.
dithering. When clock dithering is
active, a secondary process adjusts
the on-chip phase-locked loop fre­­
quency and off-chip dc-to-dc converter
voltage to a more energy-efficient oper­
ating point to maximize performance.
The control loop goes between clock
dithering and voltage/frequency ad­­
justment to achieve maximum per­
formance, which occurs when total
power consumption is close to the
power budget. A two-times perfor­­man­­
­c e improvement is observed when
power is limited to 25% of normal
operating power [3].
Sipping Power Through a Straw
(Power Delivery Network)
Powering the processors is also a
very important consideration, and
the design of the power delivery
RVDD
Transition
Transition
FBB
Active Retention
network (PDN) impacts the perfor­
mance capability. Because a very
robust PDN is also associated with
a higher cost, there is a very care­
ful tradeoff between the cost of the
PDN solution versus the performance
achievable by the processor that needs
to be considered.
During run time, the processors
switch between light and heav y
work loads continuously, c ­ ausing
voltage droop in the PDN. These
droops diminish the voltage margin
available and compromise CPU oper­
ating speed. To minimize voltage
droops, a remote-sensing technol­
ogy is employed [1]. A feedback line
using a printed circuit board (PCB)
trace to a location closest to CPU
power pins provides actual CPU volt­
ages to the power management IC
VNWBIAS
VDDB
VDD
ORET
OBIASEN
OPDB
Transition
Transition
Transition
Transition
No FBB
Active Retention Active
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 29
 (PMIC). The voltage delivered from
Die PCB Cap the PMIC continuously compensates
VCC
PKG
Pkg Cap PMIC for any losses, thus power deliv­
PCB ered to the processors is guarante­
­ed to within a known error margin.
The feedback mechanism is con­
VCC VCC tinuous, and thus power supplied
Max Max is constantly tracked and adjusted
during operation. Figure 4 shows
oscilloscope plots before and after
VCC VCC
remote sense are enabled achi­e v­i ng
Min Min
18 mV(dc), 11 mV(ac) power sup­­­­­p ­­­
Remote Sensing Off Remote Sensing On
­ly compensation.
Increasing CPU clock frequency,
Figure 4: Oscilloscope plots of voltage measured at the probe location on the PCB closest
to the IC before and after remote sense (VCCmax and VCCmin are the high and low voltage
core count, and lower supply voltage
specs, respectively). stresses both the power distribution
network and the dc/dc converter from
current load transients. Aggressive
clock gating in a high-performance
Without Clock Gating Second Droop: 118 mV CPU creates an additional challenge:
idle CPUs enter an idle state in which
dynamic power is completely elimi­
nated, and consequently the dc/dc
converter switches from pulsewidth
mode (PWM) to pulse-frequency mode
(PFM). When this event is detected, the
CPU clocks are automatically switched
With Clock Gating Second Droop: 64 mV to a lower clock frequency, thus pre­
venting a large step in supply current
and minimizing the dI/dt transient.
Without this feature enabled, the
maximum VDD droops 118 mV, as
the dc/dc converter transitions from
PWM to PFM. When enabled, the droop
is reduced to 64 mV due to lower ini­
tial current demand, achieving a 45%
Figure 5: A silicon measurement of WFI ➔ max-power showing droop reduction from
118 to 64 mV of the second droop through aggressive clock gating when the transient is reduction in VDD droop (Figure 5) [2].
detected. WFI: wait for interrupt. Another droop reduction scheme uses
a 1.8 V supply to deliver momentary
boosting current and charge to the
CPU (Figure 6). A bank of five clocked
2.5-GHz Clock 1.8 V Supply on-die voltage sensors continuously
Bandgap
State monitors the internal power supply
Voltage
Voltage voltage, using an externally supplied
Monitor Array
2.5-GHz clock. State-based logic, in
VMon0 turn, monitors the five sensor outputs
Reference VMon1 Power
Digital 12 and, upon detecting a droop occur­
Voltage VMon2 Switch
Control
Generator VMon3 Activation Array rence, sends a 12-b activation code to
VMon4 Code the integrated bank of power switches.
Response Time <1 ns This switch activation effectively can­­
DIE_SENSE_VDD cels the resonant droop before it
CPU
Cluster reaches the minimum voltage, thus
DIE_SENSE_VSS
improving VMIN. For effective droop
reduction, the entire process from
detection to prevention must occur in
Figure 6: Droop mitigation design with response time <1 ns. under 1 ns [4].

30 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

“I Feel the Need, the Need for
Speed” (Clocking) CPU Bounding Box
A structured clock mesh is often used in
Fishbone “Spine”
high clock rate CPUs to minimize clock
Fishbone “Ribs”
insertion delay and end point skew. In
Tap-Point Buffer
the CPU, a “fishbone” structure is con­
First-Level Clock Gate
structed to propagate the main clock
to a grid of 229 tap-points across the
CPU. As shown in Figure 7, the fishbone
utilizes a distributed driver column
tied to horizontal spines; no additional
vertical strapping is used, eliminating
half of the traditional mesh capacitance.
The resistance-capacitance (RC) of each
spine is constrained by using tap-point
buffers at each grid point, minimizing
capacitance and RC va­­­­r iation of each
spine. Traditional clock tree synthe­ Figure 7: A fishbone clock physical structure.
sis (CTS) is used to connect from the
tap-points to lower-level gates, allowing
skew to be used as required [2]. 200
A direct connection to a large nu­­m­­ HD HC
ber of clock tree elements maximizes 64 b/bl 32 b/bl Cell: HD
the potential benefit of a mesh style of 175 Cell: HD Bits/BL: 32
clock grid. To achieve this, the first SVT LVT Bits/BL: 64 Periphery: LVT
level of functional clock gates instan­ Periphery: LVT Area: 119.3%
Area: 100%
Reactive Power (%)

tiated in the register transfer level are

logically combined into the second
level. This increases the number of
first-level clock loads from three to
3,009, which are immediately behind
229 tap-point buffers. The overall CPU
clock insertion delay is reduced by 35%
while maintaining parity power with
traditional CTS in a 28-nm CPU design.
How to Lay a Good Foundation
­(Standard Cell and Embedded SRAM)
Once the CPU specification and micro­
architecture are defined, the next
step is to implement them into digital
logic and implement the place and
route. One knob for additional tuning
of the power/performance of the CPU
is the standard cells and embedded
memory (SRAM) design to achieve the
power/performance target.
To meet CPU L1 cache SRAM perfor­
mance requirements while minimiz­
ing the power consumption, three
design options were explored: 1) high-
density (HD) versus high-current (HC)
bit cell, 2) 64 b/bit line (bbl) versus
32 bbl, and standard threshold volt­
age (VT) versus low VT periphery
transistors. Figure 8 shows the design
150
Cell: HD
125
Bits/BL: 64
Periphery: SVT
Area: 100%
100
Power Too
Low
75
90
Figure 8: An L1 SRAM’s PPA tradeoff resulting in L1 CPU SRAM using HD with 32 bbl.
option tradeoff. LVT was eliminated
due to the impact of leakage power.
HD with 64 bbl does not meet perfor­
mance, so HD with 32 bbl or HC with
64 bbl is considered; compared to HD
64 bbl, these have +19.3%, and +18.6%
more area, respectively. As can be seen,
the HD 32 bbl has a 3% higher perfor­
mance and 9% lower power than the HC
64 bbl and, hence, is the topology used
for CPU L1 caches for optimal power,
performance, and area/cost [2].
Clock gating is a commonly used
methodology to reduce power. However,
Power Too High
Cell: HC
Bits/BL: 64
Periphery: SVT
Area: 118.6%
Cell: HD
Bits/BL: 32
Periphery: SVT
Area: 119.3%
95 100 105 110 115
Relative Performance (%)
clock-gating paths are frequent­­ly speed
bottlenecks in high-speed CPU imple­
mentations. A high-speed clock-gating
cell, shown in Figure 9, is devised to
replace the traditional clock-gating cells
(four inverter delays) in timing-critical
paths. The new cells offer data-to-output
timing of only two inverter delays [1].
One of the significant challenges
to logic performance in advanced
process technology pertains to the
midend-of-line (MEOL) and higher re­
sistance between transistors and in­
terconnects as the technology scales

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 31

 counterparts. Area impact from the
FF larger double-source cells is managed
FF
ECK FF by restricting their use to only the most
EN
CG critical timing paths.
CK
VDD VDD
CK
Up the Food Chain (Circuit ➔
TE CK1
CK
CK1 TE
CK1 ­System ➔ Software ➔ Humanities?)
In any system the power/performan­
EN
ECK ­ce tradeoffs made at higher levels can
CK1
EN ECK make or break any improvements
CKN TE made at the lower levels. For exam­
TE CKN ple, if many low-power knobs made
VSS VSS available at the circuit level are not
correctly used at the system or soft­
Traditional Clock Gating Cell High-Speed Clock Gating Cell
ware level, then the power overhead
at the higher level can not be opti­
Figure 9: The EN to ECK critical path in the clock gate is optimized from four gates to two
mized away by circuit innovations.
gates. EN: enable; ECK: enable CK.
Therefore cross optimizations from
circuits upward are vitally important
to the end product.
2 One such example is in the CPU
MEOL
Connections FO4 Delay software model utilizing a heteroge­
3
1
(ps) neous multiprocessor (HMP) archi­
Standard 2x INV 9.1 tecture. In mobile platforms, there
Xtor Source
4 is a wide range of demand for high
5 Double-Source 2x INV 8.6
Frequency Benefit 5.5%
performance in burst modes, sustain­
able performance in thermally limited
FO4 Delay at 0.75 V, TT, 25 °C
applications and low power modes
Input Output 2 1 for continuous usage. Thus a hetero­
geneous multiprocessor architecture
that includes both high-performance
4 and low-power CPUs is adopted to fit
3 5
all the power/performance profiles
needed. Since this architecture is dif­
ferent than previous computing mod­
els of multiprocessor systems, a new
software model was needed. The ini­
tial models imposed a limitation where
only one CPU type can be active at a
time. For a truly heterogeneous expe­
rience, new HMP software allows the
application access to all of the proces­
sors in the asymmetric CPU subsystem
Figure 10: A schematic and layout of a double-source inverter to reduce the MEOL resis-
tance and improve speed. simultaneously. While inherently supe­
rior to the previous models, the HMP
to a smaller dimension [4]. To miti­ across the source and drain from the performance remains highly depen­
gate this impact, a new standard cell source of the active transistors to the dent on the quality of the heteroge­
topology was created in a 10-nm pro­ respective power rail. neous scheduler embedded in the SoC
cess node. As shown in Figure 10, an Since these additional transistors solution. An advanced scheduler algo­
example topology of a 2× inverter, ad­ have gate/drain/source shorted, they rithm, combined with the asymmetric
ditional transistors are placed to the do not add to device leakage or input CPU architecture and an adaptive
left and right of the active transistors loading. This technique is applied to thermal and interactive power man­
to reduce their source resistance. The inverters, buffers, and commonly used agement system, maximize both per­
lowered source resistance and result­ combinational cells. The double-source formance and energy efficiency [1].
ing performance benefit is achieved cells are over 5% faster and 18% lar­­ An important input to the hetero­
by using an MEOL connection to short ger on average than conventional geneous scheduler is the CPU power

32 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE


250
+40% Power-Efficiency
Improvement Versus HP
Power/Performance (%)
200
150
100
+44% Power-Efficiency
Improvement Versus LP
50
0 100
Single-Threaded Performance (%)
Figure 11: CPU power-efficiency curves showing for three CPU types the single-threaded
performance versus the power.
efficiency curves to allow the sched­
uler to make important CPU tradeoffs.
The curves in Figure 11 show the CPU
single-threaded performance versus
the power per CPU as a function of per­
formance. If the HMP architecture can
provide different CPUs, then the soft­
ware can choose the CPU that provides
the lowest possible power for that
given performance requirement [4].
As the system and software become
optimized to minimize power/perfor­
mance for a given application, per­
haps the next optimizations will take
place upward at the humanities level,
where the human aspect of comput­
ing might be brought in. New comput­
ing models such as deep learning and
brain-inspired computing will help
us to further improve the user expe­
rience and power efficiency of the
devices we all rely on in our every day.
The future is extremely bright and
the opportunity is rich in the area of
mobile computing!
Acknowledgments
Many thanks to all of the worldwide
engineering teams at MediaTek who
contributed their blood, sweat, and
tears to this innovative work and deep
appreciation to the management at
MediaTek to support new and excit­
ing technology to be introduced to
our products.
HP-Cluster
LP-Cluster
ULP-Cluster
200 300 400
References
[1] A. Wang, T.-Y. Lin, S. Ouyang, W.-H. Huang,
J. Wang, S.-H. Chang, S.-P. Chen, C.-H. Hu,
J. C. Tai, K.-S. Tan, M.-N. Tsou, M.-H. Lee,
G. Gammie, C.-W. Yang, C.-C. Yang, Y.-C.
Chou, S.-H. Lin, W. Kuo, C.-J. Chung, L.-K.
Yong, C.-W. Wang, K. H. Dia, C.-H. Chien,
Y.-M. Tsao, N. Kumar S., R. Lagerquist,
C.-C. Chen, and U. Ko1 “Heterogeneous
multi-processing quad-core CPS and du­
al-GPU design for optimal performance,
power, and thermal tradeoffs in a 28nm
mobile application processor,” in Proc. Int.
Solid-State Circuits Conf. Dig., 2014, pp.
180–181.
[2] H. Mair, G. Gammie, A. Wang, S. Gururaja­
rao, I. Lin, H. C. Chen, W. Kuo, A. Rajago­
palan, W.-Z. Ge, R. Lagerquist, S. Rahman,
C. J. Chung, S. Wang, L.-K. Wong, Y.-C.
Zhuang, K. Li, J. Wang, M. Chau, Y. Liu, D.
Dia, M. Peng, and U. Ko “A highly integrat­
ed smartphone SoC featuring a 2.5GHz
octa-core CPU with advanced high-per­
formance and low-power techniques,” in
Proc. Int. Solid-State Circuits Conf. Dig.,
2015, pp. 425–426.
[3] H. T. Mair, G. Gammie, A. Wang, R. Lager­
quist, C. J. Chung, S. Gururajarao, P. Kao,
A. Rajagopalan, A. Saha, A. Jain, E. Wang,
S. Ouyang, H. Wen, A. Thippana, H.-C.
Chen, S. Rahman, M. Chau, A. Varma, B.
Flachs, M. Peng, A. Tsai, V. Lin, U. Fu, W.
Kuo, L.-K. Yong, C. Peng, L. Shieh, J. Wu,
and U. Ko, “A 20nm 2.5GHz ultra-low-
power tri-cluster CPU subsystem with
adaptive power allocation for optimal
mobile SoC performance,” in Proc. Int.
Solid-State Circuits Conf. Dig., 2016.
pp. 76–77.
[4] H. Mair, E. Wang, A. Wang, P. Kao, Y. Tsai,
S. Gururajarao, R. Lagerquist, J. Son, G.
Gammie, G. Lin, A. Thippana, K. Li, M.
Rahman, W. Kuo, D. Yen, Y.-C. Zhuang, U.
Fu, H.-W. Wang, M. Peng, C.-Y. Wu, T. Do­
sluoglu, A. Gelman, D. Dia, G. Gurumur­
thy, T. Hsieh, W. X. Lin, R. Tzeng, J. Wu,
C. H. Wang, and U. Ko, “A 10nm FinFET
2.8GHz tri-gear deca-core CPU complex
with optimized power-delivery network
for mobile SoC performance,” in Proc.
Int. Solid-State Circuits Conf. Dig., 2017,
pp. 56–57.
IEEE SOLID-STATE CIRCUITS MAGAZINE
About the Authors
Alice Wang (alice.wang@mediatek
.com) received her bachelor’s, mas­
ter’s, and Ph.D. degrees in electrical
engineering and computer science
from the Massachusetts Institute of
Technology, in 1997, 1998, and 2004,
respectively. She wrote the paper “A
180-mV Subthreshold FFT Proces­
sor Using a Minimum Energy Design
Methodology” with Prof. Anantha
Chandrakasan, which inspired a new
research field in ultra-low voltage
technology. After her Ph.D., she spent
eight years at Texas Instruments and
six years at MediaTek developing
low-power circuit and system tech­
nology for mobile baseband applica­
tion processors and radios. Her work
on low-power technology has been
showcased in more than 30 IEEE pub­
lications, and she has coauthored two
books. She is a Senior Member of the
IEEE. Currently, she is an assistant
general manager in high-performance
processor technology at MediaTek.
She has served on the International
Solid-State Circuit Conference Techni­
cal Program Committee for more than
ten years and been a guest editor of
IEEE Journal of Solid-State Circuits. She
was elected to the Advisory Commit­
tee for the IEEE Solid-State Circuits
Committee (2017–2019) and heads up
the IEEE Solid-State Circuit Society
Women in Circuits Committee.
Hugh Mair graduated from Glasgow
University with a degree in electrical
and electronics engineering in 1990
and joined the mixed-signal design
group of Texas Instruments, Dallas.
His work has focused on high-speed,
low-power mixed-signal and digital
circuit design, including high-rate/
long-reach SERDES, low-power SRAM,
and power management for advanced
CMOS. He has authored/coauthored
19 papers and invented/coinvented
more than 50 patents. Currently, he
is an assistant general manager in
high-performance processor technol­
ogy at MediaTek.

fa l l 2 0 17 33
 Alison Burdett

Low-Power
Wireless Systems
for Hospital
Patient Monitoring
The challenges and solutions
Footage Firm, Inc.
for emerging application areas

W
hile mobile,
wireless con­
n e c t iv it y is
per vasive in
most areas of
business and social activities, the
use of wireless technology in the
field of medical devices is not as
widespread. In this heavily regulated
industry, wireless communication is
often seen as an extra risk that, for
some applications, can be unaccept­
able. But the benefits that wireless
connectivity can bring to medical
devices is being recognized, lead­
Digital Object Identifier 10.1109/MSSC.2017.2745718
Date of publication: 16 November 2017
ing to the development of a new ge­­
neration of connected products for
patient benefit. This article discusses
some of the challenges in the im­­
plementation of low-power wireless
connectivity for hospital patient mon­
itoring, and describes solutions for
two emerging application areas: the
early detection of patient deteriora­
tion on general care wards and real-
time patient monitoring in intensive
care units.
Hospital Patient Monitoring
Vital-sign monitoring is a fundamen­
tal component of hospital patient
care. A patient’s heart rate, respi­
ration rate, temperature, and blood
pressure are essential in identify­
ing clinical deterioration, and these
parameters must be measured and
recorded accurately. The existing stan­
dard of care in most hospitals is
continuous monitoring in high-depen­
dency and intensive care areas, and
intermittent spot-check monitoring
on general wards. Patients in inten­
sive care units (ICUs) are suffering
life-threatening conditions and
can deteriorate very quickly, thus
their vital signs are monitored con­
tinually and in real time by attach­
ing the patients to bedside monitors
using multiple wires and cables.
Although patients in ICUs are immo­
bile and being tethered to the bed

34 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

by wires and cables may not appear
to be a problem, in practice, this
“cable clutter” causes a number of
problems. Inadequate cleaning of
cables can lead to cross-infection, the
large number of cables can make it
difficult to access the patient to pro­
vide care, and cables can become eas­
ily disconnected, leading to loss of
signal or false readings.
Wired monitoring is not appro­
priate for the majority of patients on
general wards who are encouraged
to be mobile as part of their rehabili­
tation. These patients are monitored
by nursing staff performing regular
observation rounds at a frequency
dictated by hospital procedure and
patient status, typically once every
4–8 h. Between these observation
rounds, some patients are at risk of
deterioration and can suffer unan­
ticipated adverse events. Recent re­­
ports have highlighted that many
patients do deteriorate between
manual observation rounds, result­
ing in significant illness and even
death, which might have been averted
had the deterioration been identified
earlier [1], [2]. However, there is a limit
to the frequency with which vital
signs can practicably and affordably
be measured by the nursing staff.
Electronic vital-sign measurement
could provide a solution, provided
that such devices did not impact
negatively on nursing workflow or
patient mobility.
One area where wireless patient
monitoring has become part of rou­
tine clinical practice is on telemetry
wards. In these areas, patients are typ­
ically being treated for cardio-respira­
tory disorders, and so a continuous
measurement of patients’ heart rates
and echocardiograms (ECGs) allows
clinicians to closely track their recov­
ery. Telemetry systems require a rela­
tively bulky transmitter to be worn
by the patient (typically in a pouch
worn on the shoulder or around the
neck) that transmits their physiologi­
cal data to dedicated base stations
within the telemetry ward and then
onto dedicated screens monitored by
specialist clinical staff.
These systems must be of a fairly
high power to achieve a good communi­
cation range from the base station and
also due to the relatively high volume of
data being streamed. Existing systems
are typically implemented either using
custom radio-frequency (RF) protocols
operating in dedicated hospital telem­
etry frequency bands (wireless medi­
cal telemetry system frequencies) or
are based on modifications of existing
communication protocols such as Digi­
tal Enhanced Cordless Telecommuni­
cations. While telemetry monitoring is
well established, it is not suitable for
either of the patient groups discussed
previously. For ICU patients, the wire­
less telemetry link performance does
not meet the necessary reliability and
latency requirements needed by this
application. For general care applica­
tions, telemetry is too bulky, costly,
and, if used on all general care patients,
would provide an overload of real-time
data that the nursing staff would not
have the capability to process.
Wireless Medical Monitoring
Wireless connectivity potentially
offers a solution for monitoring ICU
and general care patients. For ICU
patients, replacing many of the cables
with wireless connectivity would
greatly improve workflow and usabil­
ity for nursing staff, while also reduc­
ing infection risk. For general care
patients, the wireless measurement
and transmission of vital signs could
provide notification of ­ physiological
deterioration many hours before
the next set of manual observations
would have been due, allowing for
timely intervention. However, the per­
formance requirements of the wire­
less link in these two applications are
quite different.
For monitoring general care pa­­
tients, a very “lightweight” telemetry
solution would be appropriate that
simply transmits a new set of vitals
readings at a measurement rate much
higher i.e., every few minutes, than the
current 4-h observations. The patient-
worn device should be small and un­­
obtrusive, ideally disposable to avoid
cross-infection issues, with a battery
IEEE SOLID-STATE CIRCUITS MAGAZINE
life suitable to last the duration of an
average in-patient stay (about three to
seven days).
For ICU patients, the volume of
data is higher since typically a 12–15
lead ECG is measured in real time,
but the key issue here is the latency
from skin to screen, which needs to be
lower than 250 ms. In an ICU situation,
the patient is immobile and so the
wireless connection can be a simple
point-to-point link from the patient to
bedside monitor. Table 1 summarizes
the requirements of the wireless com­
munication link for these two patient
monitoring scenarios.
Performance Requirements
for Wireless Medical Devices
To correctly define and design a wire­
less system for hospital patient moni­
toring, it is important to understand
the regulatory requirements when
deploying wireless technology in
medical devices. In 2013, the U.S. Food
and Drug Administration (FDA) pub­
lished a guidance document, “Radio
Frequency Wireless Technology in
Medical Devices” [3]. This document
does not specify which technologies
should be used and does not pre­
scribe specific ways of operating but
instead discusses key considerations
that must be addressed and assessed
for risk when incorporating wireless
technology in medical devices. It spe­
cifically highlights
fa l l 2 0 17 35
 To correctly define and design a wireless States and 2483.5–2500 MHz in the
European Union] [4].
system for hospital patient monitoring, it
is important to understand the regulatory EMC of Wireless Technology
A wireless medical device must be
requirements when deploying wireless shown to continually function as in­­­­
technology in medical devices. tended in the presence of electro­
magnetic interference (EMI) from
other devices. For medical devices,
■■ the selection and performance of requirements for latency and pro­­­ EMC/EMI testing is moving away from
wireless technology b a bi l it y of loss of i n for m at ion being a prescribed set of tests and
■■ wireless quality of service (drop out). frequencies to an individual prod­
■■ wireless coexistence uct-based risk analysis and testing;
■■ the electromagnetic compatibility Wireless Coexistence that is, the manufacturer must declare
(EMC) of wireless technology This technology must meet the which frequencies his product is most
■■ the security of wireless signals monitoring performance require­ susceptible to and then show by test­
and data. ments in the presence of other ap­­ ing that the risks of this interference
While all these issues should be plications operating in the same have been mitigated.
considered when implementing any frequency spectrum. While interfer­ Regulations to be introduced in
wireless system, when designing a ence mitigation techniques such as 2019 require very high levels of RF
medical device, the burden is on the frequency hopping, forward error- immunity testing for proximity fields
manufacturer to show that the impact correction, and data redundancy from certain wireless transmitters
of any of these issues has been as­­ can be employed, if they are not that are expected to become com­
sessed and appropriate risk control implemented efficiently, these tech­ monplace in hospitals, namely global
measures are in place. niques can have a negative impact system for mobile communications/
on system latency and power con­ code division multiple access/long-
Selection and Performance sumption. Concerns about interfer­ term evolution (LTE) at 00.8–0.9 GHz
of Wireless Technology ence from other devices having a and Bluetooth/wireless local area
Whether a custom protocol or an negative impact on emerging wire­ network/RF identification/LTE at
existing standard, the wireless tech­ less patient monitoring systems has 2.4–2.57 GHz [5]. The EMI testing lev­
nology must be shown as suitable led U.S. and European regulatory els for medical devices are orders of
to meet the monitoring application bodies, the Federal Communications magnitude higher in field strength
requirements, e.g., throughput, num­ Commissions a nd the Europea n and closer in frequency than RF
ber of nodes supported, and com­ Telecommunications Standards immunity testing required for con­
munication range. In­stitute, to allocate dedicated fre­ sumer products, and it is very likely
quency spectrum for wearable wire­ that low-power RF communication
Wireless Quality of Service less monitoring devices [the Medical systems will face tough challenges
The chosen wireless technology must body area networks (MBANS) spec­ in meeting these requirements. For
meet the monitoring performance trum at 2360–2400 MHz in the United medical devices, this will neces­
sitate the careful system design and
mitigation at RF protocol and ap­­
Table 1. Wireless Patient Monitoring Application Requirements. p l i cation levels to ensure robust
op­eration in presence of these high-
General Care Patients ICU Patients
level interferers.
Date type Intermittent, processed vital signs Continuous, up to 12-lead ECG
Data rate Low, few b/s Up to 120 kb/s Security of Wireless Signals
Range ~30 m ~3 m and Data
Concern about the vulnerability of
Latency Few minutes < 250 ms
wireless medical devices to hacking
Number of nodes 100 s 1
led to the FDA issuing a new guidance
Network topology Ad-hoc star Point to point note in 2014, “Management of Cyber
Network priority Low High Security in Medical Devices” [6], which
Security High High highlighted t wo major concerns:
device hijacking and denial of ser­
Lifetime Few days Few days
vice. Device hijacking occurs when
Cost Low Medium an attacking device discovers the

36 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

communication protocol and is able
to listen in (eavesdrop) or exchange
data with the medical device to mod­
ify its behavior (man in the middle).
The solution for wireless devices is
to implement encryption and authen­
tication with secure key exchange.
But again such techniques can be chal­
lenging under low power constraints,
and further advances in this area
are needed. Under a denial of service
attack, the wireless medical device is
prevented from communicating either
by RF jamming or by flooding the net­
work with legitimate connection/data
transmission requests. Sophisticated
jamming techniques that exploit pro­­
tocol features or weaknesses can
be difficult to detect and have been
demonstrated for wireless medical
systems based on Wi-Fi and Zigbee
[8]. This presents an argument for
wireless medical monitoring devices
to use modified or custom protocols
that cannot be so easily understood
and replicated.
peak transceiver current consump­
tion of 5 mW was achieved to allow
additional overhead for vital-sign
sensing, digitization and process­
ing, and other system housekeeping
functions. The transceiver operates
in the 868/915 MHz ISM bands as
this gives a good tradeoff between
antenna size, range, and power con­
sumption [12] and allows a 30-m range
with a transmit power of ~100 uW.
Key to robust wireless system opera­
tion at very low power levels is a custom
hardware medium access control­
ler, implementing many of the key
SensiumVitals Patch
control functions in efficient low-power
hard­­­ware, including RF channel selec­
tion, channel access, link establish­­
ment, forward error correction, data
transfer, and sleep management [13]. In
many other transceivers, such func­
tions would be run at a higher layer
in software, allowing for greater flex­
ibility but with a resulting higher
power usage.
Since the development of this SoC
and system, Bluetooth low energy
(BTLE) has emerged as a popular low-
power wireless technology for wire­
less sensing and the Internet of
SensiumVitals Bridge

A Wireless Solution for

General Care Patient Monitoring
Low-power, wearable, and wireless
vital-sign monitors for the early de­­
tection of patient deterioration on
general wards are available on the MG Service Application
Server
market. One of the first such devices Monitoring
Gateway Service (Provides MAS
to become commercially available as and MG Services)
Controls Bridges
a CE-marked and FDA 510K-cleared Tracks Patches
medical device is the SensiumVi­ No Patient Names
MAS Service
tals system, as shown in Figure 1
Monitoring
[9]. At the heart of this system is a Application Service
single-use wearable wireless patch Database Links Patient ID
that is attached to the patient’s torso Server to Patch
Notifications Sent
and monitors heart rate, respiratory
Via E-mail
rate, and temperature and transmits User Interface
up ­­­d ated readings to wall-mounted (Using https)
bridges every 2 min.
This patch is based on a dedicated
system-on-chip (SoC) incorporating
a custom wireless protocol designed
to minimize power consumption and
cost and obtain a five-day battery life
from a single CR2032 coin cell [10].
To maximize battery life, the peak Connects to ADT Wireless Monitoring Notifications Sent to
current drain must be lower than and EMR System Application Screen Handheld Devices
10 mA [11]. In this SoC, peak current
consumption is dominated by the Figure 1: A wireless patient monitoring system for the early detection of deterioration on
transceiver when active, and thus a general care wards. (From [9], used with permission.)

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 37

Things [14]. While not yet able to Wireless Communication waveform and rate and photo ple­­
reach the very low peak power con­ for Intensive Care Monitoring thysmography waveform for blood
sumption (<10 mA) and extended Replacing wired cables in the ICU with oxygen saturation, gave an appli­
range (>10 m) of a custom protocol, wireless communication presents a cation data rate requirement of
wearable wireless patient monitoring significant challenge at low power 166 kb/s.
patches based on BTLE have started consumption, which, in this applica­ Equally important for ICU stream­
to become commercially available, tion, is also highly desirable to mini­ ing are the wireless QoS parameters
e.g., [15] and [16]. Moreover, recent mize size and maximize battery life. that need to be achieved. In addition
publications have demonstrated For ICU monitoring, the required to the data throughput of 166 kb/s,
BTLE transceivers operating at a data rate is dominated by the need the application requires a latency of
lower than 10 mA peak current, and to stream multiple leads ECG, which <250 ms with a reliability of <25 ms
while not yet commercially avail­ for a 15-lead ECG requires around data drop out in any 10-min period
able, such products can be expected 120 kb/s. Adding more capability (i.e., data loss lower than 50 parts
to appear on the market in the near to support the monitoring of other per million). Such a high reliability
future [17]–[19]. vital signs, including respirator y is usually achieved using strong for­
ward error correction combined with
message acknowledgment and retry.
But in our application, this would
300 lead to an unacceptable latency from
patient measurement to display.
250
Effective Througput (kb/s)

Therefore, we chose to implement

200 redundancy through frequency di­ ­
versity; with a data throughput of
150 166 kb/s per frequency channel
1 Packet/Event 6 Packet/Event and three time the frequency diver­
100 2 Packet/Event 7 Packet/Event sity, we require an application data
3 Packet/Event 8 Packet/Event throughput of 498 kb/s.
50 4 Packet/Event 9 Packet/Event
To select an appropriate wire­
5 Packet/Event 10 Packet/Event
0 less technology for this monitor­
ing application, simulations were
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
136
144
152
160
168
176
184
192
200
208
216
224
232
240
248
256

Packet Size (bytes) performed using models of many

different wireless protocols with the
Figure 2: Effective data throughput versus packet size for BTLE 4.2. potential to operate in the dedicated
MBANS frequency bands at ~2.4 GHz.
The protocols selected were BTLE
(1 Mb/s raw data rate), Bluetooth-
700 extended data rate (EDR) [differen­
Target Application Throughput (kb/s) 606 tial quadrature phase-shift keying
600 590
Effective Application Throughput (kb/s) (DQPSK) and 8PSK modes giving 2
528
498 498 498 498 498 498 498 and 3 Mb/s data rates, respectively],
500
450 and IEEE 802.15.6.
The IEEE 802.15.6 protocol was
400
developed specifically for the imple­
300 mentation of wireless body area
248 networks, including medical device
200 applications, and thus has many
148 security and reliability features built
100 in while still supporting low-power
44 implementation [20]. The 802.15.6
0 protocol was simulated for RATE3 and
BT4.0
(BER = 1E–3)

BT4.0
(BER = 1E–4)

BT4.2
(BER=1E–4)

802.15.6
RATE3

802.15.6
RATE4

BT-EDR
(2 Mb/s)

BT-EDR
(3 Mb/s)

RATE4 modes giving raw data rates of

600 kb/s and 1.2 Mb/s, respectively.
Simulations were carried out for each
protocol, varying the packet size from
the minimum to maximum allowed
Figure 3: The relative effective throughput of different wireless technologies. and adjusting the number of packets

38 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

needed for each payload event to be
transmitted, to determine the effective
throughput. From these plots, the
maximum effective throughput was
established, as shown in Figure 2 for
BTLE 4.2.
The results of this exercise are
shown in Figure 3. The better re­­
ceiver sensitivity and increased
maximum packet length for BTLE
introduced in BT 4.2 greatly improve
the maximum throughput compared
to BT 4.0 but still fall short of what
is needed for this application. (At the
beginning of 2017, BT 5 was released
with a doubling of the maximum
data rate to 2 Mb/s. This should theo­
retically allow a doubling of through­­
put to 496 kb/s, very close to the
application’s requirements.) The
802.15.6 MODE 4 protocol and both
BT-EDR modes are able to meet the
application data throughput re­ ­ at transmission at three ­d ifferent
quirements; however the typically
current consumption of a BT-EDR
(classic Bluetooth) device is typically
~30 mA, which would not allow for
use with a small coin cell. Therefore,
to support this application, we pro­
ceeded with a design based on IEEE
802.15.6.
To achieve the latency requirement,
samples must be acquired, received,
and displayed at the bedside device
fewer than 250 ms later, as illustrated
in Figure 4. Allowing three attempts
frequencies gives a frame length of
40 ms. If the data is successfully trans­­
mitted in the first frame (a block
acknowledgement is received), the
transceiver can sleep for the next

120 ms

Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Sensor

Tx Set 1 Tx Set 2 Tx Set 3 Tx Set 4 Node
Rx Set 1 Rx Set 2 Rx Set 3 Rx Set 4 Hub

< 250 ms

Tx Set 1–1 Tx Set 1–2 Tx Set 1–3

40 ms

ECG SPO2

Figure 4: A transmission frame structure to meet quality of service demands.

0.14
0.12
0.1
Probability

0.08
0.06
0.04
0.02
0
0 10 20 30 40 50
Packets in Error 1.00E–05

8.00E–06
Probability

6.00E–06

4.00E–06

2.00E–06

0.00E+00
25 30 35
Packets in Error

Figure 5: Transmission link reliability.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 39

two frames until the next data set is
ready. However if the sensor fails to
transmit its data, there are two fur­
ther attempts to transmit before the
packet needs to be dropped since new
data is available.
The data payload was divided
into 15 packets; with three times
the redundancy, we have the oppor­
tunity to transmit 45 packets, of
which only 15 need to be received
successfully. Running a simulation
of link reliability using a model of
the 802.15.6 protocol and assum­
ing a bit error rate of 1E-3 gives the
results shown in Figure 5. The total
probability of dropping more than
30 packets is lower than 2E-6, and
this is well within our reliability tar­
get of 50 E-6.
To validate this application in sili­
con, we implemented a custom SoC
in 65-nm CMOS with a peak power
consumption of <15 mW in transmit
mode and <10 mW in receive mode;
for further details, see [21]. Although
this work currently remains a re­­
search project, it illustrates the pos­
sibility of deploying low-power and
high-reliability links in demanding
wireless medical monitoring appli­
cations through the close coupling
of protocol design and low-power
hardware implementation.
Conclusions
Although the medical device industry
is slow to replace wired by wireless
connectivity, the convenience and
other benefits that wireless can bring
means that new applications for wire­
less patient monitoring are starting
to emerge. Since the development of
low-power standards is mainly driven
by consumer and other large markets,
it is inevitable that such standards
do not currently prioritize the high
reliability and security requirements
needed by medical devices. However,
as the market keeps developing, we
anticipate that the needs currently
addressed by custom or niche wire­
less protocols and SoCs may begin
to be met by widely available off-the-
shelf devices.
40 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Acknowledgments
The author acknowledges the input
of all colleagues at Toumaz and
Sensium Healthcare, in particular
Okundu Omeni for work on system
simulations.
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[18] M. Babaie, F.-W. Kuo, H.-N. R. Chen, L.-C.
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[19] Y.-H. Liu, X. Huang, M. Vidojkovic, A. Ba,
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standard/802.15.6-2012.html
[21] A. C. W. Wong, M. Dawkins, G. Devita, N.
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About the Author
Alison Burdett (alison.burdett@
sensium-healthcare.com) has more
than 30 years of experience in elec­
tronic engineering and semiconduc­
tor design, particularly in the field of
ultra-low power wireless communi­
cation for medical applications. She
joined Toumaz in 2001 as technical
director and became chief technical
officer in 2006. In 2016, the health-
care business unit of Toumaz, Sen­
sium Healthcare, became part of
The Surgical Group, and she joined
Sensium, where she serves as chief
scientific officer. Prior to joining Tou­­­
maz, she spent time in industry as
an IC designer and in academia as a
senior lecturer in analog IC design
at Imperial College London. She is a
chartered engineer, a fellow of the
Institute of Engineering and Tech­
nology, and a Senior Member of the
IEEE. She is chair of the Technical
Program Committee for the Interna­
tional Solid-State Circuits Confer­
ence. She is a member of the U.K.
Engineering and Physical Sciences
Research Council Strategic Advisory
Network, and a visiting researcher
at the Institute of Biomedical Engi­
neering, Imperial College.

footage firm, inc.
Ingrid Verbauwhede

Security Adds an Extra

Dimension to IC Design
Future IC design must focus on security in addition
to low power and energy

I
nternet of Things
(IoT) devices, in­­
clud ing med ic a l
impla nts, s e n s o r
nodes, wea rables,
automotive elements, and more, are
typically immersed in the environ­
ment and extremely resource con­­st­
rai­ned. They operate using batteries
Digital Object Identifier 10.1109/MSSC.2017.2745799
Date of publication: 16 November 2017
or scavenged energy: thus, optimiz­
ing for power and/or energy is of
the utmost importance. However, to
protect privacy, authenticate data or
sources of information, and provide
resistance to physical manipulation,
we must add security, cryptographic
capabilities, and other countermea­
sures to IC design.
The implementation of these cry­
ptographic a lgo r it h m s and pro­
tocols must be compact and energy
efficient but, at the same time, re­­
sistant to physical attacks and leak­
age of sensitive information from
the device during computations.
Adding countermeasures increases
the overall cost and energy budget
and adds an extra design dimen­
sion. Attackers will always go for
t he weakest link. Thus, security
needs to be considered at every de­­
sign step and requires its own test­
ing strategies.

1943-0582/17©2017IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 41

 The implementation of cryptographic
algorithms and protocols must be compact
and energy efficient but resistant to physical
attacks and leakage of sensitive information.
This short article was motivated
by a recognition of the need for secu­
rity in embedded devices. It begins
with the attacker model, discusses
associated design and test methods,
and offers several illustrative ex­­
amples. The main focus is on digital
hardware implementations for cryp­
tographic algorithms, protocols, and
security devices; the article does not
address hardware solutions to pro­
tect against software attacks.
It is difficult to measure security
as there are no commonly agreed
upon units for such measurement.
Therefore, security is based on an
attacker model and evaluated against
the assumptions made in this at­­
tacker model. For typical digital cir­
cuit design, we distinguish among
the following broad categories: the
black box model (used mostly in the
past), the gray box model of current
designs, and the immersed model of
the future. Also, white box cryptog­
raphy exists.
Black Box Attacker Model: The Past
Modern cryptography began in the
1970s with the first U.S. standard
for symmetric key encryption, the
Data Encryption Standard (DES);
the invention of public key cryp­
tog raphy; and the development
of the public key Rivest–Shamir–
FIGURE 1: An illustration of the black box attacker model, with the green dots representing
the devices’ roots of trust.
42 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
A d le man (RSA) algorithm. These
developments appeared in conjunc­
tion with novel electronic communi­
cation means and were spurred by
the electronics revolution.
The DES algorithm was developed
with efficient hardware implemen­
tation in mind. Indeed, it performs
poorly in software. Cryptography,
in this case, is applied to protect the
information flow between two com­
municating parties. For the attacker
model, we assume that the devices
owned by Alice and Bob (the two main
“characters” in every cryptographic
protocol) operate in black boxes, mean­
ing that only the cryptographic inputs
and outputs of the devices can be
observed by Eve, the attacker. This
is illustrated in Figure 1, where each
device has a root of trust, indicat­
­ed by the green dots. Examples are
computers and servers in computer
rooms or offices.
Typical attacks are performed on
the network connections between
devices, e.g., a local area network, the
Internet, or any wireless link between
devices. In the black box model,
Eve collects input/output pairs (i.e.,
plaintext/ciphertext pairs), which
she uses to guess the secret key. She
is also allowed to modify input data
or adaptively supply her own input
data. The security strength in this
model is based purely on the compu­
tational complexity of the underly­
ing cryptographic algorithms. If Eve
succeeds in guessing the key more
quickly than brute force (i.e., faster
than trying all possible keys), then
the cryptographic community consid­
ers the algorithm broken.
In this context, Moore’s law is im­ ­
portant for the algorithm designer.
Indeed, Moore’s law helps the attacker,
as it gives him/her more computa­
tional power for brute-forcing crypto­
graphic algorithms. The consequence
is that key lengths for cryptographic
algorithms keep growing. First, the
European network ECRYPT and later
the European Union Agency for Net­
work and Information Security pub­
lished documents regarding required
key lengths for near- and long-term
security [3]. For long-term security, the
suggested key lengths are 256 for
the symmetric key size, 512 for the
hash output size, 15,360 for the RSA
modulus size, and 512 for bit ellip­
tic curves.
As a result, the digital hardware
designer often has to design for very
large word lengths in combination with
unusual arithmetic. The most critical
component of secret key algorithms
such as DES or the Advanced Encryp­
tion Standard (AES) are the “substitu­
tion boxes,” or Sboxes. Special effort
is expended to make these either com­
pact or very fast [11]. The most critical
components of public key algorithms
such as RSA or elliptic curve-based
cryptography rely on the implementa­
tion of finite-field arithmetic and, more
specifically exponentation algorithms
and finite-field multipliers. The focus
of digital hardware designers in the
black box context is thus efficiency:
small area, high throughput, low po­ ­
wer, and low energy. In this sense,
the IC design process is no different
from optimizations in other fields,
such as image, video, or communica­
tions applications.
Testing of black box security cir­
cuits focuses, therefore, on functional
correctness, as well as on measur­
ing throughput, power, and energy.
Care must be taken to ensure that
sensitive registers (such as key reg­
isters) a re not included on sca n
chains or that these scan chains are
disconnected before shipment. For­
tunately, because cryptographic algo­
rithms aim at maximum confusion
and diffusion, fault coverage is typi­
cally very high for testing crypto­
graphic algorithms.
Gray Box Attacker Model:
The ­Present
Today, electronic devices and compu­
tations are more dispersed and distri­
buted. In the IoT context, we assume
that electronics are in the hands of
the user, e.g., mobile devices, smart
cards, game consoles, and other gad­
gets. Sensor nodes are distributed in
the environment, and medical devices
are implanted into our bodies. Elec­
tronics are everywhere in our cars:
to monitor sensors and drive actua­
tors, provide an entertainment sys­
tem, enable autonomous driving, and
more. Security, reliability, and safety
are of the utmost importance.
In this context, we assume an at­­
tacker model in which the attacker
has access to both the communication
channel and the devices themselves,
as illustrated in Figure 2. Instead of
using only input/output plaintext/
ciphertext pairs, the attacker obtains
extra information by observing (a pas­
sive attack) or manipulating (an active
attack) one IC while it is performing
the calculations on the embedded
device. This extra side-channel infor­
mation can take many forms.
For typical digital circuit design, we distinguish
among the black box model (used mostly in the
past), the gray box model of current designs,
and the immersed model of the future.
Public key algorithms, such as RSA or
elliptic-curve public key schemes, typi­
cally scan the key bits in a bit-serial
fashion. A sequential implementation
that contains key-dependent if-then-
else structures will leak information:
when the if branch takes a different
execution time than the else branch,
the difference in execution time again
leaks information concerning the key.
Therefore, huge effort is spent to make
sure that a cryptographic implementa­
tion in hardware or software runs in
constant time.
For instance, it is crucial that finite-
state machines consume exactly the
same amount of cycles, independently
of the data being processed. Unfor­
tunately, most hardware optimiza­
tion and synthesis tools (and also
software compilers) will remove the
dummy code or logic that was added
to make a circuit or implementation
constant-time, because it is consid­
ered redundant or dead code. Hence,
there is a need for tools that check
or create constant-time implementa­
tions [7]. Note that timing attacks
can also be executed remotely; thus,
they are also a concern for cloud and
server implementations.
Side-Channel Attacks:
Simple and ­Differential
Similarly, data-dependent variations
in power consumption or electro­
magnetic (EM) radiation can reveal
sensitive data. Collectively, these
are called side- channel attacks.
These require that the attacker is in
close proximity to the device and can
monitor the power consumption or
pick up the EM radiation. Such attacks
are passive: they monitor the device
without disturbing its normal opera­
tion. The danger of passive attacks
is that the device itself might not
be aware that it is being monitored,
which is further evidence of the need
to develop circuits that can detect
observation [4].
Simple power attacks (SPAs) rely
on one or, perhaps, a few power or
EM measurements to obtain the secret
key. Template attacks are one exam­
ple of an SPA; here, a template of
the device under attack is available.
Creating the template could take a
huge number of measurements, but
the attack on the actual device might
take only one or, at most, a few such
measurements. (The term SPA is
somewhat misleading because, in

Timing Attacks
In a timing attack, the attacker will
observe differences in execution time,
depending on the values of the key or
other sensitive data. Cache attacks are
a well-known example. They are effec­
tive for table-based implementations
of the Sboxes of symmetric key algo­
rithms: if data in the cache depend on
the key, then timing differences leak
information [1].
In reaction, native AES instructions
were added to high-end x86 proces­
sors: these both improve performance FIGURE 2: An example of the gray box attacker model, with the green dot representing the
and run in data-independent time [10]. device’s root of trust.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 43

 In the future, we expect that the capabilities
of attackers will improve and that we will
evolve from a gray testing box model toward
an immersed model.
general, SPA attacks are not that sim­
ple to mount.)
Differential power attacks (DPAs)
and EM attacks typically require mul­
tiple (in the hundreds or, sometimes,
millions) power or EM traces to guess
cryptographic secrets. In a typical
setup, the attacker creates a model
for the power consumption behav­
ior of the device. For example, the
attacker assumes that the power con­
sumption is related to the Hamming
distance between current and previ­
ous data values stored in flip-flops
or registers. Indeed, this closely
corresponds to the dy­­namic power
consumption profile in standard
complementary–metal-oxide-semi­
conductor designs, where power is
consumed only when the state of the
flip-flop changes. Up until now, we
have typically ignored leakage cur­
rent and other noisy effects because
dynamic power is still dominant.
DPA attacks are quite robust and re­­
silient to noise: noisy uncorrelated
FIGURE 3: A graphic depicting an immersed model.
44 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
effects can be reduced by increasing
the number of measurements.
To protect symmetric key algori­
thms such as AES, two main classes of
countermeasures have been devel­
oped. One is a set of circuit styles
that make the switching activity of
gates independent of the data being
processed: it is based on dynamic
differential logic styles [12]. Masking
techniques are a second major class
of countermeasures: these are based
on randomly splitting sensitive data
into multiple shares and obtaining
a subset of shares that do not dis­
close those actual data [8]. Public key
algorithms are usually protected at
the algorithm level (by adding ran­
domness to the calculations) with
techniques such as key or scalar
blinding or the use of projective
coordinates, making it difficult for
the attacker to obtain multiple power
or EM measurements.
In practice, side-channel information
is used to reduce the computational
complexity of a brute-force attack.
As an example, the popular correla­
tion power attack reduces the effort
of attacking an AES key from 2128
to the size of the AES Sbox, 28 (the
input data to the Sbox being cor­
related to the key). The attacker makes
256 possible Ha m m ing dist a nce
power models and looks for the model
that results in a ma ximum corre­
lation w it h t he me a sur ed power
t r a c e s . This is then repeated for
every key byte. Hence, a correlation
attack is a divide-and-conquer attack:
it combines side-channel informa­
tion with brute-forcing 256 possible
key byte guesses.
Fault Attacks
Fault attacks are an active attack
but not necessarily an invasive one.
Faults can be triggered by playing
with the power supply, introducing
clock glitches, freezing or heating
the device (typically also applied
to random number generators), or
any other means that triggers faulty
results [5].
IC designers have developed many
test strategies to address random
faults in ICs, including those based
on scan chains, built-in-self-tests,
and more. Many countermeasures,
such as adding redundancy, could be
reused to detect fault attacks. There
are, however, two main differenc­
­e s between an attacker aiming to
inject faults and a designer testing for
random faults. The first is the simple
fact that knowing whether a fault
occurred (yes or no) could in itself
disclose sensitive information and so
needs to be avoided [2]. The second
is that the designer must avoid hav­
ing key registers and other sensitive
data sitting on the scan chains. This
would otherwise provide a very nice
back door.
Side Note on
White Box ­Cryptography
White box cryptography is used in
the context of secure software dis­
tribution, where a cr y ptog r aph ic
algorithm with an associated key
is conver ted into a key-specific,
tamper-resistant piece of software.
It is used when no hardware crypto­
graphic module or trusted element
is available. Mathematically, most
white box schemes are broken, but
specific applications such as digital
rights management still make use of
white box cryptography. However,
this topic will not be further dis­
cussed here.
Future Attacker Models
In the future, we expect that the capa­
bilities of attackers will improve and
that we will evolve from a gray box
testing model toward an immersed
model, as shown in Figure. 3. The IoT
is a complex system with lightweight,
resource-constrained devices at the
edge. These devices communicate
with each other and with mobile por­
table devices, such as phones, per­
sonal computers, lap tops, etc. At the
center, cloud computing and serv­
ers provide extraordinary compute
power to all.
So far, in the gray box model, we
assume that an attacker observes one
device or one communication link at
a time. In the immersed model, we
assume that multiple nodes supported
by malicious servers or botnets can
conspire to attack one poor IoT device.
Thus, besides providing protection
with strong cryptographic algorithms
and strong physical defenses against
side-channel attacks, we also need
strong cryptographic protocols that
protect a system even if individual
nodes fail. In this context, we see
many interesting research challenges.
Because electronics are immersed
into the environment, we need strong
roots of trust. These roots of trust will
be in hardware, they need to be mini­
mal in size, and there should be some
explicit proof that one can trust them.
Included in this set will be physi­
cally unclonable functions to derive
device-specific keys and embedded
true-random-number generators that
can resist a wide range of attacks. Sec­
ond, there is a need to develop more
hardware circuits to support software
security and provide, for instance,
In the immersed model, we assume that
multiple nodes supported by malicious servers
or botnets can conspire to attack one poor
IoT device.
control flow integrity, software integ­
rity, remote attestation, and so on. A
third challenge is the development of
quantum computers. Major classes of
current public key algorithms based
on RSA and elliptic curves will be
broken if/when quantum computers
appear. Mathematicians are develop­
ing a new generation of algorithms,
but the challenge for the digital hard­
ware designer is to implement them,
including all current software, side-
channel, and fault attack counter­
measures. Also lacking currently is
support for security by design meth­
ods and tools.
To conclude, the future of secure
digital hardware design will require
a complex interaction among digital
circuit design, computer arithmetic,
cryptography, and evolving technol­
ogy. And, while in the past, we wor­
ried only about energy and power
minimization, we now have to face
the additional constraint that our cir­
cuits need to be resistant to a wide
range of attacks.
References
[1] D. J. Bernstein. (2004). Cache-timing at­
tacks on AES. [Online]. Available: https://
cr.yp.to/papers.html#cachetiming
[2] D. Boneh, R. DeMillo, and R. Lipton, “On
the importance of eliminating errors in
cryptographic computations,” J. Cryptol.,
vol. 14, no. 2, pp. 101–119, Mar. 2001.
[3] N. P. Smart, Ed. ENISA. (2014). Algorithms,
key size and parameters report. [Online].
Available: https://www.enisa.europa.eu/
publications/algorithms-key-size-and-
parameters-report-2014
[4] N. Homma, Y. Hayashi, N. Miura, D. Fu­
jimoto, M. Nagata, and T. Aoki, “Design
methodology and validity verification
for a reactive countermeasure against
em attacks,” J. Cryptol., vol. 30, no. 2, pp.
373–391, 2017.
[5] D. Karaklajic, J. Schmidt, and I. Verbau­
whede, “Hardware designer’s guide to
fault attacks,” IEEE Trans. Very Large Scale
Integration Syst., vol. 21, no. 12, pp. 2295–
2306, 2013.
[6] P. Maene, J. Goetzfried, R. de Clercq, T.
Mueller, F. Freiling, and I. Verbauwhede,
“Hardware-based trusted computing archi­
tectures for isolation and attestation,” IEEE
Trans. Computers, 2017, to be published.
IEEE SOLID-STATE CIRCUITS MAGAZINE
[7] O. Reparaz, J. Balasch, and I. Verbau­
whede, “Dude, is my code constant time?”
in Proc. Conf. Design, Automation and Test
in Europe, 2017, p. 6.
[8] O. Reparaz, B. Bilgin, B. Gierlichs, S. Niko­
va, and I. Verbauwhede, “Consolidating
masking schemes,” in Advances in Cryp-
tology, Lecture Notes in Computer Science,
vol. 9215, R. Gennaro, and M. J. Robshaw,
Eds. New York: Springer-Verlag, 2015, pp.
764–783.
[9] V. Rozic, O. Reparaz, and I. Verbauwhede,
“A 5.1μJ per point-multiplication elliptic
curve cryptographic processor,” Int. J.
Circuit Theory Applicat. vol. 45, no. 2, pp.
170–187, 2016.
[10] S. Gueron. (2012, Aug. 2). Intel advanced
encryption standard (Intel AES) instruc­
tions set—Rev 3.01. [Online]. Available:
https://soft ware.intel.com/en-us/ar­
ticles/intel-advanced-encryption-stan­
dard-aes-instructions-set
[11] S. Satpathy, S. Mathew, V. Suresh, M.
Anders, H. Kaul, A. Agarwal, S. Hsu,
G. K. Chen, and R. Krishnamurthy,
“250mV-950mV 1.1Tbps/W double-affine
mapped Sbox based composite-field
SMS4 encrypt/decrypt accelerator in
14nm tri-gate CMOS,” in Proc. VLSI Cir-
cuits, 2016.
[12] K. Tiri and I. Verbauwhede, “A digital de­
sign flow for secure integrated circuits,”
IEEE Trans. Computer-Aided Design In-
tegrated Circuits Syst., vol. 25, no. 7, pp.
1197–1208, 2006.
About the Author
Ingrid Verbauwhede (ingrid.verbau­
whede@esat.kuleuven.be) heads the
embedded systems and hardware
team of the research group COSIC at
the KU Leuven in Belgium. She is an
adjunct professor in the Electrical
Engineering Department at the Uni­
versity of California, Los Angeles,
and a member of the Royal Academy
of Belgium for Science and the Arts.
She received a European Research
Council Advanced grant in 2016, as
well as the 2017 IEEE Computer Soci­
ety Technical Achievement Award.
She is a pioneer in the field of effi­
cient and secure implementations of
cryptographic algorithms in embed­
ded contexts on application-specific
ICs, field-programmable gate arrays,
and embedded software.

fa l l 2 0 17 45
 Vivienne Sze

Designing Hardware
for Machine Learning
The important role played by circuit designers

M
achine learn­ing is becoming in­­
creasingly important in this era
of big data. It enables us to extract
meaningful information from the
overwhelming amount of data being
generated and collected every day. This information can be
used to analyze and understand the data to identify trends
(e.g., surveillance and portable/wearable electronics) or to
take immediate action (e.g., robotics/drones, self-driving
Digital Object Identifier 10.1109/MSSC.2017.2745798
Date of publication: 16 November 2017
cars, and smart Internet of Things). In many applications,
embedded processing near the sensor is preferred over the
cloud due to privacy or latency concerns or limitations in
the communication bandwidth. However, sensor devices
often have stringent constraints on energy consumption
and cost in addition to throughput and accuracy require­
ments. Circuit designers can play an important role in
addressing these challenges by developing energy-effi­
cient platforms to perform the necessary processing for
machine learning. In this article, we will give a short over­
view of the key concepts in machine learning, discuss
its challenges particularly in the embedded space, and

footage firm, INc.

46 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

highlight various opportunities where
circuit designers can help to address
these challenges.
Introduction
Machine learning is needed to extract
meaningful, and ideally actionab­
­le, information from the enormous
amount of data that is being generated
and collected every day. Given the
sheer volume of data, the high energy
cost of communication, and the often
limited communication bandwidth,
there is an increasing need to perform
the analysis locally near the sensor
rather than sending the raw data to
the cloud. Enabling machine learning
at the edge also addresses important
concerns related to privacy, latency,
and security. Accordingly, embedded
machine learning has shown to be
beneficial for many applications such
as those in the multimedia and medi­
cal fields.
For instance, computer vision is
a form of machine learning that
extracts information from images
and videos, which are arguably the
largest portion of big data as they
account for ove r 70 % of today ’s
Internet traffic [1]. In many appli­
cations (e.g., measuring wait times
We will give a short overview of the key
concepts in machine learning, discuss its
challenges particularly in the embedded
space, and highlight various opportunities
where circuit designers can help to address
these challenges.
in stores and traffic patterns), it is Another important application is
desirable to extract the meaning­ speech recognition, which enables
ful information from the video at seamless interaction with electronic
the image sensor rather than in the devices, such as smartphones. Speech
cloud to reduce the communication recognition is the first step before many
cost. For other applications such as other tasks such as machine translation
autonomous vehicles, drone naviga­ and natural language processing. Low-
tion, and robotics, local processing is power hardware for speech recognition
desired since the latency and security is explored in [3] and [4].
risk of relying on the cloud are too In the medical field, there is a clinical
high. However, video involves high- need to collect long-term data to help
dimensional data, which is compu­ detect/diagnose various diwseases
tationally expensive to process; thus, or monitor treatment. For instance,
low-cost hardware to analyze video the constant monitoring of electro­
is challenging yet critical to enabl­ ­ cardiogram or electroencephalogram
ing these applications. While there signals can identify cardiovascular
is a wide range of computer vision diseases or detect the onset of a sei­
tasks [2], in this article, we will focus zure for epilepsy patients, respec­
on image classification as a driv­ tively. In many cases, these devices
ing example, where the task is to are either wearable or implantable,
determine the class of the object in an and thus the energy consumption
image (Figure 1). must be kept to a minimum. The
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 47
 Machine learning is needed to extract
meaningful, and ideally actionable, information
from the overwhelming amount of data that is
being generated and collected every day.
use of embedded machine learning the task is performed on new data
to extract meaningful physiological through a process called inference.
signals and process them locally is Machine learning is particularly useful
explored in [5] and [6]. for applications where the data is dif­
ficult to model analytically.
Machine Learning Basics A typical machine learning pi­­
Machine learning is a form of artificial peline for inference can be broken
intelligence that can perform a task with­ dow n into two steps as shown in
out being specifically programmed. Figure 2: feature extraction and clas-
Instead, it learns from previous exam­ sification. Approaches such as deep
ples of the given task during a pro­ neural networks (DNN) blur the dis­
cess called training. After learning, tinction between these steps.
Dog (0.7)
Cat (0.1)
Machine
Learning Bike (0.02)
(Inference) Car (0.02)
Plane (0.02)
House (0.04)
FIGURE 1: An example of an image classification task. The machine learning platform takes
in an image and outputs the confidence scores for a predefined set of classes.
Image
Trained Weights (w )
Pixels Feature Features (x )
Extraction
Handcrafted Features
(e.g., HOG)
FIGURE 2: The inference pipeline.
48 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Feature Extraction
Feature extraction is used to transform
the raw data into meaningful represen­
tations for the given task. Tradition­
ally, feature extraction was designed
through a handcrafted process by ex­­­­­
perts in a given field. For instance, it
was observed that humans are sen­
sitive to edges (i.e., gradients) in an
image. As a result, many well-known
computer vision algorithms use image
gradient-based features such as histo­
gram of oriented gradients (HOG) [7]
and scale invariant feature transform
[8]. The challenge in designing these
features is to make them robust to varia­
tions in illumination and noise.
Classification
The output of feature extraction is
re­­presented by a vector (x in Fig­
ure 2), which is mapped to a score of
confidence using a classifier. Depend­
ing on the application, the score is
either compared to a threshold to deter­
mine if an object is present or com­
pared to the other scores to determine
the object class.
Techniques for classification in­ ­
clude linear methods such as support
vector machine (SVM) [9] and Softmax
and nonlinear methods such as ker­
nel-SVM [9] and Adaboost [10]. Many
of these classifiers compute the score
Classification Scores
(w Tx )
Scores Per Class
(Select Class Based
on Max or Threshold)
Learned Features
(e.g., DNN)
using a dot product of the features
(xv ) and a set of weights (w v ) (i.e.,
/ i i i As a result, machine learn­
w x ).
ing hardware research tends to focus
on reducing the cost of a multiply and
accum u late (MAC) operation.
Training involves learning these
weights from a dataset. Inference
in­­volves performing a given task us­­
ing the trained weights. In most cases,
training is done in the cloud, while infer­
ence can happen in the cloud or locally
on a device near the sensor. In latter
case, the trained weights are down­
loaded from the cloud and stored on
the device. Thus, the device needs to
be programmable in order to support
a reasonable range of tasks.
Deep Neural Networks
Rather than using handcrafted fea­
tures, the features can be directly
learned from the data, similar to
the weights in the classifier, such
that the entire system is trained end
to end. These learned features are
used in a popular form of machine
learning called called Deep Neu­
ral Networks (DNNs), also known
as deep learning [11]. DNNs deliver
higher accuracy than handcrafted
features, sometimes even better
than human-level accuracy, on a
variety of tasks by mapping inputs
to a high-dimensional represen­
tation; however, it comes at the cost
of high-computational complexity,
resulting in orders of magnitude
higher energy consumption than hand­
crafted approaches [12].
There are many forms of DNNs
(e.g., convolutional neural networks
and recurrent neural networks). For
computer vision applications, DNNs
are often composed of mu lt iple
con­volutional (CONV) layers [13] as
shown in Figure 3; each layer involves
the application of multiple high-
dimensional filters to the incoming
data. With each layer, a higher-level
abstraction of the input data, called
a fe at ur e m ap, i s extracted that
preserves essential yet unique in­­
formation. Modern DNNs are able
to achieve superior performance
by employing a very deep hierar­
chy of layers on the order of tens
to hundreds.
Modern DNNs: 5–1,000 Layers
Low-Level
CONV Features
Layer
Convolution Nonlinearity
×
FIGURE 3: DNNs are composed of several CONV layers followed by FC layers.
The output of the final CONV layer
is typically processed by fully con­
nected (FC) layers for classification.
In FC layers, the filter and input fea­
ture map are the same size so that
there is a unique weight for each input
feature value. In between CON V and
FC layers, additional functions can
be added, such as pooling and nor­
malization [14]. In addition, a nonlin­
ear function, such as a rectified linear
unit (ReLU) [15], is applied after each
CONV and FC layer. Overall, convo­
lutions account for over 90% of the
run time and energy consumption in
modern DNNs for computer vision.
Table 1 compares modern DNNs,
with a popular neural net from the
1990s, LeNet-5 [16]. Today’s DNNs
use more layers (i.e., deeper) and are
1–3 Layers
High-Level
CONV Features FC Classes
Layer Layer
Normalization Pooling

Table 1. A Summary of popular DNNs [16], [18]–[21]. Accuracy Is measured based on The top-Five errors on
ImageNet [22].

Metrics LeNet 5 AlexNet VGG-16 GoogLeNet (v1) ResNet-50

Accuracy n/a 16.4 7.4 6.7 5.3

CONV layers 2 5 16 21 49
Weights 2.6 thousand 2.3 million 14.7 million 6 million 23.5 million
MACs 283 thousand 6.66 billion 15.3 billion 1.43 billion 3.86 billion
FC layers 2 3 3 1 1
Weights 58 thousand 58.6 million 124 million 1 million 2 million
MACs 58 thousand 58.6 million 124 million 1 million 2 million
Total weights 60 thousand 61 million 138 million 7 million 25.5 million
Total MACs 341 thousand 724 million 15.5 billion 1.43 billion 3.9 billion

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 49

several orders of magnitude larger in the ImageNet data set [22] (Fig­ As previously discussed, the ac­ ­
in terms of compute and storage. A ure 4). Accordingly, LeNet-5, which curacy of the machine le a r n i ng
more detailed discussion on DNNs is designed for digit classification, algorithm should be measured for
can be found in [17]. requires much less storage and com­ a well-defined task on a sufficiently
pute than the larger DNNs in Table 1, large dataset (e.g., ImageNet). Energy
Impact of Difficulty of Task which are designed for the 1,000- consumption is often dominated by
on ­Complexity class image classification task. Thus, data movement as memory access
The difficulty of the task must be hardware platforms should only be consumes significantly more energy
considered when comparing differ­ compared when performing machine than computation [24]. This is par­
ent hardware platforms for machine learning tasks of similar difficulty ticularly challenging for machine
learning as the size of the classifier or and accuracy, ideally, the same task learning as the high-dimensional
network (i.e., number of weights) and with the same accuracy. representation and filters increase
the number of MACs tend to be larger the amount of data generated, and
for more difficult tasks and thus Challenges the programmability needed to sup­
require more energy. For instance, The key metrics for embedded machine port different applications, tasks,
the task of classifying handwritten learning are accuracy, energy con­ and networks means that the weights
digits from the MNIST dataset [23] sumption, throughput, and cost. The also need to be read and stored. In
is much simpler than classifying an challenge is to address all these re­
­ this article, we will discuss various
object into one of a 1,000 classes quirements concurrently. methods that reduce data movement
to minimize energy consumption.
The throughput is dictated by the
amount of computation, which also
MNIST ImageNet increases with the dimensionality of
the data. In this article, we will dis­
cuss various transforms that can be
applied to the data to reduce the num­
ber of required operations.
The cost is dictated by the amount
of storage required on the chip. In
this article, we will discuss various
methods to reduce storage costs such
FIGURE 4: The MNIST (ten classes, 60,000 training, and 10,000 testing) [23] versus Ima- that the area of the chip is reduced,
geNet (1,000 classes, 1.3 million training, and 100,000 testing) [22] dataset. while maintaining low off-chip mem­
ory bandwidth.
Currently, state-of-the-art DNNs
consume orders of magnitude higher
energy than other forms of embedded
Temporal Architecture Spatial Architecture
(SIMD/SIMT) (Data Flow Processing) processing (e.g., video compression)
[12]. We must exploit opportunities
Memory Hierarchy Memory Hierarchy
at multiple levels of hardware design
Register File to address all these challenges and
close this energy gap.
ALU ALU ALU ALU
ALU ALU ALU ALU
Opportunities in Architectures
The MAC operations in both the fea­
ALU ALU ALU ALU ALU ALU ALU ALU
ture extraction (CONV layers in a
DNN) and classification (for both
ALU ALU ALU ALU DNN and handcrafted features) can
ALU ALU ALU ALU be easily parallelized. Two com­
ALU ALU ALU ALU
mon highly parallel compute para­
digms that can be used are shown
ALU ALU ALU ALU in Figure 5.
Control

CPU and GPU Platforms

Central processing units (CPUs) and
FIGURE 5: Highly parallel compute paradigms with multiple ALUs. graphics processing units (GPUs)

50 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

use temporal architectures such as
SIMD or SIMT to perform the MACs
in parallel. All the arithmetic logic
units (ALUs) share the same control
and memory (register file). On these
platforms, all classifications are
represented by a matrix multiplica­
tion. The CONV layer in a DNN can
also be mapped to a matrix multi­
plication using the Toeplitz matrix.
Software libraries that optimize for
matrix multiplications can be used
to accelerate processing on CPUs
(e.g., OpenBLAS and Intel MKL) and
GPUs (e.g., cuBL A S and cuDNN).
The matr i x multiplications c a n
be further sped up by applying
transforms such as fast Fourier trans­­
form [25], [26] and Winograd [27]
to the data to reduce the number
of ­multiplications.
Specialized Hardware
Specialized hardware provides an
opportunity to optimize the data
movement (i.e., data flow) to mini­
mize accesses from the expensive
levels of the memory hierarchy and
maximize data reuse at the low-cost
levels of the memory hierarchy. Fig­
ure 6 shows the memory hierarchy of
the spatial architecture in Figure 5,
where each ALU processing element
(PE) has a local memory (register file)
on the order of several kilobytes and
a shared memory (global buffer) on
the order of several hundred k ilo ­
bytes. The global buffer communi­
cates with the off-chip memory (e.g.,
DRAM). Data movement is allowed
between the PEs using an on-chip net­
work to reduce accesses to the global
buffer and the off-chip memory.
The data flows of all three types
of data (feature map, filter weights,
and partial sums) affect energy con­
sumption. Various data flows have
been demonstrated in recent works
[28]–[39], which differ in terms of
the type of data that moves and the
type of data that remains station­
ary in the register file of the PE [40].
The row stationary data flow, which
considers the energy consumption
of all three data types, reduces the
energy consumption by 1.4× to 2.5×
The key metrics for embedded machine learning
are accuracy, energy consumption, throughput,
and cost.
compared to the other data flows for
the CONV layers [41].
Opportunities in Joint Algorithm
and Hardware Design
The machine learning algorithms
c a n b e m o d if ie d to m a ke t h e m
more hardware friendly by reducing
com­­putation, data movement, and
storage requirements, while main­
taining accuracy.
Reduce Precision
GPUs and CPUs commonly use a 32-b
floating point as the default repre­
sentation. For inference, it is possible
to use fixed point with reduced bit
width for energy and area savings,
and increased throughput, without
affecting accuracy.
For instance, for object detec­
tion using handcrafted HOG features,
only 11 bits are required per fea­
ture vector and only 5 bits per SVM
weight [42]. For DNN inference, recent
commercial hardware uses 8-b inte­
ger operations [43]. Custom hard­
ware can be used to exploit the fact
that the minimum bit widths varies
per layer for energy savings [44]
or increased throughput [45]. With
Global
DRAM
Buffer
0.5–1.0 kB RF
NoC: 200–1,000 PEs PE
100–500 kB Buffer
DRAM
FIGURE 6: Memory hierarchy and data movement energy for a spatial architecture [41].
IEEE SOLID-STATE CIRCUITS MAGAZINE
more significant changes to the net­
work, it is possible to reduce the bit
width of DNNs to 1-b at the cost of
reduced accuracy [46], [47].
Sparsity
Increasing sparsity in the data reduces
storage and computation cost. For
SVM classification, the weights can
be projected onto a basis such that
the resulting weights are sparse for a
2× reduction in number of multiplica­
tions [42]. For feature extraction, the
input image can be made sparse by
preprocessing for a 24% reduction in
power consumption [48].
For DNNs, the number of MACs and
weights can be reduced by re­­­moving
weights through a process called prun­
ing. This was first explored in [49]
where weights with minimal impact
on the output were removed. In [50],
pruning is applied to modern DNNs
by removing small weights. However,
removing weights does not necessar­
ily lead to lower energy. Accordingly,
in [51], weights are removed based
on an energy model [52] to directly
minimize en­­er­g y consumption.
Specialized hardware in [42] and
[53]–[55] exploits sparse weights for
PE PE
PE Fetch Data to Run
ALU
a MAC Here
Normalized Energy Cost
ALU 1× (Reference)
ALU 1×
ALU 2×
ALU 6×
ALU 200×
fa l l 2 0 17 51
 Recent work has also explored
the use of mixed-signal circuits to
WLDAC
Code reduce the computation cost of the
WL MAC. It was shown in [59] that per­
V1 forming the MAC using switched
IBC
MA capacitors can potentially be more
G1
MD energy efficient than digital circuits
∆VBL
∆V
at low bit widths despite ADC and
BL BLB I1 = V1 × G1
DAC overhead. In [60] and [61], the
Ideal Transfer Curve V2 matrix multiplication (with bit widths
Standard Deviation less than or equal to 8 bits) is inte­
G2
0.06 (from Monte Carlo grated into the ADC; this also moves
Simulations) the computation closer to the sensor
∆VBL(V)

I2 = V2 × G2
0.04 and reduces the number of ADC con­
versions by 21×.
0.02
To further reduce the data move­
Nominal Transfer Curve
I = l1 + l2 ment from the sensor, [62] proposed
0
5 10 15 20 25 30 35 = V1 × G1 + V2 × G2 performing the entire CONV layer
WLDAC Code in the analog domain at the sensor.
(a) Multiplication Performed by (b) Gi Is Conductance of Resistive Similarly, in [63], the entire HOG
Bit Cell (Figure from [57]) Memory (Figure from [58]) feature is computed in the analog
domain to reduce the sensor band­
FIGURE 7: Analog computation by (a) a SRAM bit-cell and (b) nonvolatile resistive memory. width by 96.5%.

increased speed or reduced energy
consumption. In Eyeriss [53], the PEs
are designed to skip reads and MACs
when the inputs are zero, resulting
in a 45% energy reduction. In [42],
specialized hardware is designed to
avoid computation and storage of zero-
valued weights, which reduces the
energy and storage cost by 43% and
34%, respectively.
Compression
L ight weight compression can be
ap­­­­p lied to exploit data statistics
(e.g., sparsity) to further reduce data
movement and storage cost. Lossless
compression can reduce the trans­
fer of data on and off chip by around
2× as shown in [5], [44], and [55]. Lossy
compression such as vector quantiza­
tion can also be used on feature vec­
tors [42] and weights [3], [6], [56] such
that they can be stored on chip at low
cost. Note that when lossy compres­
sion is used, it is also important to
evaluate the impact on accuracy.
Opportunities in
Mixed-Signal Circuits
Mixed-signal circuit design can be
used to address the data movement
between the memory and PE and also
the sensor and PE. However, circuit
nonidealities should be factored into
the algorithm design, for instance,
by reducing precision as discussed
in the “Opportunities in Joint Algo­
rithm and Hardware Design” section.
In addition, since the training often
occurs in the digital domain, the
analog-to-digital converter (ADC) and
the digital-to-analog converter (DAC)
overhead should also be accounted
for when evaluating the system.
While spatial architectures bring
the memory closer to the computa­
tion (i.e., into the PE), there have also
been efforts to integrate the compu­
tation into the memory itself. For
instance, in [57] the classification is
embedded in the SRAM [Figure 7(a)],
where the bit-cell current is effec­
tively a product of the value of the
5-b feature vector (WLDAC) that
drives the word line (WL), and the
value of the binary weight stored
in the bit cell. The currents from
bit cells in the column are added
together to discharge the bit line
(BL) by TVBL. This approach gives
12× energy savings over reading the
1-b weights from the SRAM.
Opportunities in
Advanced ­Technologies
Advanced technologies can also be
used to reduce data movement by
moving the processing and mem­
ory closer together. For instance,
embedded DRAM (eDRAM) and hyper
memory cube (HMC) are explored
in [39] and [64], respectively, to
reduce the energy access cost of the
weights in DNNs. The multiplication
can also be directly integrated into
advanced nonvolatile memories [65]
by using them as resistive elements
[Figure 7(b)]. Specifically, the multi­
plications are performed where the
conductance is the weight, the volt­
age is the input, and the current is the
output; the addition is done by sum­
ming the current using Kirchhoff’s
current law. Similar to the mixed-sig­
nal circuits, the precision is limited,
and the ADC and DAC overhead must
be considered in the overall cost.
DNN processing using memristors is
demonstrated in [58] and [66], where
the bit width of the memristors is
restricted to between 2 to 4 bits.
The computation can also be em­­­
bedded into the sensors. For instance,
an angle sensitive pixels sensor can
be used to compute the gradient of

52 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

the image input, which, along with
compression, reduces the sensor
bandwidth by 10× [67]. Such a sen­
sor can also reduce the computation
and energy consumption of the sub­
sequent processing engine [48], [68].
Summary
Machine learning is an important
area of research with many prom­
ising applications and opportuni­
ties for innovation at various levels
of hardware design. The challenge
is to balance the accuracy, energy,
throughput, and cost requirements.
Since data movement dominates
energy consumption, the primary
focus of recent research has been
to reduce the data movement while
maintaining accuracy, throughput,
and cost. This means selecting archi­
tectures with favorable memory hier­
archies like a spatial architecture and
developing data flows that increase
data reuse at the low-cost levels of
the memory hierarchy. Joint design
of algorithms and hardware can be
used to reduce bit-width precision,
increase sparsity, and compression
to further reduce the data movement
requirements. Mixed-signal circuit
design and advanced technologies
can be used to move the computa­
tion closer to the source by embed­
ding computation near or within the
sensor and in the memories.
Finally, designers should also con­
sider the interactions between the
different levels of design. For instan­
­ce, reducing the bit width through
hardware-friendly algorithm design
enables reduced precision process­
ing with mixed-signal circuits and
nonvolatile memories. Reducing the
cost of memory access with advanced
technologies could also result in more
energy-efficient data flows.
Acknowledgments
Portions of this article contains ex­­­­
cerpts from the invited paper “Hard­
ware for Machine Learning: Challenges
and Opportunities” that appeared at
the 2017 IEEE Custom Integrated Cir­
cuits Conference [69]. The work was
done in collaboration with Yu-Hsin
Machine learning is an important area of
research with many promising applications and
opportunities for innovation at various levels
of hardware design.
Chen, Joel Emer, Amr Suleiman, Tien-
Ju Yang, and Zhengdong Zhang.
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About the Author
Vivienne Sze (sze@mit.edu) is an
associate professor in the Electrical
Engineering and Computer Science
Department at the Massachusetts
Institute of Technology (MIT). Her
research interests include energy-
aware signal processing algorithms
and low-power circuit and system
design for multimedia applications
such as machine learning, computer
vision, and video coding. Prior to
joining MIT, she was with Texas
Instruments, where she developed
algorithms and hardware for the lat­
est video coding standard H.265/
HEVC. She received the B.A.Sc. degree
from the University of Toronto in
2004 and the S.M. and Ph.D. degrees
from MIT in 2006 and 2010, respec­
tively. She is a recipient of several
awards, including the Google Faculty
Research Award, the AFOSR Young
Investigator Award, the DARPA Young
Faculty Award, and the Jin-Au Kong
Outstanding Doctoral Thesis Prize.
She currently serves on the Technical
Program Committee of VLSI Sympo­
sium and MICRO.

 Embedded Deep Neural
Network Processing
Algorithmic and processor techniques
bring deep learning to IoT and edge devices
D
eep learning has
recently become
im-mensely pop­
ular for image rec­­
ognition, as well as
for other recognition and pattern match­­
ing tasks in, e.g., speech processing,
natural language processing, and so
forth. The online evaluation of deep
neural networks, however, comes with
significant com­­putational complex-
ity, making it, until recently, feasible
only on power-hungry server plat-
forms in the cloud. In recent years,
we see an emerging trend toward em-
bedded processing of deep learning
Digital Object Identifier 10.1109/MSSC.2017.2745818
Date of publication: 16 November 2017
1943-0582/17©2017IEEE
Marian Verhelst and Bert Moons
networks in edge devices: mobiles,
wearables, and Internet of Things
(IoT) nodes. This would enable us
to analyze data locally in real time,
which is not only favorable in terms
of latency but also mitigates privacy
issues. Yet evaluating the powerful
but large deep neural networks with
power budgets in the milliwatt or even
microwatt range requires a signifi-
cant improvement in processing en-
ergy efficiency.
To enable such efficient evalua-
tion of deep neural networks, optimi-
zations at both the algorithmic and
hardware level are required. This
article surveys such tightly interwo-
ven hardware-software process-
ing techniques for energy efficiency
IEEE SOLID-STATE CIRCUITS MAGAZINE
background—footage firm, inc.
and shows how implementation-
driven a lgor ithm ic innov ations,
together with customized yet flex-
ible processing architectures, can
be t r ue g a m e c h a n g e r s . To h e lp
readers fully understand the im-
plementation challenges as well as
opportunities for deep neural net-
work algorithms, we start by briefly
summarizing the basic concept of
deep neural networks.
The Birth of Deep Learning
Deep learning [1] can be traced back
to neural networks, which have been
around for many decades and were
already gaining popularity in the
early 1960s. A neural network is a
brain-inspired computing system,
fa l l 2 0 17 55
typically trained through supervised The trained classification model illustrated in Figure 1. The output
learning, whereby a machine learns in such neural networks consists of of the network indicates the prob-
a generalized model from many several layers of neurons, wherein ability that a certain object class is
training examples, enabling it to each neuron of one layer connects observed at the network’s input. In
classify new items. to each neuron of the next layer, as such a network, every individual neu-
ron creates one output o, which is a
weighted sum of its inputs i. For the
i11
nth neuron, of layer l, this can be for-
o11 o21 o31 Car? malized as
i12
o12 o22 o32
i13 House? o ln = v c /w lmn . i lm + b ln m . (1)
i14 m
o33 Dog?
i15 o13 o23
The weights w lmn and biases b ln are
b11 the flexible parameters of the net-
i11 × w111 work that enable it to represent a
i11 o11
i12 o11 particular desired input/output map-
i12 × w112 +
i13 ping for the targeted classification.
i13 × w113 σ They are trained with supervised
training examples in an initial off-
Oln = σ (∑wlmn × ilm + bln) line training phase, after which the
m network can classify new examples
presented to its inputs, a process typi-
Figure 1: A traditional fully connected neural network is made up of layers of neurons. cally referred to as inference.
­Every neuron makes a weighted sum of all its inputs, followed by a nonlinear ­transformation. Such neural networks have been
used for decades in several applica-
tion domains. In a classical pattern-
Edges recognition pipeline [Figure 2(a)],


Gradients
Neural features are generated from an input
Corners “House”
Network image by an application-specific fea-
HOG
…
ture extractor, hand-designed by an
expert engineer. This preliminary
Image Designed Trained Class
Feature Classifier Label feature extraction step was necessary
Extraction because, at that time, one could use
(a) only small neural networks with a
limited number of layers that did not
…


have the modeling capacity required
… Neural “House” for complex feature extraction from
network
… raw data. Larger neural networks were
impossible to train due to noncon-
Image Trained Trained Class vergence issues, lack of sufficiently
Feature Classifier Label large data sets, and insufficient com-
Extraction
(b) pute power.
Yet, after a long winter for neural
networks in the 1970s and 1980s,

 “House”
they regained momentum in the
1990s and again in the 2010s. The
incr e a sing av a ilabilit y of pow-
Image Trained Trained Class erful compute servers and graph-
Feature Classifier Label ics processing units (GPUs), the
Extraction abundance of digital data sources,
(c)
and innovations in training mecha-
nisms allowed training deeper and
Figure 2: (a) Traditionally, machine learning classifiers were trained and applied on hand-
deeper networks, with many layers of
crafted features. (b) The advent of deep learning allowed the network to learn and extract the
optimal feature sets. (c) Such a network trains itself to extract very coarse, low-level features neurons. This meant the start of a new
in its first layers, then finer, higher-level features in its intermediate layers, and, finally, targets era for classification, as it allow­­
full objects in the last layers. HOG: histogram of oriented gradients. ed training networks with enough

56 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

modeling capacity to operate directly To enable efficient evaluation of deep
on raw data. [Figure 2(b)]. Such “deep
learning networks” thus fulfilled neural networks, optimizations at both the
the role of both feature extractor algorithmic and hardware level are required.
and classifier.
A deeper network can automati-
cally learn the best possible features The first part of the network con- size H # H # C ) into a 3-D output ten-
during its training phase, instead of sists out of a sequence of convo- sor I (of size M # M # F ).
relying on features hand-crafted by lutional layers and pooling layers, As illustrated in Figure 4, each
humans. When inspecting trained replacing the traditional fully con- element of the output tensor O does
networks, one can see that a deep nected layers. A convolutional layer not need all elements of the input
neural network trains itself to extract transforms a 3-D input tensor O (of tensor I to be computed. Instead, it
very coarse, low-level features in its
first layers and finer, higher-level
features in its intermediate layers
Hand-Crafted Deep ImageNet Challenge:
and then targets full objects in the Features Learning
last layers [Figure 2(c)]. 1,000 Classes
28.2
25.8 1.3 M Training Images/50 k
A network’s ability to learn the
Validation/100-k Testing
most optimal features significantly
boosted the classification accuracy Eight Layers Top 5 Classification Errors (%)
of such networks, resulting in their
16.4 Eight Layers
true breakthrough: deep learning was
19 Layers
born. Over the last decade, deep learn- 11.7
ing has, as such, been able to move to 22 Layers
Human 7.7
deeper and deeper network architec- 6.7 152 Layers
5.1%
tures, enabling tremendous improve- 3.57
ments in achievable classification
accuracy, as illustrated by the results
0

N 2

VG ’14

eN 4

N 5
from the yearly ImageNet challenge
’1

’1

ex ’1

’1

gl C’1

es ’1
et

et

et
C

Al RC

R RC
R

oo R
(Figure 3) [2].
SV

SV

SV

SV

SV

G V

SV
S
IL

IL

IL

IL

IL

IL

Deep Neural Network Topologies
Another crucial factor in the break-
through of deep learning technol-
ogy is the advent of new network
topologies. Classical neural networks—
which rely on so-called fully con-
nected layers, with each neuron of
one layer connected to each neuron
of the next layer (Figure 1)­­— suffer
from a very large number of training
parameters. For a network with L
layers of N neurons each, L. (N 2 + N)
parameters must be trained. Know-
ing that N can easily reach the
order of a million (e.g., for images
with a million pixels), this large
pa­­­rameter set becomes unpractical
and untrainable.
For many tasks (mainly in image
processing and computer vision),
convolutional neural networks (CNNs)
are more efficient. These CNNs, in­­
spired by visual neuroscience, orga-
nize the data in every network layer
as three-dimensional (3-D) tensors.
IL
Figure 3: The classification results of the ImageNet challenge have seen enormous boosts
in accuracy since the appearance of deep learning submissions. (Data from [2].) ILSVRC: Ima-
geNet Large-Scale Visual Recognition Challenge; AlexNet: a CNN named for Alex Krizhevsky;
VGG: a network from the Visual Geometry Group at Oxford University; ResNet: Residual Net.
Trained Feature Extraction Classification
C
F
K
K
H
M
ReLU ReLU Fully Connected
Convolutional Max-Pooling Convolutional Max-Pooling Classification
for (int f = 0; f < F; f++) Per Output Pixel of a Layer:
for (int mx = 0; mx < M; my++) • Load C.K 2 Weights
for (int my = 0; my < M; mx++) • Load C.K 2 Inputs
for (int c = 0; c < C; c++) • Do C.K 2 MACs
for (int kx = 0; kx < K; kx++) • One Output Store
for (int ky = 0; ky < K; ky++) Repeat F.M 2 Times Per Layer
o [c ][mx][my] += w [f ][c ][kx][ky] . i [c ][mx + kx][my + ky]);
Figure 4: The topology and pseudocode of one layer of a typical CNN. The psuedocode is
for one layer of the network. MACs: multiply accumulation.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 57

 A deeper network can automatically learn
the best possible features during its training
phase, instead of relying on features hand-
crafted by humans.
is connected only locally to a patch maximum of a local patch (typically
of the input tensor of size (K # K # C ) 2 × 2 or 3 × 3) of output units to the
through a trainable 3-D kernel W (of next layer. This thereby reduces the
size K # K # C ) and a bias B. A formal dimension of the feature representa-
mathematical description to com- tion and creates invariance to small
pute the outputs of a convolution shifts and distortions in the inputs.
layer, l, is given as A modern CNN consists of tens [3]
to hundreds [4] of such alternating
C K K
O lfxy = / / / I lc^x +i h^y +j h .W lfcij + B lf . convolutional and max-pooling lay-
c =0 i =0 j =0 ers, typically followed by one to
three classification layers, imple-
The result of the local sum com- mented using the traditional fully
puted in this filter bank is then connected neurons (Figure 4).
passed through a nonlinearity layer, It is important to note that the
typically a rectified linear unit (ReLU), same convolution kernel W and bias
using the nonlinear activation func- B are used to compute all (M X M)
tion f ^u h = max ^0, u h. This output outputs of one slice in the output ten-
can finally be processed by a max- sor. As such, every layer of the net-
pooling layer, which outputs only the work needs only F x ^K # K # C + 1h
Embedded Device: Tx/Rx Latency Cloud: Training + Inference
Privacy
Tx Energy
Raw Data
Classification
Result
Scarce Resources Infinite Resources
(a)
Embedded Device: Inference Latency Cloud: Training
Privacy
Tx Energy
uP Energy
Training
Information
Network
Parameters
Scarce Resources Infinite Resources
(b)
Figure 5: Concerns regarding user privacy, recognition latency, and energy wasted on raw
data transmission push deep learning inferences from (a) the cloud to (b) the embedded device.
Tx/Rx: transmitter/receiver; uP = microprocessor.
58 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
parameters. With K typically rang-
ing between one and seven and F and
C on the order of tens or hundreds,
this method allows the creation of
very large networks while keeping
the number of trainable parameters
under control—all of which gave
deep learning its significant boost.
The majority of recent state-
of-the-art deep learning networks
rely on such CNNs. The optimal net-
work architecture, characterized
by the number of cascading stages
and the values of model param-
eters F, H, C, K, and M, varies for
each specific application. Over the
last few years, various alterations
have been proposed to this stan-
dard topology, such as, e.g., introduc-
ing feed-through connections in
ResNets [4], concatenating very small
convolutions in inception networks
[5], stacking depthwise and pointwise
convolutions in Xception networks
[6], extracting full-image dense mul-
tiscale features using DenseNets
[7], or recurrent connections in RNNs
or long short-term memories [8].
These, however, lie beyond the scope
of this tutorial.
Challenges for Embedded
Deep Inference
Both the training of a deep network
and its own inferences to perform
new classifications are now typically
executed on power-hungry serv-
ers and GPUs [Figure 5(a)]. There is,
however, a strong demand to move
the inference step, in particular, out
of the cloud and into mobiles and
wearables to improve latency and
privacy issues [Figure 5(b)]. How-
ever, current devices lack the capa-
bilities to enable deep inferences for
real-life applications.
Recent neural networks for image
or speech processing easily require
more than 100 giga-operations (GOP)/s
to 1 tera-operations (TOP)/s, as well
as the ability to fetch millions of
network parameters (kernel weights
and biases) per network evaluation.
The energy consumed in these numer-
ous operations and data fetches is
the main bottleneck for embedded
inference in energy-scarce milliwatt or
microwatt devices. Currently, micro-
controllers and embedded GPUs
are limited to efficiencies of a few
tens to hundreds of GOP/W, while
embedded inference will only be
fully enabled with efficiencies well
beyond 1 TOP/W. Overcoming this
bottleneck is possible yet requires
a tight interplay between algorith-
mic optimization (modifying the
network topology) and hardware
optimization (modifying the process-
ing architectures).
The following section elaborates on
the most promising optimizations cur-
rently being explored toward energy-ef-
ficient, embedded deep in­­­­ference. The
focus here is on the energy-efficient
execution of convolutional layers,
which form the bulk of the workload
during inference. However, several tech-
niques can also be applied to fully con-
nected layers.
Algorithmic and Architectural
Techniques for Energy Efficiency
GPUs and central processing units
(CPUs) are extremely flexible, general-
purpose machines. While this makes
them widely deployable and easy to use
and program, it also limits their effi-
ciency because they cannot exploit
several computational aspects of
deep inference networks, resulting
in both a memory bottleneck and a
computational bottleneck. More spe-
cifically, deep inference networks
have three typical characteristics
that can be exploited—or further
enhanced—to improve execution en­­
ergy efficiency:
1) Deep learning networks exhibit a
very particular data flow with a
large amount of potential paral-
lelism and data reuse. This can,
moreover, be manipulated dur-
ing network training by playing
with the F, H, C, K, and M pa-
rameters of the network.
2) Deep learning networks prove
to be quite robust to approxima-
tions or fault introductions. This
is exploited in various reduced-
precision hardware implementa-
tions. Also, this characteristic can
CNNs, inspired by visual neuroscience,
organize the data in every network layer
as 3-D tensors.
be manipulated when training the techniques highlighted in this article
network, allowing it to find the are summarized in Figure 6.
best tradeoff between a low com-
plexity and a robust network. Enhancing and Exploiting
3) Deep learning networks dem- Network Structure
onstrate large sparsity. Many In many application areas, designers
parameters become very small, have improved the energy efficiency
even equal to zero, after network of embedded network evaluation by
training. Also, many data values moving away from general-purpose
propagated with the network processors and developing custom-
during evaluation become zero. ized hardware accelerators. Such
This can be exploited to reduce accelerators can exploit the known
operations and memory fetches data flows within the algorithm to
in hardware yet can also be stim- 1) enhance the parallel execution of
ulated further with innovative the algorithm as well as 2) minimize
training techniques. the number of data movements (Fig-
We will show how, for each of these ure 7). Descriptions of several app­­
three aspects, hardware can benefit lication-specific integrated circuits
from the network’s characteristics targeting the efficient execution of
but also how, during the algorith- convolutional and fully connected
mic training phase of the network, layers have recently been published.
it is possible to additionally opti- All solutions exhibit a very large
mize the particular characteristic to degree of parallelization, far beyond
reach even greater efficiency gains. CPU parallelism. This easily demon-
As such, it is clear that the hardware strates itself in a data path contain-
and algorithmic level need to closely ing a few hundred to thousands of
cooperate not only to exploit but also multiply accumulators (MACs), with
to enhance the network’s character- Google’s recent tensor processing
istics toward the most efficient hard- unit as an extreme example (64,000
ware-software realization. All of the MACs) [9].
Solving the Memory Bottleneck Solving Computational Bottleneck
A) Enhancing and Exploiting Network Structure
Algorithmic • Spatial Data Reuse • Highly Parallel Architectures
Techniques • Hierarchical Memory • Distributed Processing
Exploiting Data Locality
B) Enhancing and Exploiting Fault Tolerance
Tightly • Quantized Training • (Dynamic) Fixed Point
Linked • Stochastic Memories • Analog and Statistical
Processing
C) Enhancing and Exploiting Network Sparsity
Processor • Network Pruning • Memory and Computational
Architecture • Network Compression Gating
Techniques and Weight Sharing • Compressed Computing
Figure 6: An overview of the algorithmic and processor architecture techniques discussed to
increase efficiency and enable the inference of deep neural networks in embedded devices.
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 59
 Providing data to all these func-
tional units in parallel would be near­
­ly impossible if the temporal and
spatial locality of the data was not
exploited. Indeed, many computa-
tions within one network layer share
common inputs. More specifically, as
highlighted in the pseudocode shown
in Figure 4, every weight parameter
is reused approximately M 2 times
across multiple convolutions of the
same slice in the output tensor, and
every input data point is reused
across F different slices of the out-
put tensor. Moreover, the intermedi-
ate accumulation results o have to be
accumulated C.K 2 times. This can, in
a custom accelerator, be exploited in
several ways to further boost efficien-
cies beyond the highly parallel, yet
not data-flow-optimized, GPUs.
Weight Memory
Input/Output Memory
Minimize Data
Movements
Figure 7: Custom deep neural network processors gain efficiency by minimizing data move-
ments and maximizing parallelism. Still, it is crucial not to lose all flexibility in mapping a
wide variety of networks. FSM: final state machine.
Data reuse can be exploited by requiring intermediate accumulation
reusing the same data across multi- results o to be pushed into mem-
ple parallel execution units or, equiv- ory and refetched later, strongly im-
alently, across multiple time steps on pacting the input/output memory
the same execution unit. In this topol- bandwidth. A similar scheme fetches
ogy, three extreme cases can be dis- every weight once and multiplies it
tinguished, as shown in Figure 8. with many input values. This “weight
The first multiplies the same input stationarity” or “input parallelism”
data value with several weights of improves the weight memory band-
a layer’s different output channels. width, yet at the expense of the in-
This is also called weight parallel or put memory bandwidth. Finally, the
input stationary. In this implementa- output stationary scheme reloads
tion, every input will ideally be loaded new weights and inputs every single
into the system only once. This, how- clock cycle and yet is able to accumu-
ever, has negative repercussions on late the intermediate results locally
the weight memory bandwidth, as within the MAC unit across different
the weights must be reloaded fre- clock cycles, to the benefit of the out-
quently (every time a new input is put memory bandwidth.
applied). Moreover, the accumula- All these optimizations can be
tion of the output o cannot be per- seen as a reshuffling of the nested
formed across different clock cycles, loops in the pseudocode of Figure 4.
Of course, in practice, most realiza-
tions implement a hybrid form of
the three presented extreme cases.
MAC Array
Examples include [23] and [24], where
× × × ×
a two-dimensional (2-D) data path
+ + + +
FSM or multiplies every input with several
× × × × Processor weights, while every weight is also
+ + + + Controlled
multiplied with several inputs, and
× × × × [10], where the input and output
+ + + + stationarities are optimized to mini-
mize the chip input/output band-
Maximize Maintain width. Which parallelization scheme
Parallelism Flexibility
is optimal depends strongly on the
network’s dimensions; the parame-
ters F, H, C, K, and M, which allow
cooptimization of the hardware; and

Weights Weight Weights Weights

× × × × + × + × × × × ×
+
Outputs
Outputs

× + ×
Inputs
Inputs

+ + × × × ×
Input

Input

+ × + × × × × ×
× + + × × × ×
+ ×

Input Stationary Weight Stationary Output Stationary Hybrids

(Weight Parallel) (Input Parallel)

Input BW Low High High Medium

Weight BW High Low High Medium
Output BW High High Low Medium

Figure 8: Different architectural topologies allow data reuse to be maximized, reusing either inputs, weights, intermediate results, or a
combination of the three. BW: bandwidth

60 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

the network itself. A more elaborate
overview of the different paralleliza-
tion schemes can be found in [11]
and [12], along with an assessment of
their merits.
A complementary way to reduce
the energy burden of continuous
data fetches is not to minimize the
number of data fetches but rather to
reduce the energy cost of every data
fetch by exploiting temporal data
locality. Most realistic deep networks
require so much weight and input/out-
put memory (megabytes to gigabytes)
that it is impossible to fit them in on
a chip memory, thus requiring fetches
from energy-costly external dynamic
random-access memory (DRAM). Simi-
lar to traditional processors, this can,
however, be mitigated by a memory
hierarchy having one or more levels of
on-chip static RAM (SRAM) or register
files. Frequently accessed data can, as
such, be stored locally to reduce its
fetching cost (Figure 9).
An important difference with gen-
eral-purpose solutions, however, is
that the sizes of the memories in the
hierarchy can be optimized toward
the network’s structure, e.g., foresee-
ing a local memory capable of cach-
ing exactly one weight tensor, or one
of the tensor [11]. Even more impor-
tantly, the networks can be trained
with the processor’s memory hierar-
chy in mind. As such, networks have,
e.g., been explicitly trained to com-
pletely fit in on-chip memory. This
optimization is, of course, highly
interwoven with the parallelization
scheme. By jointly optimizing these,
one can adjust the degree of parallel-
ization to the memory hierarchy and
minimize the product of the number
of memory accesses with the cost of
every memory access [13].
Distributed and systolic process-
In the systolic processing concept, a 2-D array
of functional units processes data locally and
passes inputs and intermediate results from
unit to unit instead of to/from global memory.
in [14]) or even just registers (as in [9])
to store data locally and maximize
data reuse within the array. Process-
ing happens as a systolic wavefront
through the array, wherein weight
coefficients can be kept stationary in
the functional units, input data are
shifted in one direction through the
array, and output data accumulate in
the orthogonal direction. This allows
the performance of a very large num-
ber of computations for convolution
or matrix multiplication in parallel
by keeping all systolic elements busy
without burdening the memory band-
width. Interested readers are pointed
to [15] and [9] for more details.
Such systolic operation opens the
door to in-memory computing, where
the computation is integrated inside
the memory array. While this is also
pursued in traditional memory archi-
tectures, the results look especially
promising for emerging nonvolatile
memory arrays. For example, in resistive
memory technologies, a multiplication
can be implemented by exploiting
the memory cell’s conductance as the
kernel weight, while accumulating cur-
rent from different elements to imple-
ment the convolution’s accumulation
operation [16]. However, this technol-
ogy currently still suffers from large
variability, limiting applications to very
low-resolution operations with very lim-
ited kernel and network sizes.
While all the aforementioned tech-
niques can dramatically boost the
system’s throughput and energy effi-
ciency, it is important to keep an eye
on their impact on the design’s pro-
grammability and flexibility. Espe-
cially in the fast-paced area of deep
learning, it is of the utmost impor-
tance to maintain sufficient flexibility
toward alternative network dimensions
and novel network topologies. Most
accelerators, however, succeed in this
by enabling the acceleration of matrix
multiplications (for the fully con-
nected layers) and convolutions (for
the convolution layers) of any size,
yet with maximal efficiency for a sub-
set of sizes.
Enhancing and Exploiting
Fault ­Tolerance
A second important aspect of deep
neural networks that can be exploited
in custom processor designs is their
fault tolerance. Many studies observe
the robustness of CNNs and other
networks to perturbations on their
weight parameters and intermediate
computational results [17], [18]. This
can be exploited both at the hard-
ware as well as the algorithmic level
in several ways.
MAC Array
× × × ×
Registers

Local + + + +
ing can be seen as an extreme type Off-Chip On-Chip SRAM
of such hierarchical memories. In the DRAM SRAM × × × ×
kB + + + +
systolic processing concept, a 2-D pJ/Word
array of functional units processes MB × × × ×
Tens of pJ/Word B + + + +
data locally and passes inputs and GB <pJ/Word
intermediate results from unit to Hundreds of pJ/Word
unit instead of to/from global mem-
ory. These functional units are each Figure 9: A well-designed memory hierarchy avoids drawing all weights and input data
equipped with a very small SRAM (as from the costly DRAM interface and stores frequently accessed data locally. pJ: picojoule.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 61

 A straightforward way to ben- weights and intermediate results. bit-width implementations all exploit
efit from the network’s fault toler- Moreover, for very low bit widths, the deep network’s tolerance to faults
ance is to perform the computations this even allows the replacement of in a deterministic way.
at reduced computational accuracy multipliers that have several data Another school of thought targets
with limited recognition loss. Typi- values with a common weight factor energy savings through tolerating
cal benchmarks can be run at a 1–9-b via preloaded lookup tables [10]. As nondeterministic statistical errors.
fixed point rather than a 32-b floating a result, all custom CNN accelerators This can be accomplished by execut-
point at lower than 1% accuracy loss operate in fixed point. While most ing the convolutional kernels in the
[18]. This is possible by quantizing processors operate at constant 16-, noisy analog domain [26]. Alterna-
all weights of a floating-point-trained 12-, or 8-b word lengths, some recent tively, in the digital domain, stochas-
network before execution. Improved implementations support variable tic fault tolerance can be exploited
results can be obtained when intro- word-length computations, wherein by operating the circuits [27] and/
ducing quantization during the train- the processor can change the used or memory [28] in the energy-effi-
ing step itself [19], [38], resulting in computational precision from opera- cient near-threshold regions. In this
smaller or lower-precision networks tion to operation [23], [10], [24]. This region, circuit delays as well as
for the same application accuracy. As accommodates for the observation memory failures suffer from large
an extreme example, networks have that the optimal word length for a variation. Yet the networks can tol-
been specifically trained to oper- deep network strongly varies from erate such stochastic behavior up to
ate with only 1-b representations of application to application and is a certain limit. Such circuits are com-
weights alone [20] as well as with even shown to differ across various bined with circuit monitors that con-
both weights and activations [20], layers of a single deep network [18] stantly assess and control the circuit’s
[21] wherein all multiplications can [Figure 10(a)]. fault rate [28].
be replaced by efficient XNOR opera- Energy-efficient variable-resolu- Finally, the operational circum-
tions [22]. In [20], a binary-weight tion processors have been realized stances can strongly influence the net-
version of ImageNet is only 2.9% less using a technique termed dynamic work’s tolerance to approximations. In
accurate (in top-1 accuracy) than the voltage-accuracy-frequency scaling a given classification application, the
full-precision AlexNet [3]. [25] to jointly reduce the switching quality of the inputs might change
This observation can lead to major activity, supply voltage, and par- dynamically, or some classes might be
energy savings, as current CPU and allelization scheme when computa- easier to observe than others. If one
GPU architectures operate using tional resolution drops [Figure 10(c)]. tries to train one common network
32–16-b floating-point number for- This results in a scaling of the sys- that performs acceptably under all
mats. Reducing precision from 32-b tem’s energy consumption, which is possible circumstances and classes,
floating point to low precision not super-linear with the computational a large, complex, energ y-hungr y
only reduces computational energy resolution [Figure 10(b)], thus allow- network topology would be needed.
but also minimizes the storage and ing every network layer to run at its Recent work, however, promotes the
data-fetching cost needed for network own minimal energy point. Reduced training of hierarchical or staged

AlexNet on ImageNet
y3 y 2 y 1/0 y 0/0
10 x 0/0
0
10 33× Gain
Quantization (Bits)

8 16 Bit at 1% RMSE
Relative Power

x 1/0
p 0/0
6
x2 p 1/0
10–2 6 Bit
4
Uniform at 100% x3
2 p 2/0
Nonuniform at 99%
10–4 1 Bit p 3/0
0
2 4 6 8 10–6 10–4 10–2 100
Layer Number Computational Precision p7 p6 p5 p4
(a) (b) (c)

Figure 10: (a) When quantizing all weight and data values in a floating point AlexNet uniformly, the network can run at 9-b precision.
Lower precision can be achieved without significant classification accuracy loss by running every layer at its own optimal precision. This allows
(b) saving power in the function of computational precision and (c) building multipliers whose energy consumption scales drastically with com-
putational precision, through reduced activity factor and critical path length.

62 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

networks [29] that perform classifica-
tions in several optional stages. At
each stage, only a few layers of the net-
work are executed, after which a clas-
sification layer tries to guess the class
from the current outputs. Additional
network layers and classifiers are run
only if the obtained probabilities are
not outspoken enough, until a classi-
fication with distinct probabilities is
obtained. Such dynamic evaluations
can be performed on any hardware
platform but, again, benefit signifi-
cantly from implementation-aware
training techniques or topology-
opt imized implementations. Infer-
ence on the ImageNet data set [29]
required up to 2.6 times fewer opera-
tions than state-of-the-art networks at
equivalent accuracy.
Enhancing and Exploiting Sparsity
Deep neural networks exhibit extreme
sparsity, i.e., many of the weight val-
ues, as well as intermediate data val-
ues, are zero. Figure 11(a) shows the
sparsity of an AlexNet in function
of the used fixed-point word length
within the network. As can be seen,
even for large word lengths, more
than 70% of the activations are zero.
At reduced bit-width computations,
also many weight values are quan-
tized to zero. This opens up many
opportunities.
On the hardware side, this can be
exploited by preventing any MAC with
a zero-valued input [see Figure 11(b)],
by not even fetching zero-valued data
values from memory, and by strongly
100
Mean Sparsity (%)
0 Memory
00
0 50
00
0 Layer Inputs
Weights
0
2 4
Fixed Point Precision (bits)
(a)
Figure 11: (a) The sparsity of input and weight values of a typical network in function of computational precision at which the network is
evaluated. (b) This sparsity allows energy to be saved in the processor’s input/output interface, on-chip memories, and data path.
An important difference with general-purpose
solutions, however, is that the sizes of the
memories in the hierarchy can be optimized
toward the network’s structure.
compressing the on/off chip data
stream using, e.g., Huffman or other
types of encoding. Several hardware
implementations exploit these CNN
characteristics. The authors of [24]
and [11] skip all unnecessary sparse
operations by gating the inputs to
their arithmetic units if the input data
is zero, as a multiply-accumulate with
zero does not change the internal
accumulation result. Both implemen-
tations also compress off-chip data
streams, either through run-length
encoding [14] or through a simpli-
fied Huffman scheme [23]. The archi-
tectures presented in [30] and [31],
on the other hand, allow speeding up
sparse network evaluation s by only
scheduling non-zero operations for
execution, improving computational
throughput up to 1.52 and 5.2 times,
respectively.
More powerful opportunities arise,
again, when the hardware and algo-
rithmic plane are jointly involved.
Deep network training algorithms
can be modified to enhance the net-
work’s sparsity by iteratively pruning
the smallest weight values (quantiz-
ing them to zero) and retraining the
network [32]. Going one step further,
energy-aware pruning techniques
even take the energy consumption
AlexNet
DRAM
6 8 10 Compress
Off-Chip
Communication
IEEE SOLID-STATE CIRCUITS MAGAZINE
model of the hardware into account
and start pruning the layers that con-
sume the most energy, to maximize
pruning efficacy [33]. This easily
allows the pruning of 70–90% of the
weights and saves up to 70% of ener­
­g y consumption.
Interestingly enough, networks
have more compression capabili-
ties beyond simply that of pruning
low-valued weights. After pruning
and quantizing a network, it turns
out that the resulting weight values
are highly clustered. This allows, e.g.,
the clustering of 8-b weights in only
16 (24) different weight clusters, each
of which can share a common weight
value expressed by a 4-b label. For
every weight value, only the 4-b labels
are stored, and these are expanded
online to their original 8-b value using
a small embedded lookup table.
Recent work has shown that the
combination of pruning, weight shar-
ing, and Huffman compression com-
presses state-of-the-art networks by
50 times in memory size (deep com-
pression [32]). Traditional accelerators
can benefit from such compression
but only in terms of a reduction
in memory size and the amount of
memory accessed. To execute convo­
lutional operations, they must still
MAC Array
Weight
× × × ×
+ + + +
× × × ×
+ + + +
Input/Output
× × × ×
Memory
+ + + +
Prevent Fetching Prevent Executing
Zero-Valued Zero-Input
Data MACs
(b)
fa l l 2 0 17 63
 Recent work has shown that the combination integrating the deep-inference chips
in complete vision-processing pipe-
of pruning, weight sharing, and Huffman lines mapping real-life applications.
compression compresses state-of-the-art This requires not only an efficient
execution of the inference kernel itself
networks by 50 times in memory size. but also efficient image slicing, data
transfer, and results interpretation.
decompress the data and, at best, offers only limited compression capa- A second interesting challenge
remain idle during zero-valued op­­ bilities, ranging typically up to only lies in the learning process. So far, most
erations. The efficient-inference engine five times compression [36]. chips focus on the inference part,
[35], however, demonstrates that it where pretrained models are efficiently
is also possible and highly benefi- Outlook executed on-chip. In the future, how-
cial to operate directly on the com- In this short tutorial, we have pre- ever, the desire for more privacy and
pressed data by adapting the data sented a selection of very promising user customization will stimulate chips
path and memory interface to the hardware and algorithmic techniques capable of executing the training phase
compressed data format. from the rapidly expanding and as well. This, however, comes with new
A network compression technique growing field of deep learning. Each computational challenges and the
that does enable straightforward exploits and/or enhances the unique need for a careful algorithm–archi-
network execution in the complex features of deep networks to improve tecture cooptimization.
domain without any hardware adapta- the energy efficiency of their execu- It is, thus, very clear that, more
tion uses singular value decomposi- tion. Together, they have allowed the than ever, the hardware and algo-
tion (SVD) [36]. By performing SVD on achievement of tremendous energy rithmic layer must be optimized
a sparse weight matrix of a fully con- savings compared to traditional jointly, grasping the various cross-
nected network layer, the matrix can CPU- and GPU-based compute plat- layer opportunities of deep neural
be decomposed into two matrices, forms. As can be seen in Figure 12 networks. This is also apparent from
the rows and columns of which are [37], this recent wave of innovations the interest of many traditionally
ordered by the function of the most breaks the barrier for embedded software-oriented companies (like
significant network parameters. By deep inference in mobile devices. Google, Amazon, and Microsoft) in
simply removing the nonsignificant Implementations far surpassing the the development of new proprietary
sections of the matrix, one is left with efficiencies of 1-TOP/W have recently hardware for deep learning.
a strongly compressed representa- been demonstrated, while computa- This field is so vibrant that every
tion of the original network layer. The tional throughput is boosted to sev- single week new ideas pop up. Of
result can be executed on any regu- eral 100 GOP. course, space does not allow us to
lar neural network accelerator, as it Still, challenges remain to effec- cover all of the exciting ideas going
is identical to the execution of two tively bring deep learning to IoT and around in the embedded deep learn-
(much smaller) fully connected layers. edge devices. First, few (if any) com- ing space at the moment. Yet we hope
While this method is more straightfor- plete end-to-end solutions have been that we were able to spark readers’
ward from a hardware point of view, it demonstrated. Doing so involves interest and stimulate further explo-
ration of this lively field.

10
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About the Authors
Marian Verhelst (marian.verhelst@
kuleuven.be) has been an assistant
professor at the Micro-Electronics and
Sensors Laboratories of the Electrical
Engineering Department at KU Leu-
ven, Belgium, since 2012. Her research
focuses on self-adaptive circuits and
systems, embedded machine learn-
ing, and low-power sensing and pro-
cessing for the Internet of Things. She
received a Ph.D. degree from KU Leu-
ven (cum ultima laude) in 2008. She
was a visiting scholar at the Berke-
ley Wireless Research Center of the
University of California, Berkeley, in
2005. From 2008 to 2011, she worked
in the Radio Integration Research
Lab of Intel Laboratories, Hillsboro,
Oregon. She is an IEEE Solid-State Cir-
cuits Society Distinguished Lecturer
and a member of the Young Academy
of Belgium and has published over
100 papers in conferences and jour-
nals. She is a member of the Interna-
tional Solid-State Circuits Conference
(ISSCC) Technical Program Committee
and the Design, Automation, and Test
in Europe (DATE) and ISSCC Executive
Committees. She was associate edi-
tor for IEEE Transactions on Circuits
and Systems II and currently serves in
the same capacity for IEEE Journal of
Solid-State Circuits.
Bert Moons received his B.S. and
M.S. degrees in electrical engineering
from KU Leuven, Belgium, in 2011 and
2013, respectively. In 2013, he joined
the Micro-Electronics and Sensors Lab-
oratories of KU Leuven as a research
assistant, funded through an indi-
vidual grant from the Research Foun-
dation of Flanders. In 2016, he was a
visiting research student at Stanford
University, California, in the Murmann
Mixed-Signal Group. Currently, he is
working toward the Ph.D. degree on
energy-scalable and run-time adapt-
able digital circuits for embedded
deep learning applications.
fa l l 2 0 17 65
 Terri S. Fiez, Mar Hershenson, Lucy Sanders,
and Catherine Ashcraft

Innovation, Startups,
and Funding in the
Age of Accelerations
A survey of the evolving landscape

T
homas Friedman’s recent book, Thank
You for Being Late: An Optimist’s Guide to
Thriving in the Age of Accelerations, traces
how the technology revolution, fueled by
the ac­­celeration predicted in Moore’s law, has
transformed our lives [1]. Friedman celebrates the remarkable
advances that have occurred over the past several decades
and describes, in layman’s terms, the ways in which the solid-
state circuits community is transforming diverse fields rang-
ing from computing to transportation, communications to
robotics, and entertainment to energy.
It all began with the invention of the IC. Now, some 50 years
later, we take for granted the many innovations with which
we interact every day and their various paths to market. It
was hard to imagine 20 years ago that today we would have
available a palm-sized cell phone with numerous integrated
© NCWIT, used with permission. background—footage firm, inc.

wireless radios, multiple microprocessor cores, an intelligent

global positioning system, high-resolution cameras, sensor
connectivity, cloud-based storage, and the ability to connect
around the world. And this is just the tip of the iceberg in
terms of the innovations spurred by the IC revolution.
In 2016, the IEEE Solid-State Circuits Society celebrated
the 50th anniversary of IEEE Journal of Solid-State Circuits.
The most highly cited papers in each decade demonstrate the
advances that have brought us to today [2]. From the mid-1960s

Digital Object Identifier 10.1109/MSSC.2017.2745778

Date of publication: 16 November 2017

66 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

through the 1970s, basic integrated
devices and processes along with
simple analog ICs were inventions
crucial to kicking off the solid-state
revolution. Over the following two
decades, further process scaling and
circuit ingenuity fueled sophisticated
analog-to-digital converters and pro-
cessors, making the personal com-
puter as ubiquitous as telephones and
supporting high-fidelity music played
on compact discs. From the mid-1990s
to 2015, high levels of integration in­­
cluding radio frequency (RF), analog,
processors, and sensors advanced
the convergence of communications,
computation, and the Internet of
Things (IoT).
These innovations have provided
the catalyst for a plethora of start-
ups and served as the foundation
for large, established companies to
generate in excess of trillions of dol-
lars annually. Friedman observes
that, around 2007, we hit a point of
“dislocation,” which he defines as a
time “when the whole environment is
being altered so quickly that every-
one starts to feel they can’t keep up.”
By hitting this acceleration point,
with change occurring so quickly,
will start-up companies and IC inno-
vations continue to play a vital role
in creating and advancing the next
big thing?
To help understand the changes in
start-ups, venture funding, and what it
takes to create a successful enterprise
in an environment characterized by
dislocation, Terri Fiez posed a series
of questions to Mar Her-
shenson of Pear Venture
Capital (VC) and to Lucy
Sanders and Catherine Ash-
craft of the National Center
for Women and Information
Technology. Their responses
provide some important
insight into this changing
landscape, as well as keys
for success. 33
Q: Mar, you have been a 2010
serial en­­trepreneur and
have now become a ven- Figure 1: The number of active seed funds per year. (Source: CB
ture capitalist. Why did you Insights.)
make this change and what impact
do you hope to make?
Mar: I became a venture capitalist
almost by accident. Pejman Nozad, an
angel investor in my second company,
Sabio Labs, approached me about
building a firm together. Initially,
I was reluctant. But, after al­­most
four years of courtship and some
angel investing, I decided to take the
plunge. I wanted to build a firm that
would provide the help to founders
that I would have liked to have access
to when I was starting my own com-
pany. For me, that meant building a
support layer for founders that was
available and effective when they
most needed it.
To build this support layer, we
have invested in two key initia-
tives. First, we have built a strong
and vibrant community of founders,
advisors, executives, and investors.
We believe that we are more powerful
when our community is effectively
connected. For example, a founder
who has questions on hiring will ben-
efit greatly from connecting to other
founders who have just hired rather
than just listening to us on best
hiring practices. To foster commu-
nity, we have very specific activities
such as small chief executive offi-
cer (CEO) dinners, educational work-
shops, social events, a distinguished
speaker series, an online community,
and a strong mentorship program.
Second, we have developed spe-
cial programs targeted at first-time
founders, especially those coming out
Number of Active Seed Funds
150
112
65
42
2011 2012 2013 2014
IEEE SOLID-STATE CIRCUITS MAGAZINE
of universities. During the acade­­
mic year, we run a program, Garage,
where we work closely with a group
of 20 engineering students as they
are thinking of starting a company.
We connect them with mentors in our
community, have regular check-ins,
offer them resources and personal
guidance. During the summer, we
run a second program, Pear Sum-
mer, where we invest in 15 com-
panies started by recent graduates,
practically all of whom graduated
that same year. My background as a
founder right after completing grad-
uate school makes me very attuned
to their needs. I am convinced that
we can teach a recent Ph.D. degree
graduate the principles of becoming
a great founder. Many of them are
mystified by the process of selling or
marketing, when it is something they
can learn if they put enough effort
behind it.
My personal goal is to help as
many founders as possible in build-
ing impactful companies. In the end,
it is founders that make companies
succeed, not any of us: we are here to
support and enable.
Q: How is Pear VC approaching
investing, and why are you taking
this approach?
Mar: Venture investment has
changed a lot in the last 15 years.
Back in 2000, one could raise an ini-
tial round of financing of US$3–5 mil-
lion from the larger series A funds on
Sand Hill Road with a PowerPoint pre-
sentation. Today, two things
have happened. One is that,
to raise series A, a company
needs to show significant
236 traction. Two is that one
does not need US$5 million
to get things started. Many
companies get started with
small cash infusions of
US$2 million or less. As a
result, there is a new type
of venture firms, called seed
2015 funds or micro VCs. In the
last ten years, the number of
seed funds has grown from
zero to almost 300 (Figure 1).
fa l l 2 0 17 67
 ”In the end, it is founders that make
companies succeed, not any of us: we are
here to support and enable.”
Additionally, there are many more
angel investors than there have ever
been. Figure 2 shows the growth of
angel investors in the popular fund-
raising platform Angel List.
Pear VC is a seed VC that is lead-
ing initial companies’ investments
across disciplines. We typically write
the first institutional check. We are
focused on finding great founders
with the ambition to build large
companies. We are not looking for
specific operational traction but
rather an understanding of how it
could be possible for building and
defining a company.
In the case of semiconductors,
one could argue that seed financing
is not viable. Semiconductor compa-
nies still require large amounts of
capital, so small seed financing is not
possible. While it is true that more
capital is needed to truly proof the
business, it is possible to raise seed
funding from the more widely avail-
able sources and focus on de-risking
some of the investment hypothesis.
How are companies doing this? In
some cases, semiconductor com-
panies can de-risk the investment
early on by building an initial pro-
totype on a field-programmable
gate array, plus basic software, and
shipping that to early customers.
Initial customer validation,
makes it much easier for
them to raise a large series
A that will fund their custom
application-specific IC (ASIC)
design. There are several
examples of seed rounds
for current successful semicon-
ductor companies: Nervana,
a compa ny developing
custom ASICs for machine-
learning applications, raised
a US$600,000 seed round
followed up by a US$3.3 mil-
lion series A and a larger Figure 2: The number of active angel investors on Angel List.
US$20 million series A-II; (Sources: Angel List, Techcrunch, and Harvard Business Review.)
68 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Barefoot networks, a company pro­­
ducing programmable net work
switches, raised US$1.35 million seed
before raising a US$24 million series
A. In other cases, companies de-risk
the initial venture investment by
raising nondilutive capital (e.g.,
SBIRs [funding from the U.S. govern-
ment’s Small Business Innovation
Research program]) and/or corpo-
rate financing.
Q: Is there a future for start-ups
that include ICs as part of their
core technology?
Mar: Absolutely. After a decade of
drought, we are seeing investments
in the semiconductor industry from
top-tier VC firms. Of course, it is not
the panacea of the late 1990s and
early 2000s, when early-stage fab-
less semiconductor start-ups were get-
ting bought by public companies for
hundreds of millions of dollars, even
billions. Remember Broadcom pur-
chasing MIPS Technology’s core pro-
vider SiByte in a US$2 billion stock
deal in 2000 or purchasing RF trans-
ceiver provider Innovent in a US$440
million stock deal, also in 2000?
Unfortunately, starting in the early to
mid-2000s, venture investments in
semiconductors declined dramatically.
The increased cost of developing a
Investors Registered on Angel List
18,000
2,500
50
02/2010 12/2011 06/2013
state-of-the art chip (~US$80–100 mil-
lion), combined with the lack of sig-
nificant exits, made semiconductor
investments very unattractive [5].
Venture investment hit a low point in
2012–2013 [6], when fewer than five
companies were raising series A per
year. Luckily, there has been some
modest growth since 2013. What has
pushed the recovery?
It has not been better perfor-
mance on old applications but rather
the rise of new applications. One key
application is the explosion of artifi-
cial intelligence (AI) applications [5].
Since 2012, when Alex Krizhevsky
used two NVIDIA graphics processing
units (GPUs) to win the 2012 ImageNet
computer image recognition com-
petition, several major corporations
and a large number of start-ups have
been racing to build AI applications
(see Figure 3 for a graph showing the
increase in the number of start-ups
with “AI” in their company descrip-
tions). In 2016, Google announced
the first-generation tensor flow pro-
cessing units (TPUs), which are cus-
tom ASICs designed to run Google’s
tensor flow machine-learning frame-
work more efficiently. In 2017, the
company announced the second
generation of TPUs, which boast
15–30 times performance improve-
ments versus general purpose CPUs
[central processing units] and GPUs
[6]. The success of TPUs has pushed
a new breed of companies to develop
custom ASICs for specific data appli-
cations. One example is Nervana,
which was sold to Intel for
US$350 million in 2016
after two-and-a-half years
in business and raising less
than US$25 million. There
30,057
is another suite of recent
start-ups specifically pow-
ering higher-performance
data centers: for example.
Innovium (found­­ed in 2014,
raised US$88 million) and
Barefoot Networks (founded
11/2016 in 2013, raised US$153 mil-
lion) [7].
AI and data center ap-
plications are not the only
new applications to require innova-
tive silicon solutions. Other applica-
tions include those for the IoT [8],
autonomous driving [9], biotechnol-
ogy, and mobile devices. These sili-
con solutions result in more analog/
RF and microelectromechanical sys-
tem (MEMS) chips. Some recent suc-
cesses include the silicon-based DNA
synthesis platform Twist Bioscience
(founded in 2013, raised US$193 mil-
lion), custom LIDAR [light detection
and ranging] Luminar Technologies
(founded in 2012, raised US$36 mil-
lion), MEMS-based force-sensing so-
lutions NextInput (founded in 2012,
raised US$15 million), vision sensor
developer Chronocam (founded in
2014, raised US$18 million), and myr-
iad other young start-ups.
At Pear VC, after having done no
semiconductor investments in three
years, we have completed two ear-
ly stealth-stage seed investments in
semiconductor start-ups, one address-
ing a specific use of AI and the other
for health-care applications. The semi-
conductor venture investment world
is looking good.
Q: What would be your best advice
for a founder today?
Mar: I have found that the “best ad-
vice” is highly dependent on the
founder to whom the advice is target-
ed. With this in mind, I can think of a
few things that may be more appro-
priate today.
■■ Absolute focus on execution. Today,
we live in a world flooded with VC,
where the speed at which we are
seeing ideas proliferate and being
replicated is staggering. It is not
enough to have a differentiated
technology, an illustrious team, or
a lot of capital. The teams that win
are able to deliver a product that
customers are ready to buy in an
efficient manner. One of the most
crucial elements of flawless execu-
tion is excelling in the art of plan-
ning. We work with our founders
to put together an operating plan
with a very clear set of objectives
from day one, even when they have
just raised a small seed round. It
“The success of TPUs has pushed a new breed
of companies to develop custom ASICs for
specific data applications.”
is important to measure progress founder needs to focus on those
on the plan in a quantitative man- hard questions and put all his/her
ner and make adjustments based energy on addressing them.
on new information. Finally, an ■■ Be paranoid. As Andy Grove said,
operating plan is not just for the “Only the paranoid survive.” Tech-
founder and the investors. It is nology cycles are becoming shorter
something the entire team needs and shorter, so a founder needs
to be behind. For that reason, we to be ready for change, aware that
recommend absolute transparen- standing still is not an option. Past
cy, sharing objectives and prog- and current success is no indica-
ress with the team frequently. One tion of future success.
of our founders displays progress ■■ Work on yourself. This is especially
on its plan on TV screens around true for first-time founders. I have
the office. It keeps everybody fo- witnessed first-time founders become
cused on goals, motivated when great CEOs, but it does not happen by
things go well, and ready to rally accident. All of these CEOs have some-
when there are setbacks. thing in common—an innate desire
■■ Get the hard things done first. You for self-growth. They read a lot, they
can always be busy at a start-up, ask questions, and they surround
but it is absolutely critical to solve themselves with better people.
the important problems first. I can
explain this with the “standard- Q: How are large companies en­­
ized test” example. Many of us suring they are capturing the new-
are expert test takers. On a stan- est and most innovative ideas? Is
dardized test, we solve the easy it working?
questions first and leave the hard Mar: Nvidia is a very innovative
ones until the end, since they are company at fostering innovation.
all worth the same points. In the For example, this past May, Nvidia put
start-up world, it is the opposite: together its first “AI Day for VCs.”
you don’t pass the test unless you They are actively trying to partner
solve the hardest question. Thus, a with the venture community to foster
80
70
60
AI Instances
50
40
30
20
10
0
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
Figure 3: AI instances per year, based on Crunchbase descriptions. (Source: Crunchbase.)
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 69
 “Over the past decade, an increasing number Universities are also recogniz-
ing the importance of partnerships
of studies have documented the benefits and collaboration across disciplines.
associated with diverse work teams, with some For example, Harvard University
is planning to open a state-of-the-
of these studies being specific to start-ups.” art engineering and applied sci-
ences building right across from
the Harvard Business School and
the creation of more AI companies. access to free working space, a net- Harvard Innovation Labs in 2020.
They understand that their GPUs are work of alumni, and access to in- Prior to this initiative, the business
powering a large number of these vestors. For example, there are the school campus and the college cam-
companies, and it is in their interest Skydeck incubator at the University pus were physically separated. At
to support the ecosystem. Addition- of California, Berkeley (2014), Delta V Stanford, the biodesign program
ally, the Nvidia GPU Ventures Pro- accelerator at the Massachusetts In- puts special emphasis on recruiting
gram is providing financial support stitute of Technology (2012), Venture multidisciplinary teams that include
to start-ups that build their business Studio at Stanford University (2013), members with clinical, engineering,
around GPU-based platforms. Viterbi Startup Garage at the Univer- computer science, design, and/or
Intel has recognized the impor- sity of Southern California (2013), and business backgrounds.
tance of investing capital in start-ups many others. There has been a proliferation of
aligned with Intel’s mis- classes targeted at stu-
sion. Last year, Intel Capi- dents starting companies.
tal switched its investment For e x a mple, St a nford
philosophy from focusing offers over 100 courses
solely on financial returns geared at entrepreneur-
to investing in start-ups ship within the business
that align with its mission. schools, law school, and
In late 2016, Intel Capital engineering school. These
committed US$250 million classes are often taught by
to auto tech investments or cotaught with industry
and created a new Autono- experts, bringing direct
mous Driving Group inter- practical knowledge to
nally. Intel has also been the students.
acquiring start-ups at a There are many other
fast pace; 2016 was their signs of interest from the
m o s t a cq u i s it i v e y e a r academic community such
ever, with nine significant as specific efforts at eas-
acquisitions [5]. ing university technology
transfer to students, busi-
Q: How do you see uni- ness plan competitions
versities fueling the in­­ with significant monetary
novation economy? prices, campus hackathons,
Mar: Over the last five and so on.
years, there has been a sig-
nificant increase in activity Q: Diversity in start-up
by and investment from uni- companies and VC firms
versities in innovation pro- has become a very vi­­­­­si­­­
grams targeted at fostering ble issue in the last cou-
a stronger entrepreneurial ple of years. We often hear
community and facilitating the mantra that diver-
the creation of new start- sity benefits the bottom
ups. This increased activity line, but what does the
can be seen in a variety of research specifically
initiatives. tell us?
Some of them are creat- Figure 4: A graphic showing the positive outcomes for companies Catherine and Lucy:
ing their own incubators, with diverse teams. (Source: https://www.ncwit.org/resources/wom- Over the past decade, an in­­
which typically include en-it-facts-infographic-2015-update, © NCWIT, used with permission.) creasing number of studies

70 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

have documented the benefits asso-
ciated with diverse work teams, with
some of these studies being specific
to start-ups (Figure 4). For example,
a 2011 analysis by Dow Jones and
VentureSource of more than 20,000
venture-backed companies showed
that successful start-ups have twice
as many women in senior positions
as unsuccessful companies. Similar
studies show that women-led com-
panies launch, on average, with less
capital but produce higher revenues
and are more likely to survive the
transition to an established com-
pany [10]. In addition, in a study of
all investments made between 2000
and 2010 by U.S.-based VC firms (in
U.S.-based companies), VC firms that
invested in women-led businesses
saw an improvement in their VC firm’s
performance [11].
Additional studies have found
that higher levels of racial and gen-
der diversity are associated with
increased sales revenue, more cus-
tomers, greater market share, and
greater relative profits
[12]. Simila rly, another
st udy found that work
teams with equal num-
bers of women and men
were m o r e innova­t ive
a n d pr o duc t ive t h a n
teams of any other com-
position [ 1 3 ] . Finally,
research about work teams
found that the intelligence
level of individual team
members was not a pre-
dictor of the collective
intelli­gence of the team
[14]. However, the collec-
tive intelli­­g e n c e of a
team was associated with
having a higher number
of women on the team.
In light of this and
a d d i t i o n a l r ese a r ch ,
start-ups would do well
to capitalize on the ben-
efits diversity can bring
to technical invention
[15]. To reap these ben- Figure 5: A graphic detailing the benefits of diversity on compa-
efits, it’s important to nies’ bottom lines. (Source: https://www.ncwit.org/resources/wom-
pay attention to what en-it-facts-infographic-2015-update, © NCWIT, used with permission.)
“Additional studies have found that higher levels
of racial and gender diversity are associated with
increased sales revenue, more customers, greater
market share, and greater relative profits.”
kinds of technical roles women and
members of other underrepresented
groups hold, in addition to looking
at overall representation numbers.
Underrepresented groups are fre-
quently channeled into execution
or project management roles that
support those who are creating new
technology. While technical support
roles are critical, there is a need for
diversity in all aspects of the techni-
cal invention process.
Q: The IC field is dominated by
men, so how do start-ups, large
companies, or venture firms in­­
crease the participation of women
or minorities, and what can they
expect when they do?
IEEE SOLID-STATE CIRCUITS MAGAZINE
Catherine and Lucy: It’s critical
that companies address diversity dur-
ing the early phases of establishing
their culture. Organizational cultures
emerge either by design or default,
and, when by default, the culture is
likely to reflect the status quo. Acting
with intention from the beginning is far
easier and more likely to be successful
than undoing damage down the road.
Companies should treat inclusiv-
ity the way they would any other busi-
ness issue. Too often, diversity efforts
are under-resourced and undervalued.
Instead, top leadership support and
accountability need to be established,
with a commitment to allocating suffi-
cient resources to the implementation of
research-based practices, goal setting,
and measuring progress. It’s
also important to establish a
shared language and under-
standing among key corporate
stakeholders as to the criti-
cal business imperatives that
depend on diversity and inclu-
sion and how subtle biases and
institutional barriers impede
progress. But just raising aware-
ness about bias is not enough—
this un­­derstanding needs to be
op­­erationalized into everyday
practice and leadership norms
in systemic ways, including
1) h elping managers lead
produc­t ive team meet-
ings where everyone can
contribute
2) examining subtle biases in
task assignment, perfor-
mance evaluation process-
es, and criteria for identify-
ing “high-potential” talent
3) examining flexible work poli-
cies, as the informal stigmas
or penalties that make these
policies difficult to use, even
when technically allowed.
fa l l 2 0 17 71
 “Universities are recognizing the importance
of partnerships and collaboration across
disciplines.”
Assessing recruiting sources, job ad
language, physical office space, and
décor is also important.
Companies should not expect that
these changes will occur overnight.
Reforming business processes takes
time, but the rewards are well worth it.
Innovation will be enriched, products
and services will address a wider range
of customer needs, talent pools will be
enlarged, and decision-making will be
more robust. Everybody in the com-
pany will benefit because, when cor-
porate cultures are improved for one
group, everyone benefits (Figure 5).
References
[1] T. Friedman, Thank You for Being Late: An
Optimist’s Guide to Thriving in the Age of
Accelerations. New York: Farrar, Straus,
and Giroux, 2016.
[2] A. Sengupta and D. Hodges, “Top-cited
IEEE Journal of Solid-State Circuits pa-
pers,” IEEE Solid State Circuits Mag., vol.
8, no. 4, pp. 30–31, 2016.
[3] K. Lawler. (2012, May). A new model for
venture investment in semiconductor
start-ups.” GSA Executive Forum. [On-
line]. Available: http://www.gsaglobal.
org/events/2012/0508/docs/siliconven-
tureskeynote_webversion.pdf.
[4] I. Akhmetshin. (2014, Aug.). The revival
of semiconductor funding. Techcrunch.
[Online]. Available: https://techcrunch.
com/2014/08/29/the-revival-of-semicon-
ductor-funding/
[5] J. Huang. (2016, Oct.). The intelligent in-
dustrial revolution. Nvidia. https://blogs.
nvidia.com/blog/2016/10/24/intelligent-
industrial-revolution/.
[6] N.P. Jouppi et. al, “In-datacenter perfor-
mance analysis of a tensor processing unit,”
in Proc. 44th Int. Symp. Computer Architec-
ture, Toronto, Canada, June 2017, pp. 1–12.
[7] Crunchbase database.
[8] H. Bauer, M. Patel, and J. Veira, (2015,
Oct.) Internet of Things opportunities and
challenges for semiconductor compa-
nies. Mckinsey Rep. [Online]. Available:
https://www.mckinsey.com/industries/
semiconductors/our-insights/internet-
of-things-opportunities-and-challenges-
for-semiconductor-companies
[9] T. Poletti. (2016, Aug.) Want to invest in
self-driving cars? Check out the chips.
Marketwatch. [Online]. Available: http://
www.marketwatch.com/story/want-to-
invest-in-self-driving-cars-check-out-the-
chips-2016-08-26
[10] C. Padnos. (2010). High performance en-
trepreneurs: Women in high-tech. Illumi-
nate Ventures. [Online]. Available: http://
www.txwsw.com/pdf/IlluminateWPSum-
mary6-10.pdf
[11] Wyckoff Consulting, LLC. (2013). U.S.
small business administration venture
capital, social capital and the funding of
72 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
women-led businesses. [Online]. Avail-
able: https://www.sba.gov/content/ven​
ture-capital-social-capital-and-funding-
women-led-businesses
[12] C. Herring, “Does diversity pay?,” Am. Soc.
Rev., vol. 74, no. 2, pp. 213, 2009.
[13] Lehman Brothers Center for Women in
Business. (2008). Innovative potential:
Men and women in teams,” London Busi-
ness School. [Online]. Available: https://
w w w.lnds.net/ blog/images/2013/09/
g r at ton r ep or t in nov at ive _ p otent ia l _
nov_2007.pdf
[14] A. W. Woolley, C. F. Chabris, A. Pentland,
N. Hashmi, and T. W. Malone, “Evidence
for a collective intelligence factor in the
performance of human groups,” Science,
vol. 330, no. 6004, pp. 686–688, 2010.
[15] L. Barker, C. Mancha, and C. Ashcra.
(2014). What is the impact of gender di-
versity on technology business perfor-
mance? Research summary, National
Center for Women in Informational Tech-
nology. [Online]. Available: https://www​
.ncwit.org/resources/what-impact-gen​
der-diversity-technology-business-per​
formance-research-summary
About the Authors
Terri S. Fiez is the vice chancellor
for research and innovation at the
University of Colorado, Boulder. Prior
to September 2015, she was head of
the School of Electrical Engineer-
ing and Computer Science at Oregon
State University, Corvallis. In 2008–
2009, she took a leave of absence to
cofound, launch, and serve as chief
executive officer of a solar electron-
ics start-up company. Her scholarly
interests focus on analog and mixed-
signal ICs for mobile communica-
tions and innovative approaches to
education. She has been recognized
with the National Science Founda-
tion’s Young Investigator award, the
2006 IEEE Educational Activities
Board’s Innovative Education award,
the 2016 IEEE Undergraduate Teach-
ing award, and the 2017 Hewlett-
Packard Harriett B. Rigas Award. She
is an IEEE Fellow.
Mar Hershenson is a cofounder
and managing partner at Pejman Mar
Ventures, a seed-stage investment
firm in Palo Alto, California. She
received her Ph.D. degree in electrical
engineering from Stanford Univer-
sity, California, and made her mark
as an entrepreneur by cofounding
three companies: Barcelona Design,
Sabio Labs, and Revel Touch. After
the acquisition of Sabio Labs, she
served as vice-president of product
development for Magma Design Auto-
mation’s Mixed Signal Division. She
has been honored by, among others,
the renowned T35 Young Innovator
Award by the Massachusetts Institute
of Technology, the prestigious Marie
R. Pistilli Women in EDA Achievement
Award in 2010, and the Midas Brink
List of Top Tech Investors in 2015.
Lucy Sanders is the chief execu-
tive officer and cofounder of the
National Center for Women and Infor-
mation Technology, housed in the
ATLAS Institute at the University of
Colorado, Boulder. She has an exten-
sive industry background, having
worked in research and development
and executive (vice-president) posi-
tions at AT&T/Lucent Bell Labs. In
1996, She w a s aw a r ded t he B ell
Labs Fellow award, the highest tech-
nical accomplishment bestowed
at the company. She serves as a
trustee for the Center for American
Entrepreneurship in Washington,
D.C., and the International Computer
Science Institute at the University
of California, Berkeley. She also has
six patents.
Catherine Ashcraft is a senior
research scientist with the National
Center for Women and Information
Technolog y at the University of
Colorado, Boulder. For the past
15 years, she has conducted research
and presented papers nationally and
internationally on issues related to
gender, diversity, information tech-
nology, and education. Her research
has been published by a number
of education and interdisciplinary
journals such as the American Edu-
cational Research Journal, Teachers
College Record, Anthropology & Edu-
cation, and Youth & Society. Her most
current work includes the recently
released reports Women in Tech: The
Facts and Male Advocates and Allies:
Promoting Gender Diversity in Tech-
nology Workplaces.

 Christian Enz, Francesco Chicco, and Alessandro Pezzotta

Nanoscale
MOSFET Modeling
Part 2: Using the inversion coefficient
as the primary design parameter

T
his article illustrates the use of the inversion coeffi-
cient (IC) as the main design parameter to explore the
various tradeoffs faced in the design of analog circuits.
We start with showing that the same transconductance,
gain-bandwidth (GBW) product, or input-referred ther-
mal noise resistance of a common-source (CS) amplifier can be achieved
with lower current by shifting the IC toward moderate inversion (MI) at
the cost of a slight increase of the transistor aspect ratio and area. In such
case the self-loading gate capacitance cannot be ignored, and accounting
for it introduces a minimum bias current at an IC that lies in the middle of
the MI to achieve a given GBW.
Various figures-of-merit (FoMs) are then introduced starting with the
current or transconductance efficiency G m /I D. It is shown that G m /I D is
maximum in weak inversion (WI) and that because of velocity saturation
(VS) more current is required in strong inversion (SI) to reach the same
transconductance than when VS is absent. The transit frequency Ft is then
derived as a function of the IC, and it is shown that it reaches a maximum
Ftpeak in SI that is inversely proportional to the VS parameter m c . It is also
shown that Ftpeak does not scale as 1/L and only depends on the ratio of
the oxide capacitance per unit area to the total extrinsic gate capacitance
per unit width. Finally the product G m /I D ·Ft FoM is introduced. The lat-
ter reaches a maximum in MI, offering a good tradeoff among gain, noise,
and current consumption. All the presented FoMs can be expressed versus
the IC using simple analytical expressions requiring only four parameters.
They are favorably compared to measurements of short-channel devices
from 40- and 28-nm bulk CMOS technologies and with the BSIM6 compact
model for the 40-nm device, illustrating the effectiveness of using the IC in
the design of analog circuits.

Introduction
The design of analog circuits is the art of finding the right tradeoff
between conflicting constraints or specifications such as power, noise,

image licensed by graphic stock

Digital Object Identifier 10.1109/MSSC.2017.2745838

Date of publication: 16 November 2017

1943-0582/17©2017IEEE IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 73

 In this second part, we will investigate how
this simplified EKV model can be used to
explore the various tradeoffs faced when
designing analog circuits.
linearity, gain, supply voltage, volt-
age swing, speed and input/output
impedance, as illustrated by Razavi’s
analog design octagon, shown in Fig-
ure 1 [1]. After having found the most
appropriate system architecture and
circuit, the designer finally needs to
select the right drain bias current,
channel width, and length for each
metal–oxide–semiconductor (MOS)
transistor [2]. These three indepen-
dent degrees of freedom for each
device influence their performance,
including bias voltages, dc gain, band-
width, noise, matching, and linear-
ity and hence have an impact on the
overall circuit performance [2].
Among all the transistor parame-
ters (current, width, length, and bias
Noise
Power
I/O Impedance
Speed
Figure 1: Razavi’s analog design octagon, illustrating the tradeoffs faced in the design of
analog circuits [1].
Ib Ib
W/L W/L
CL
Vout
Vin Vin
(a) (b)
Figure 2: CS gain stage schematics for the calculation of (a) constant G m, (b) constant GBW,
and (c) constant GBW including self-loading.
74 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
voltages), the overdrive voltage VG - VT0
has been used as a key design vari-
able for a long time. However, with
the down-scaling of complementary
MOS (CMOS) technology, the operat-
ing points of MOS transistors have
been progressively pushed toward
moderate or even WI (subthreshold
region), where the overdrive voltage
is not convenient anymore. To cover
the whole range of operating regimes
from WI to SI, we propose replac-
ing the overdrive voltage by the IC
describing the state of inversion of
the channel from weak via moderate
to SI.
The concept of IC was introduced in
the first part of this article [3], together
with the simplified charge-based
Linearity
Gain
Supply Voltage
Voltage Swing
Ib
W/L
W ⋅CW CL0
Vout Vout
Vin
(c)
Enz–Krummenacher–Vittoz (EKV) M O S
field-effect transistor (FET) model
that can be used to model devices in
saturation even in advanced CMOS
processes with only a few param-
eters including the effect of VS. The
model includes simple expressions
of the normalized (source) transcon-
ductance and the transconductance
efficiency G m /I D in terms of IC and
the VS parameter m c . Similarly, the
output conductance in saturation for
short-channel devices can also be
ex­­­­­­­p ressed in terms of IC and two
additional parameters m d and v d .
The model was validated on several
advanced bulk and fully depleted
silicon on insulator (FDSOI) CMOS
processes [3].
In this second part, we will inves-
tigate how this simplified EKV model
can be used to explore the various
tradeoffs faced when designing ana-
log circuits. Since much circuit per-
formance directly depends on G m
and/or G ds, it can be characterized
over a wide range of bias using the
expressions of G m and G ds.
Basic Tradeoffs in Analog IC Design
The transconductance, and hence
the current and area, of a single-
stage amplifier or a differential pair
is often dictated by the require-
ments on gain, GBW product, and
noise [4], [5]. Because the transcon-
ductance is proportional to the aspect
ratio W/L and increases with the
current, the same transconductance
can be achieved for different W/L
ratios and bias current. Hence, the
designer still has the degree of free-
dom to choose the appropriate IC at
which the device needs to be biased
to achieve a given transconductance.
It will be shown below that mov-
ing the operating point to MI or WI
actually comes with a reduction of
current at the cost of an increase in
area to achieve the same transcon-
ductance, GBW, or input-referred
thermal noise [4], [5]. To show this,
we will look at the simple CS stage
shown in Figure 2. We will inves­
tigate how the bias current I b and
a sp e c t r a t io W/L of a transistor
varies with IC for a given G m, GBW,
and input-referred thermal noise
resistance R n.
Constant-Gm
The transconductance of an MOS
transistor such as in the CS gain
stage shown in Figure 2(a) is propor-
tional to the transistor aspect ratio
W/L and depends on the bias cur-
rent I b. The latter can be reduced to
lower the power consumption, but
the aspect ratio has to be increased
to achieve the same transconduc-
tance, therefore increasing the tran-
sistor area. This tradeoff between
the bias current and the transistor
aspect ratio can be explored by
means of the IC using the defini-
tion of the normalized source trans­­
conductance g ms (IC ) given in [3]. The
gate transconductance G m can be
written as
I spec4 W
Gm = · ·g (IC ), (1)
nU T L ms
where W and L are the width and
l e n g t h o f t h e t r a n s i s t o r, n i s
the slope factor, and U T _ kT/q is
the thermodynamic voltage [3].
I spec4 _ 2nn 0 C ox U 2T is the specific
current per square, which is a fun-
damental parameter for a given
technology and type of transistor
(n- or p-channel), where n 0 is the
low field mobility in the channel
region and C ox the oxide capacitance
per unit area [3]. g ms is the normal-
ized source transconductance given
by [3]
From this perspective, MI turns out to
be a good tradeoff between low current
and acceptable area for achieving a given
transconductance.
I D = I spec ·IC = I spec4 · W ·IC.(3)
L
Solving (1) and (3) for I D and W/L
results in
I D = I b = G m ·nU T ·IC ,(4a)
g ms (IC)
W = G m ·nU T , (4b)
L g ms (IC) ·I spec4
which can be nor ma lized to the
desi r e d t r a n s con duc t a n ce G m
according to
Ib
ib _ = IC , (5a)
G m ·nU T g ms (IC)
I spec4
AR _ W · = 1 .(5b)
L G m ·nU T g ms (IC)
The normalized bias current i b
and aspect ratio AR are plotted in
Figure 3 for different values of the
VS parameter m c . It shows that the
same G m can be achieved with lower
current by shifting IC toward MI
and WI where i b saturates to unity.
This is obtained at the cost of a sig-
nificant increase of the transistor
aspect ratio (or of the transistor
width W for a fixed length L ) result-
ing in a drastic area increase. From
this perspective, MI turns out to be
a good tradeoff between low current
and acceptable area for achieving a
given transconductance [4], [5].
Constant Gain-Bandwidth Product
An important specification that deter-
mines the transconductance of single-
stage amplifiers as the CS amplifier
shown in Figure 2(b) is the GBW prod-
uct GBW or unity-gain frequency
~ u given by
~u =
G m = ~ · W ·g , (6)
L
CL L ms
where C L is the load capacitance
at the drain of the transistor and
~ L _ I spec4 / (nU T C L) is a normaliz-
ing quantity corresponding actually
to the GBW of a square transistor
biased in WI. If C L is assumed to
be constant, then (6) and (3) can be
solved for I D and W/L and normal-
ized to the desired GBW, result-
ing in
Ib
ib _ · 1 = IC , (7a)
I spec4 X g ms
AR _ W · 1 = 1 , (7b)
L X g ms
where X _ ~ u /~ L. Note that this nor-
malization leads to the same expres-
sions for i b and AR as in (5a) and
(5b), which are plotted in Figure 3.
Again, for achieving a given GBW
product, current can be saved by
moving the operating point toward
MI at the cost of a slight increase in

G ms
g ms _
G spec
100 100
(m c IC + 1) 2 + 4IC - 1
 = n·G m = , λc = 1
Normalized Bias Current ib

G spec m c (m c IC + 1) + 2
(2) λc = 0.3
Normalized W/L

10 λc = 0 10
where G spec _ I spec /U T = 2nn 0 C ox U T
and m c _ L sat /L is the VS param- λc = 1
eter corresponding to the fraction
1 1
of the channel in which the carrier λc = 0.3
drift velocity reaches the saturated
velocity v sat over a portion of the λc = 0
channel length L sat = 2n 0 U T /v sat [3]. 0.1 0.1
0.01 0.1 1 10 100
From the definition of IC given in Inversion Coefficient IC
[3], the drain current in saturation
can be written as Figure 3: The normalized current and W/L ratio versus IC for a constant G m and GBW.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 75

transistor width. Moving it further
toward WI does not gain much cur-
rent and costs a lot of area [4], [5].
The assumption that the load ca­­­
pacitance remains constant becomes
obviously erroneous as the transis-
tor gets wider. Indeed, since the
parasitic capacitance of the transis-
tor is proportional to the width W,
enlarging the transistor to move the
operating point to WI makes this
parasitic capacitance contribute sig-
nificantly to the load capacitance
at the drain. This can be accounted
for as illustrated in Figure 2(c) by
splitting the load capacitance into a
constant part C L0 (typically includ-
ing the wire capacitance and the
capacitance of the next stage) and
a part that scales proportionally to
the transistor width W
C L = C L0 + C w ·W,(8)
where C w is the self-loading capacitan­
­ e per unit width mostly due to overlap
c SI gets significantly larger with VS.
and fringing field capacitances. Equa-
tions (6) and (3) can then be solved for
i b and W/L accounting for (8), result-
ing in the following normalized cur-
rent and aspect ratio [6]–[8]:
ib _ ID · 1 =
I spec4 X
AR _ W · 1 = 1 , (9b)
L X g ms - lX
where l _ C w L/C L0 is the ratio of
the self-loading parasitic capaci-
tance of a square transistor (W = L)
100
Normalized Bias Current ib
κ=0
10
κ = 0.3
1 1
κ=0
0.1
0.01
Figure 4: The normalized current and W/L ratio versus IC for a constant GBW including self-loading capacitance: (a) without VS (m c = 0)
and (b) including VS.
76 fa l l 2 0 17
to the fixed load capacitance. Equa- thermal noise resistance R n given
tions (9a) and (9b) are plotted versus by [9]
IC for a constant GBW (X = 0.1) in
Figure 4(a) without accounting for Rn =
c nD
= nU T ·
c nD
, (11)
Gm I spec4 ·W/L g ms
VS (m c = 0) [6], [8]. It shows that the
current accounting for self-loading where c nD _ G m R n is the noise excess
(l = 0.3 and l = 1) now reaches a mi­­ factor, which is slightly bias depen-
nimum for an optimum IC given by dent for a long-channel transistor
and is typically comprised between
IC opt = 2lX (1 + lX)
 n/2 in WI and 2n/3 in SI. For short-
+ lX (1 + lX) (1 + 2lX) 2 .
channel devices c nD raises quickly
(10) in SI due to several short-channel
This is because when reducing IC effects but usually stays lower than
and at the same time increasing W 3 [9]. It can be approximated as [10]
leads to an increase of C L and hence
a reduction of ~ u that has to be com- c nD , 1 + a c ·IC (12)
pensated by an increase of the current
to maintain ~ u constant. The curves with a c , 0.07 [10]. Solving (11) and
in Figure 4(a) are without accounting (3) for I D and W/L and normalizing
for VS. Figure 4(b) shows i b and AR to the desired R n results in
for l = 0.3 and for different values of
c nD ·IC
m c . As expected, the impact of VS is i b _ I D ·R n = , (13a)
nU T g ms
negligible in WI whereas the required
R n ·I spec4 c nD
current to achieve the same GBW in AR _ W · = .(13b)
L nU T g ms
Notice that the optimum IC corre- The normalized bias current i b and
sponding to the minimum current i b aspect ratio AR given by (13) are
when VS is present is no more given plotted versus IC in Figure 5 for
by (10) and cannot be solved analyti- different values of m c and a c . It
cally, but (10) can still be used as a shows that the required current
first guess since IC opt is actually not for achieving a given R n in SI is sig-
IC , (9a)
g ms - lX much affected by VS as shown in Fig- nificantly larger in case of a short
ure 4(b) [7], [8]. channel device where both m c and
a c are different than zero. Moderate
Constant Input-Referred inversion is again a sweet spot for a
Thermal Noise balanced tradeoff between current
The transconductance can also be consumption and area for achieving
determined by the input-referred a given input-referred thermal noise.
100 100 100
κ = 0.3
κ=1 Ω = 0.1 Ω = 0.1 λc = 1
Normalized Bias Current ib
λc = 0 κ = 0.3
λc = 0.3
Normalized W/L
Normalized W/L
10 10 10
κ=1 λc = 0
λc = 1
1 1
λc = 0.3
λc = 0
0.1 0.1 0.1
0.1 1 10 100 0.01 0.1 1 10 100
Inversion Coefficient IC Inversion Coefficient IC
(a) (b)
IEEE SOLID-STATE CIRCUITS MAGAZINE
 The next section will show how
some FoMs can be used as design
guidelines using IC as the main va­­
riable to help designers choosing
the appropriate region of operation
for reaching their specs at the low-
est power.
FoMs as Design Guidelines
The Transconductance
Efficiency G m /I D
The transconductance efficiency
G m /I D FoM is one of the most impor-
tant performance metrics for analog
circuit design. It is a measure of how
much transconductance is produced
for a given bias current and is a func-
tion of IC. The transconductance
efficiency (or its inverse) appears
in many expressions related to the
power optimization of analog cir-
cuits. We actually already have seen
it (or the inverse) in expressions (5),
(7), and (13), derived, respectively,
for constant G m, constant ~ u, or
constant R n .
In the normalized form, the trans-
conductance efficiency is defined as
the actual gate transconductance
obtained at a given IC with respect
to the maximum transconductance
G m = I D / (nU T ) reached in WI [7]
g ms
= G m ·nU T
IC ID
 0.01
(m c IC + 1) 2 + 4IC - 1 (14)
IC· 6m c · (m c IC + 1) + 2@
= .
The expression in (14), which is con-
tinuous from WI to SI and includes the
effect of VS, is plotted in Figure 6. The
figure shows the behavior of g ms /IC
for long-channel devices in which VS
is absent which scales as 1/ IC in SI
(dashed blue curve). For short-chan-
nel devices subject to VS, the drain
current becomes a linear function of
the gate voltage, independent of the
transistor length. Hence, the trans-
conductance becomes independent
of the current and length. Since G m
becomes independent of I D or IC,
the G m /I D curve scales like 1/ (m c IC)
in SI instead of 1/ IC when VS is
absent. In essence, the effect of VS
is to degrade the transconductance approximation of Ft is given by
efficiency in SI, meaning that more [9], [11]
current is required to reach the same
transconductance obtained without Ft = G m , (15)
2rC G
VS. Nevertheless, irrespective of
the channel length, G m /I D remains where C G = C Gi + C Ge is the total gate
invariant (i.e., g ms /IC = 1) in WI, capacitance comprising the intrin-
since short-channel effects, includ- sic capacitance C Gi, which is linked
ing VS, have the same effect on G m to the mobile charges in the chan-
than on I D simply because G m is pro- nel, and the extrinsic capacitance
portional to I D in WI. C Ge = C GeW ·W, including the overlap
and fringing field capacitances as
The Transit Frequency Ft shown in Figure 7, which scale with
The transit frequency Ft is defined as the transistor width W. Since both
the frequency at which the extrapo- G m and C Gi, are bias dependent, Ft
lated small-signal current gain of the is bias dependent too. Its variation
transistor in CS configuration falls with respect to IC is shown in Fig-
to unity [9]. Ft is a widely used met- ure 8. In WI, the mobile charges are
ric for characterizing the high-fre- few and the intrinsic gate capacitance
quency behavior of a MOSFET because is negligible compared to the ex­­
many performances, such as the gain trinsic capacitance so that C G , C Ge .
at RF and the minimum noise factor, The bias dependence in WI is mostly
are directly linked to Ft [9]. A good coming from G m. Since in WI G m ? I D
100 100
λc = 0.3, αγ = 0.07
Normalized Bias Current ib
λc = 0.3, αγ = 0
Normalized W/L
10 λc = 0, αγ = 0 10
1 1
λc = 0.3, αγ = 0.07
λc = 0.3, αγ = 0
λc = 0, αγ = 0
0.1 0.1
0.1 1 10 100
Inversion Coefficient IC
Figure 5: The normalized current and W/L ratio versus IC for a constant input-referred
thermal noise resistance R n .
1
0.5
Gm . n . UT /ID
1/
0.2
IC /(λ CI
1
0.1
C)
0.05 Without VS
1/λC 2
With VS 1/λC
0.02
0.001 0.01 0.1 1 10 100
IC
Figure 6: g ms /i d versus IC showing the long and short channel asymptotes.
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 77

CGf
Cif C
ov Cof
CGo
Figure 7: The extrinsic gate capacitances
made of the overlap capacitance C G O and
the fringing field capacitance C G f .
and hence G m ? IC, Ft is therefore
also proportional to IC.
Similarly to G m /I D, Ft can be no­­
r­
malized as shown in Figure 8 to
Ftspec defined as the value of Ft on
the WI asymptote corresponding to
IC = 1 [12]. In this way, the normal-
ized transit frequency ft _ Ft /Ftspec
turns out to be equal to g ms, which
is given by (2). Note that Ftspec scales
roughly as 1/L [12]
WLC ox
Ftspec = Fspec ·
CG
WLC ox
, Fspec ·  Both G m /I D and Ft are very impor-
C Ge
I spec4
= ,
2rnU T C GeW L
where Fspec _ 2n 0 U T / (2rL2) .
As illustrated in Figure 8, in SI
and under VS (i.e., for 1/m 2c 1 IC ), Ft
(or ft in normalized form) saturates
to Ftspec /m c (or 1/m c in normalized
form). When increasing the channel
length, i.e., for lower values of m c, the
value of Ft at which VS starts, moves
to higher values and there is a region
between IC = 1 and IC = 1/m 2c where defined as the product of the two
Ft follows the SI asymptote IC . formerly defined metrics comes into
Note that once the VS param- the picture. Combining two quanti-
eter is extracted from the G m /I D as ties that have their maxima on the
described in [3], it is therefore easy to opposite ends of the IC axis, the
assess the peak Ft for a given technol- G m /I D ·Ft FoM [13] serves as design
ogy from Ftspec. It is also interesting guide to locate the optimum IC.
to point out that the denormalized It can be justified from the small-
value of the saturation value of Ft is signal voltage gain of the CS stage
given by [12] shown in Figure 9, which is given by
Ftspec WC ox v sat DVout Gm ZL ~
Ftpeak = = Av = =- ,- u,
mc 2rC G DVin 1 + ~R S C GS ~
  (18)
C ox (17)
, v sat · ,
2rC GeW
where ~ u = ~ t ·Z L /R S is the unity-
which shows that, surprisingly, Ftpeak gain frequency and G m /C GS has been
does not scale as 1/L anymore [12]. approximated by the transit frequency
This means that the only way to in­­­ ~ t . It can be shown that the noise fac-
crease Ftpeak is to increase C ox but tor NF, neglecting the noise of the bias
without increasing C GeW [12]. This current source, is given by
observation could explain the recent
c nD
slow down of the peak transit fre- NF = 1 + . (19)
Gm RS
quency progression witnessed in re­­
cent years. An FoM can be defined such that
it maximizes the unity gain band-
The G m /I D ·Ft FoMs w idth ~ u while minimizing the
added noise NF - 1 and the bias cur-
tant FoMs from an analog/RF design rent I b
(16)
perspective: the former character- ~u
FoM RF _
izes the dc performance of a device (NF - 1) ·I b
G ·~
while the latter characterizes its = ZL · m t , (20)
R S ·c nD Ib
high-frequency performance. How-
ever, as is clear from Figures 6 and 8, which is proportional to the prod-
there exists a fundamental tradeoff uct of G m /I b and Ft . Neglecting the
between the two. Aiming for low- bias dependence of c nD, this prod-
power operation by targeting a high uct can be expressed in terms of IC
G m /I D at small values of IC invari- using the normalized G m /I D ·Ft FoM
ably means compromising in speed defined as [7]
(bandwidth). This is where the FoM
g ms ·ft
fom rf _ , (21)
IC

Ft (ft ) where ft _ g m /c g is the normalized

IC transit frequency with g m _ G m /G spec
Ft spec 1 ∝
Ft peak = and c g _ C G / (WLC ox). As shown in
λC λC
Ft spec (1)

Ib
IC
∝

RS
M1
CGS Vout Z
IC Vin L
0.01 0.1 1 1 10 1 100
λC λ2C

Figure 8: The transit frequency Ft versus IC showing the definition of Ftspec . The variables in Figure 9: The CS amplifier used for deriva-
parenthesis correspond to the normalized transit frequency. tion of the G m /I D ·Ft FoM.

78 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 Figure 10, fom rf shows a peaking
behavior [13] that makes it useful
10 for locating the optimum IC, which
λC = 0 is due to the asymptotic behavior of
λC = 1/3 two quantities that it incorporates
[7], [14]. This maximum is located
fomrf = gms/id · ft

1
∝ approximately at IC , 1/m 4c /3. What
IC 1/
∝ IC is even more interesting is that this
peak lies at the higher end of the MI
0.1 IC region for the contemporary CMOS
∝

technologies and moves deeper into

the MI region with decreasing chan-
nel lengths, as shown in the bottom
0.01
0.01 0.1 1 10 100 plot of Figures 11 and 12. It is worth
noting that the peaking behavior of
1 1 1 this FoM is caused by the degrada-
2
λC (λC) 4/3 λC tion of G m and G m /I D in SI due to
Inversion Coefficient IC VS [14]. In the absence of VS, in SI,
G m (consequently Ft ) and G m /I D
are respectively proportional to
Figure 10: The normalized FoM fom rf (on a log scale) as a function of IC , along with I D and 1/ I D , implying that the
the WI and SI asymptotes. The peak of the FoM lies at the intersection of IC and 1/ ^ m 2c IC h FoM would simply saturate in this
asymptotes. region as shown by the blue dashed

1
1 W = 108 µm
W = 108 µm ∝1
L = 31 nm IC
L = 40 nm
∝
gms/id

n = 1.46 1/
gms/id

n = 1.48 IC
0.1 Ispecsq = 870 nA
0.1 Ispecsq = 650 nA Ispec = 3.9 mA
Ispec = 2.1 mA
Lsat = 20.2 nm
Lsat = 19.5 nm
λc = 0.6516
λc = 0.4875
0.01 0.01

10 10
ft sat = 1/λc = 2.05 ft sat = 1/λc = 1.5

1 1
Ft spec = 128.4 GHz Ft spec = 226.6 GHz

0.1 0.1 IC
ft

∝
ft

C
0.01 0.01 ∝I
CGeW = 640 pF/m CGeW = 670 pF/m
0.001 0.001
1 1
∝
1/
IC
0.1 0.1 C
∝I
fomrf

fomrf

1/λc = 2.05
1/λc = 1.53
2
0.01 1/λc = 4.21 0.01
2
1/λc = 2.36
4/3 4/3
1/λc = 2.61 1/λc = 1.77
0.001 0.001
0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100
Inversion Coefficient IC Inversion Coefficient IC
Measurements BSIM6 Theory
Measurements Theory

Figure 11: g ms /i d , ft , and fom rf versus IC for a 40-nm device [12]. Figure 12: g ms /i d , ft and fom rf versus IC for a 30-nm device [12].

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 79


This article illustrates the use the IC as the
main design parameter to explore the various
tradeoffs faced in the design of analog circuits.
1.0
0.8
NFmin (dB)
0.6
0.4
0.2
0.0
0.1
Figure 13: Minimum noise figure versus IC [11], [17].
line in Figure 10 and there would be
no maximum.
Note that this FoM was succes­
sfully used by [15] to design an
ultra low-power low-noise ampli-
fier (LNA).
Experimental Results
The three FoMs presented previ-
ously are plotted versus IC in Fig-
ure 11 and in Figure 12 for a 40- and
a 30-nm RF device from a 40- and
28-nm bulk CMOS process, respec-
tively [12]. Despite their simplicity
and reduced number of parameters,
the analytical models fit the experi-
mental data very well over almost
five decades of IC (current). The
small discrepancy for the last mea-
surement point in SI is due to mobil-
ity reduction due to the vertical
field [9], which is not accounted for
in the simple model. However, this
effect is accounted for in the BSIM6
compact model [16], which perfectly
fits the measured data in Figure 11,
including at high IC.
Other FoMs
Other FoMs can be defined and ex­­
pressed in terms of IC. For example,
80 fa l l 2 0 17
at 14 GHz
at 10 GHz
Measurements
Analytical Model
BSIM6
1 10 100
IC
the minimum noise figure NFmin,
which gives the minimum noise
that can be achieved under proper
impedance matching conditions, also
shows a minimum at the higher end
of MI as shown in Figure 13 [11], [17].
Another example is used for the de­­
sign of low-power oscillators. An
FoM including the phase noise at a
given offset frequency, the power
consumption, and the oscillation
frequency can be defined. The latter
has been evaluated for Pierce and
cross-coupled oscillators and shows
a maximum also at the edge of MI
and WI [18], [19].
Conclusions
This article illustrates the use the
IC as the main design parameter to
explore the various tradeoffs faced
in the design of analog circuits. It
can help the designer to select the
most appropriate IC setting the cur-
rent and the W/L ratio. This is illus-
trated by looking at the simple CS
gain stage. It is shown that the same
transconductance, GBW, or input-
referred thermal noise resistance
can be achieved with lower current
by shifting the IC toward MI at the
IEEE SOLID-STATE CIRCUITS MAGAZINE
cost of a slight increase of the tran-
sistor aspect ratio and area.
A minimum bias current can
be found at an IC that lies in the
middle of the MI to achieve a given
GBW product when accounting for
the self-loading capacitance at the
drain. This current can be signifi-
cantly less than the current required
to achieve t h e s a m e t r a n s c o n -
duc t a nce, GBW or input-referred
thermal noise resistance in SI, par-
ticularly under VS. Different FoMs
are then introduced, starting with
the transconductance or current
efficiency G m /I D, which tells how
much transconductance is obtained
for a given current. G m /I D is maxi-
mum in WI and decreases as 1/ IC
in SI for long channel devices and as
1/ (m c ·IC) for short-channel transis-
tors because of VS. Another FoM key
to evaluate the RF performance of a
device is the transit frequency Ft . It
is shown that Ft follows a behavior
opposite of G m /I D, namely increas-
ing with IC to reach the maximum
Ftpeak in SI because of VS. It is shown
that Ftpeak is simply inversely propor-
tional to the VS parameter m c and
that does not scale as 1/L but is sim-
ply proportional to the ratio of the
oxide capacitance per unit area and
the total extrinsic gate capacitance
per unit width.
Another FoM is introduced as the
product G m /I D and Ft that helps max-
imizing the GBW, while minimizing
the added thermal noise at a given
bias current, which turns out to be
useful for choosing the right operat-
ing point of RF circuits such as LNAs.
It is shown that the G m /I D ·Ft FoM
reaches a maximum in MI offering
a good tradeoff between gain, noise
and current consumption.
All these FoMs can be expressed
versus IC using simple analytical
expressions that fit experimental data
very well despite requiring only four
parameters: n, I spec4, L sat, and C GeW .
All the presented FoMs are ­favorably
compared to measurements of short-
channel devices from 40- and 28-nm
bulk CMOS technologies and with the
BSIM6 compact model for the 40-nm
device, illustrating how powerful the
concept of the IC can be.
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[2] D. Binkley, Tradeoffs and Optimization in
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About the Authors
Christian Enz (christian.enz@epfl
.ch) received his Ph.D. degree from
the Sw iss Federa l Instit ute of
Technology (EPFL) in 1989. He is
c u r rently a professor at EPFL, direc-
tor of the Institute of Microengi-
neering, and head of the IC Lab.
Until April 2013, he was vice presi-
dent at the Swiss Center for Electron-
ics and Microtechnology (CSEM),
Neuchâtel, Switzerland, where he
headed the Integrated and Wireless
Systems Div ision. Before joining
C SE M , h e was a pr incipa l senior
engineer at Conexant (formerly
Rockwell Semiconductor Systems),
Newport Beach, California, where
he was responsible for the modeling
and characterization of MOS transis-
tors for RF applications. His techni-
cal interests and expertise are in
the field of ultralow-power analog
a n d R F IC desig n , wireless sen-
sor networks, and semiconductor
device modeling. Together with E.
Vittoz and F. Krummenacher, he is
the developer of the EKV MOS tran-
sistor model. He is the author and
coauthor of more than 250 scien-
tific papers and has contributed to
IEEE SOLID-STATE CIRCUITS MAGAZINE
numerous conference presentations
and advanced engineering courses.
He is a member of the Swiss Acad-
emy of Engineering Sciences. He
was a member of the IEEE Solid-State
Circuits Society (SSCS) Administra-
tive Committee from 2012 to 2014.
He is also the chair of the IEEE SSCS
Chapter of Switzerland.
Francesco Chicco received his
B.Sc. degree in physical engineer-
ing from the Polytechnic University
of Turin, Italy, in 2013 and his M.Sc.
degree in micro and nanotechnolo-
gies for integrated systems from the
Polytechnic University of Turin, Italy,
the Grenoble Institute of Technology,
France, and the Swiss Federal Insti-
tute of Technology (EPFL), Lausanne,
Switzerland, in 2015. Since 2015, he
has been working toward a Ph.D.
degree as a member of the IC Lab
at EPFL. The focus of his work is on
the analysis and design of low-power
analog and RF integrated circuits for
wireless communications.
Alessandro Pezzotta received
his M.Sc. and Ph.D. degrees in solid-
state physics from the University of
Milano-Bicocca, Italy, in 2012 and
2015, respectively. During his Ph.D.
study, he developed a mixed-signal
CMOS front-end ASIC devoted to the gas-
electron multiplier detector readout,
employed in neutron beam monitor-
ing applications. He also participated
in R&D activities regarding CMOS
continuous-time analog filters and
sensor analog front ends. In 2016, he
joined the IC Lab at the Swiss Federal
Institute of Technology as a scien-
tist, where he works on semiconduc-
tor device modeling, especially in
design methodologies based on the
inversion coefficient in terms of dc
characteristics, linearity, noise, and
RF performance, while also targeting
radiation-tolerant applications. He
has published more than 20 scien-
tific papers.

fa l l 2 0 17 81
 Payam Heydari

Neutralization
Techniques for
High-Frequency
Amplifiers
An overview

Background art—footage firm, inc.

N
eutralization tech-
niques to miti­gate
the oscillatory cur-
rents/voltages in
amplifiers due to
instability goes as far back as the era
of vacuum tube amplifiers. For instan
ce, in U.S. patent 1,334,118, granted
on 16 March 1920 to C.W. Rice, it was
observed that “under certain conditions,
a device employing an incandescent
Digital Object Identifier 10.1109/MSSC.2017.2745858
Date of publication: 16 November 2017
cathode, an anode, and a grid produces
oscillatory currents in the circuits as­­
so­­ciated therewith and in some cases
the oscillatory currents so produced
interfere with the efficient reception,
amplification and detection of the sig-
nals to be received.” It then goes on by
stating that “in order to compensate for
the coupling due to the natural capac-
ity between the grid 10 and anode 11
in Figure 1(a), which is represented by
the dotted condenser 12, an electromo-
tive force, equal and opposite to that
impressed, is applied to the grid circuit
through the condenser 13, upon the grid
from the anode 11 across the capacity
12.” [See Figure 1(a).]
The same phenomenon was later
observed in transistor amplifiers. For
example, the U.S. patent 2,901,558,
granted on 25 August 1959 to R.R.
Webster “relates to semiconductor
amplifier circuits and more particu-
larly to a method of neutralizing the
effects of interelectrode capacitance
in semiconductor amplifier devices.”
Next, it introduces “a neutralization
circuit, where the feedback network

82 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

is connected between a secondary
coil of the output transformer of the
amplifier circuit and the primary coil
of the input transformer of the ampli-
fier circuit.” [See Figure 1(b).]
The reemergence of silicon-based
millimeter (mm)-wave ICs in radio
transceivers due to an ever-increas-
ing demand for bandwidth in high
data rate wireless applications has
recreated great interest in neutral-
ization techniques in the context of
low-noise wideband amplifier design.
Tuned Amplifiers
The baseband signal associated
with a mobile user in wireless trans-
ceivers is bandlimited. Therefore,
the RF modulated signal has a band-
pass characteristic. To amplify this
band-pass signal, while filtering the
(a)
Figure 1: Circuit schematics of (a) U.S. patent 1,334,118, “System for Amplification of Small Currents,” and (b) U.S. patent 2,901,558, “Tran-
sistor Amplifier Circuits.”
undesired out-of-band interference,
radio-frequency (RF) amplifiers em­­
ploy a bandpass filter (BPF) tuned
at the RF signal’s carrier frequency.
Figure 2(a) shows the general block
diagram of an RF amplifier with a
BPF load. The input/output match-
ing circuits are used to facilitate
maximum power transfer from the
source to the amplifier’s input and
from the amplifier’s output to the
load, respectively.
A simple BPF circuit is realized
with a lossy LC tank circuit where
the loss is represented by the induc-
tors’ Q-factor (Q L = R L / (L~ 0)) . The
core amplifier, in general, is not uni-
lateral where the parasitic capacitors
of the transistor(s) contribute to non-
zero reverse transmission. In prac-
tice, it is commonly known that this
IEEE SOLID-STATE CIRCUITS MAGAZINE
nonzero reverse transmission may
cause stability issue in a tuned ampli-
fier. To find out why this is the case,
we study the input admittance of a
generic tuned amplifier in Figure 2(b).
The core amplifier is represented by
its two-port model, depicted in Fig-
ure 2(c), where the voltage across its
input parasitic capacitance controls
a voltage-controlled current source,
G m Vi . The output parasitic capaci-
tance C O of this amplifier is absorbed
in the load capacitance to constitute
an overall capacitance, C, as indi-
cated in Figure 2(c). Solving the I-V
equations for the input admittance
Ydrv yields
Ydrv ^~h = j~C I + j~C F c
YRLC + G m m
.
YRLC + j~C F
(1)
(b)
fa l l 2 0 17 83

|HBPF(ω)|
ω CF
ωRF
BPF
Core Amp.
(a)
Figure 2: (a) A general block diagram of a tuned RF amplifier. (b) A general schematic of a tuned amplifier with a tank RLC load. (c) The two-
port model of an amplifier with a tuned RLC tank load.
YRLC in (1) represents the admit-
tance of the RLC (resistor, capacitor,
and inductor) tank, which is expressed
as YRLC = G L + j (C~ - 1/L~). The sus-
ceptance associated with the feedback
capacitance C F appears in the second
term of the input admittance. The sec-
ond term has a real and an imaginary
part, G in = Re [Yin] and B in = Im [Yin],
which are calculated to be
B F (G m + G L) + B RLC G m
G in = BF
G L2 + (B RLC + B F ) 2
G (G + G ) + B RLC (B RLC + B F )
B in = L m 2 L
 B F.
G L + (B RLC + B F ) 2
(2)
According to (2), the susceptance
B F of the feedback capacitan­­ce bears
two key contributions on the con­­­
duc­­tance and susceptance of the in­­
put admittance.
First, we study the B F effect on
the conductance, G in . The tank sus-
ceptance, B RLC , becomes negative for
frequencies lower than the tank re­­
sonance frequency ~ 0 (= 1/ LC ).
Over this frequency range, if
CF 1 G m R L C , (3)
G m R L + 1 eff
where
C eff = ;`
~ 0 j2
- 1E C,
~
then the conductance G in will be­­
come a negative quantity. The in­­
equality in (3) is easily satisfied at
RF and mm-wave frequencies as the
tank capacitance is typically much
larger than the feedback capacitance,
itself predominantly contributed by
84 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
VDD
L, QL CL
+
Vi
– CI
Ydrv
Core Amp.
(b)
the parasitics of the transistor [e.g.,
C GD in a metal–oxide–semiconduc-
tor (MOS) device or C n in a bipolar
transistor]. If an RLC circuit (i.e.,
input-matching circuit) is present at
the input port, it is possible for the
energy provided by the negative input
conductance of this amplifier to sup-
ply all the energy loss associated with
the loss of the matching circuit. If
this happens, a lossless LC circuit will
appear at the input port and the cir-
cuit begins to oscillate. The feedback
capacitance thus makes the amplifier
potentially unstable.
Second, an inspection of B in in
(2) reveals that the feedback capa­­
citance appears across the input
port as an equivalent capacitance
C eq = M (~) C F . M represents a frequ­
ency-dependent scaling factor, which is
derived to be:
M ^~h = 1 + Gm RL , (4)
1 + (R L C eff ~) 2
It is noted that M essentially pre­­
sents the generalized high-frequen­
­cy version of Miller coefficient. The
tank load affects the input reactance
through this Miller capacitance. There-
fore, the feedback capacitance couples
the output load back onto the ampli-
fier’s input admittance. The design of
input matching circuit for conjugate
matching should thus account for this
parasitic reactance.
Complementa r y M O S (C M O S )
common-source or bipolar common-
emitter amplifiers are obvious exam-
ples where the gate-drain overlap or
VDD
L, QL C
C = CL+ CO
GmVi
(c)
base-collector parasitic capacitances
cause nonzero reverse transmissions.
Therefore, techniques that neutralize
the effect of these capacitances in
the circuit are of great interest. To
help the flow of this article, the fol-
lowing discussion concentrates on
CMOS amplifiers. However, the same
principle can also apply to the bipo-
lar counterparts.
Neutralization Techniques
Neutralization techniques ­primarily
­cancel detrimental effects, described
in the “Tuned Amplifiers” section,
associated with parasitic feedback
capacitance in an amplifier. If the
design constraints allow, the most
straightforward approach is to em­­ploy
topologies with no direct capacitive
feedback from the input to the output
of the amplifier. One widely known
topology is the cascode configuration.
As will be explained in the “Cancella-
tion of the Capacitive Feedback” sec-
tion, an RF cascode amplifier at very
high frequencies loses its promised
advantages. The neutra­lization tech-
niques thus pr ov ide a powerful
pathway for stabilizing am­­plifiers at
high frequencies.
Cascode Topology
One topology that provides isola-
tion between the input and output,
thus giving rise to an uncondition-
ally stable amplifier, is the cascode
topology. Figure 3(a) shows the basic
schematic of a tuned cascode ampli-
fier. If being utilized as a low-noise
 VDD

VDD VDD
RB2 L, Q

RB2 L, Q RB2 L, Q LGG

C
M2

ZP
C C P
CGD1
CP
M.N. M.N.
M1

RB1 RB1
LS

1
Re[ZP] = (1 – LGGCGS2ω 2)
VB1 VB1 gm 2
(a) (b) 1
For ω > Re[ZP] < 0
√LGGCGS2

Figure 3: (a) The general circuit schematic of a tuned cascode amplifier. The input match- Figure 4: The core cascode circuit with para-
ing (M.N.) is shown as a black box driving this amplifier. (b) The circuit schematic of a tuned sitic capacitance CP, the gate-drain capacitance
cascode amplifier with inductive degeneration to provide noise-free input matching. CGD, and the parasitic capacitance LGG included.

amplifier, inductive degeneration is

commonly employed to provide a
noise-free input impedance match-
ing [1], as shown in Figure 3(b). At low
RF frequencies, a cascode topology
has larger output resistance com-
pared to a common-source configu-
ration, making it possible to achieve
higher gain. In addition, the noise
contribution of the common-gate
transistor to the overall noise figure
is negligible because this transis-
tor sees a large source-degenerated
resistance (i.e., ro1 of the common-
source device [2]).
Unfortunately, all these advan-
tages will fade away at high frequ­
encies toward mm-wave frequency
range where the external passives
are in the range of device parasitics.
For instance, the overall capacitance
C P at the cascode node, shown in
Figure 4, starts lowering the overall
impedance at this node at high fre-
quencies. This means that the noise
contribution of the common-gate de­­­
vice to overall noise figure is no longer
assumed to be negligible. In fact, at
near-fmax frequencies (loosely de­­fined
as frequencies around and above half-
fmax ), the noise figure of the cascode
topology may worsen the noise figure
by as much as 3 dB.
VDD VDD
RB2 L, Q RB2 L, Q
C C
M2 M2
CBY,1 CBY,1
LC
LP M1
M1
CBY,2
(a) (b)
Figure 5: An interstage inductor to lower the noise contribution of the common-gate transis-
tor in a cascode stage. (a) Parallel inductor LP and (b) series inductor LC.
One way to alleviate this issue is junctions of the common-source and
to place a series [3] or parallel induc- common-gate transistors are shared.
tor [4] to partially resonate out C P These shared drain and source junc-
[cf. Figure 5(a) and (b)]. The paral- tions must inevitably be separated
lel inductor in Figure 5(a) creates a apart if the series interstage induc-
band-limited high impedance at the tor, L C , is to be used. This separa-
resonance frequency, whereas the tion of junction regions leads to
series inductor in Figure 5(b) cre- additional parasitics at the inductor’s
ates a wideband interstage filter, terminals. In addition, when consid-
extending the roll-off at the cascode ering the inductor’s parasitics, the
node to higher frequencies. For a CMOS usefulness of L C in extending the
cascode stage, the drain and source bandwidth and lowering the noise

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 85

 Node 1 Node 2 –∆V + +
∆V
– +
– + – ∆V – –
V1 V2 – +
CF V1 – ∆V1 +++ CF V1
Cin CF ∆V – ∆V
Cin ∆V1 = ∆V – ∆V1 ∆V1
CF + Cin CX CF
Cin

(a) (b)

Figure 6: The conceptual circuit to demonstrate the underlying idea behind the neutralization technique.

contribution of the common-gate
transistor on the overall noise figure
becomes unclear.
Moreover, the parasitic induc-
tance L GG of the bypass capacitor
and interconnects (Figure 4) con-
nected to the gate of a cascode de­­
vice can degrade the stability factor
of the amplifier. In fact, this induc-
tor induces a negative resistance
at the cascode node at frequencies
below the resonance frequency of
this inductor and the equivalent
capacitance seen from the gate ter-
minal, as also indicated in Figure 4.
Finally, at high frequencies, the
parasitic gate-drain capacitance
C GD1 of the common-source transis-
tor in a cascode configuration estab-
lishes a feed-forward path from the
input of this common-source stage
to its output. The signal travel-
ing through this path destructively
combines with the signal amplified
by the common source, as shown in
Figure 4. The effective gain of this
stage is thus compromised. Moreover,
the real part of the output im­­pedance
of a source-degenerated c a sco de
amplifier becomes smaller than that
of a common-source counterpart
because the intermediate node P
becomes a short at high frequencies.
This, in turn, further lowers the cas-
code power gain.

VDD
VDD Cancellation of the
Capacitive Feedback
L, Q C
L, Q As described above, the cascode
VS topology, while providing unilateral
M.N.
gain, entails several drawbacks at
M.N. C R VS
S RB1 CB high frequencies. This notion calls
RS RB1 VBIAS for techniques that retain the origi-
VB1 nal amplifier topology and surround
VB1 the amplifier with a network which
(a) (b) cancels the feedback capacitance.
To understand the principle of
Figure 7: The use of a mutually coupled inductor for neutralization of the feedback capaci- neutralization technique, consider
tor. The neutralization is realized between (a) the drain and gate and (b) the source and gate the arrangement in Figure 6, where
of a common source amplifier. the floating and grounded capacitors
C F and C in exemplify the feedback
capacitance and the amplifier’s input
VD capacitance, respectively. A negative
CGD voltage drop at node 2 will induce a
(1–k )L (1–k )L CN negative voltage drop at node 1 due
CGD 1:1
to the presence of C F . To keep node 1
(1–k )L (1–k )L
kL CN 1:1 quiet, an opposite charge needs to be
VG created to cancel the delta-charge on
VG kL the upper and left plates of capacitors
L = LT /2 C in and C F , respectively. This can be
L = LT /2
accomplished by sampling the delta-
(a) (b)
voltage across C F and producing its
inverse with the aid of an inverting
Figure 8: The circuit models for neutralized amplifiers in Figure 7(a) and (b). The circuit
model employs a T-section model followed by ideal transformer to model the center-tapped voltage-controlled voltage source and
inductor. (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for the apply this delta-voltage to a capacitor
amplifier in Figure 7(b). C X [see Figure 6(b)]. Assuming equal

86 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

capacitances, C P = C X , the voltage at
node 1 will then remain quiet. VD
We use the aforementioned gen- CGD
eral principle to develop neutral- (1–k )L (1–k )L CN YL
CGD 1:1
izing networks around the main (1–k )L (1–k )L
1:1
amplifier. Noting that the transistor YL k L CN
is essentially a multiterminal com- VG
VG kL
ponent, this neutralizing network L = LT /2 L = LT /2
can be placed between the output
terminal (typically drain or collec- (a) (b)
tor) and any of the remaining two
terminals to cancel the feedback Figure 9: The circuit models for neutralized amplifiers with load admittance YL in Figure 7
parasitic capacitance. Shown in Fig- (a) and (b). (a) The circuit model for the amplifier in Figure 7(a), and (b) the circuit model for
the amplifier in Figure 7(b).
ure 7 are two examples in which the
neutralization is realized by forming
a passive feedback between drain
and gate [5], as in (a), or between the
drain and source [6], as in (b).
CN CN
In both examples, the neutraliz-
ing capacitor is realized using the
VS VS
gate-drain overlap region of an MOS
– +
device to ensure that its structure + –
resembles that of the gate-drain
overlap capacitance of the main
common-source transistor. There-
fore, they exhibit the same behavior
in the presence of process and tem-
perature variations. Also, in both
VDD
circuits, a center-tapped inductor is
employed to generate voltage pha-
sors of opposite signs at its up and L, Q L, Q
bottom terminals. Assuming an ideal
M.N. M.N.
magnetic coupling (i.e., k = 1) and – +
C C
equal loading on both sides of the CN CN
center-tapped inductor, the neutral-
VS VS
izing capacitance should be equal to
the parasitic gate-drain capacitance. + –
M.N. M.N.
However, in practice, the coupling
coefficient, k, is less than unity. k
will get closer to unity at very high
frequencies where a center-tapped ISS
one- or half-turn folded microstrip
line can produce the required induc-
tance. Figure 8(a) and (b) shows the Figure 10: Neutralization in differential amplifiers. A pair of cross-connected capacitors will
equivalent circuits, replacing mutu- neutralize the feedback parasitic capacitance.
ally coupled inductors in the cir-
cuits of Figure 7(a) and (b) with a
T-section equiv a lent model [7 ]. practice, however, the two sides between these two quantities. Using
With equal loadings, if the T-section of the center-tapped inductor a r e the eq­­­uivalent circuit in Figure 8(a)
model is excited from its two sides loaded by the unequal impedances. and (b), straightforward I-V equations
by a differential voltage, the circuit Figure 9(a) and (b) replicates Figure 8(a) reveals that DV1 - DV2 is calculated
will remain balanced for C N = C GD . and (b), while including the load admit- to be
As mentioned earlier, neutraliza- tance YL . Ideally, the voltage changes
tion occurs completely if the termi- DV1 and DV2 should have the same DV1 - DV2 =-~ 2 LC N (1 - k)
nal voltages of the center-tapped magnitude and opposite phase. Nev- N 
# V e j (+NV -+DV ) (5)
inductor r em a in dif fer ential. In ertheless, YL creates phase mismatch DV

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 87

 VDD = 1.8 V

L Ls = 100 pH
1 : 1.95 CL CBY
L = 320 pH
LGG = 450 pH
RL = 50 Ω
(W/L)1 = 28.8 µm/180 nm
CBY LGG 0.89 : 1
(W/L)2 = 28.8 µm/180 nm
Ideal CL = 19.4 fF
RS = 50 Ω RB1 Transformer
LS RB1 = 1 MΩ
All Q’s = 12
Ideal VB1 = 0.9 V
Transformer
(a)

VDD = 1.8 V

LT Ls = 100 pH
LT = 640 pH
1 : 1.2 CL CBY
VS LGG = 810 pH
CBY LGG 1.3 : 1
(W/L)1 = 28.8 µm/180 nm
RL = 50 Ω
RB1 CL = 46.5 fF
RS = 50 Ω LS
RB1 = 1 MΩ
Ideal All Q’s = 12
Ideal Transformer
VB1
Transformer
(b)

Figure 11: (a) The circuit schematic of a cascode amplifier with inductive degeneration designed and simulated in a CMOS 180-nm process.
(b) The circuit schematic of a CGD -neutralized common-source amplifier. Both amplifiers have been designed to operate at a 28-GHz center
frequency. All component values have been included.

and see the equation at the bottom center-tapped inductor are perfectly between the input and the com-
of the page where G eq and B eq are coupled (k = 1) or 2) for partially mon terminal, forcing them to be
the conductance and susceptance coupled inductors (k 1 1) and when in opposite phase. This means that
of t he equiv a lent a d m i t t a n c e there is no mismatch between the ideally the transconductance will
Yeq (= YL + j~C GD f o r F i g u r e 9 (a ), loadings of two sides. be boosted by 6 dB [6]. However,
= YL + j~C N for Figure 9(b), respec- For the circuit of Figure 7(a), this g m-boosting is mainly used to
tively. Equation (5) verifies that, the neutralizing network is placed compensate for the resistive source
for two important special cases, between the input and output ter- degeneration associated with the
the gain and phase offset between minals. The inductor would also be loss of the center-tapped inductor.
DV1 and DV2 is zero, namely, 1) part of the output tank circuit. On One additional drawback regard-
for any arbitrary load admittance, the other hand, the center-tapped ing the neutralized amplifier in Fig-
YL, and when the two sides of the inductor in Fig ure 7(b) is placed ure 7(b) is that the presence of large
bypass capacitance contributes to
significant phase error between the
two terminals of the inductor. This
~L ^k + 1h G eq makes the design of a perfect neu-
\N V - \D V = tan -1 - tan -1
2 - ~L ^k + 1h^~C N + B eqh tralizing network extremely chal-
~L 61 - ~ 2 LC N ^1 - k 2h@ G eq lenging as this phase error needs to
1 - ~ LC N - ~L 61 - ~ 2 LC N ^1 - k 2h@ B eq
# 2
be accounted for during the design
R V1/2 of the center tapped inductor.
NV S ^2 - ~L ^k + 1 h^~C N + B eqhh2 + (~L (k + 1) G eq) 2 W On the other hand, neutralization
=S W
DV 1 2 2
Se - ~ LC N - ~L
o + ^~L 61 - ~ 2 LC N ^1 - k 2h@^G eqh ) W
2 in differential amplifiers can be done
S 61 - ~ 2 LC N ^1 - k 2h@ B eq W
SS WW with no explicit use of inductors. In
T X fact, the output terminals of opposite
polarity readily exist in a differential

88 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

topology. Figure 10 shows the core
differential circuit incorporating the
capacitive neutralization technique.
Capacitive neutralization of differ-
ential amplifiers is a wideband tech-
nique that insures the stability of the
amplifier. Conse­q uently, differen-
tial front-end mm-wave po­­wer ampli-
fiers on the transmitter side and
low-noise amplifiers on the receiver
side use this technique to achieve
wideband performance improve-
ment. In addition, this technique can
be used at near-fmax frequencies to
boost the amplifier’s power gain.
One important observation is that,
besides stabilizing the amplifier, neu-
tralization essentially increases the
maximum allowable matching band-
width of the amplifier, predicted by
the Bode–Fano limit [1]. This notion
will be used in wideband RF or mm-
wave applications.
For a better performance comparison,
consider two amplifiers in the same
180 -n m CMOS pr o cess, bot h de­­
signed to operate at 28-GHz center fre-
quency. In Figure 11, (a) shows a source
degenerated cascode amplifier, and (b)
indicates a common-source stage with
neutralization. For the sake of simplicity,
the input and output matching circuits
are realized with transformers. From
the simulated gain plots indicated in
Figure 12(a), the neutralized common-
source stage exhibits higher peak gain
and wider frequency response, which
is to be expected. Since the operation
Cascode
6 6.5
5.5
5 5.5
Gain (dB)
The general concept of amplifier neutralization
to overcome amplifier instability has been
around for many years, dating back to the
early part of the 20th century.
frequ­ency is close to fmax of the device
in this process, which is around 55 GHz,
the common-gate transistor contri­
butes considerably to the overall
noise figure. The noise figure of the cas-
code amplifier is higher than that of the
neutralized common-source ampli-
fier, which is also verified with noise fig-
ure simulation of these two stages [see
Figure 12(b)].
Conclusions
The general concept of amplifier
neutralization to overcome amplifier
instability has been around for many
years, dating back to the early part of the
20th century. This article provided an
overview of neutralization techniques
for high frequency amplifiers. First, the
problem of instability in non-unilateral
amplifiers driving tuned RLC tank cir-
cuits was studied. This discussion was
followed by revisiting RF cascode ampli-
fiers. The issues associated with cas-
code topology at high frequencies were
briefly explained, which paved the way
for introducing the neutralization tech-
niques in both single-ended and differ-
ential high-frequency amplifiers. Two
examples, a cascode amplifier with
source degeneration and a neutralized
Neutralized
6 tion Circuits: Analysis and Design, 2nd ed.
common-source amplifier, in a 180-nm
CMOS process and for carrier frequency
of 28 GHz were presented. The common-
source amplifier shows higher power
gain and lower noise figure compared to
the cascode amplifier, as was anticipated
from the study of this article.
Acknowledgments
This work was supported in part by
a grant from the Samsung Advanced
Institute of Technology (SAIT) Global
Research Outreach (GRO) Program
and NSF Award ECCS-1611575.
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J. Solid-State Circuits, vol. 39, no. 12, pp.
2239–2249, Dec. 2004.
[5] V. Jain, S. Sundararaman, and P. Heydari,
“A CMOS 22-29GHz receiver front-end for
UWB automotive pulse-radars,” in Proc.
IEEE Custom Integrated Circuits Conf.,
Sept. 2007, pp. 757–760.
[6] A. Shameli and P. Heydari, “A novel ultra-
low power (ULP) low noise amplifier using
differential inductor feedback,” in Proc.
32nd European Solid-State Circuits Conf.,
Sept. 2006, pp. 352–355.
[7] K. K. Clarke and D. T. Hess, Communica-
Florida: Krieger Publishing, 1994.

Gain (dB)

4.5
5
4
4.5
About the Authors
3.5 Payam Heydari is a full professor of
4
3 electrical engineering at the Univer-
2.5 3.5
sity of California, Irvine. He is noted
2 3 for his pioneering work on silicon-
2.6 2.7 2.8 2.9 3 2.6 2.7 2.8 2.9 3
Frequency (Hz) × 1010 Frequency (Hz) × 1010 based millimeter-wave and terahertz
(a) (b) IC design. He is the author or coauthor
of two books, one book chapter, and
Figure 12: (a) Simulated gain versus frequency. (b) Simulated noise figure versus frequency more than 130 journal and conference
for both cascode and common-source amplifiers in Figure 11(a) and (b). papers. He is a Fellow of the IEEE.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 89

 Long Yan and Joonsung Bae

Challenges
of Physiological
Signal Measurements
Using Electrodes

image licensed by ingram publishing

Fundamentals to understand the instrumentation

W
ith an aging society and sedentary
lifestyles around the world, the
cost of health care becomes a signif-
icant challenge. People continuously
seek new technologies for affordable
Digital Object Identifier 10.1109/MSSC.2017.2745860
Date of publication: 16 November 2017
but comfortable solutions to improve the efficiency of
their health care. Recently, advances in miniaturized bio-
sensor and data analysis have accelerated the health-care
paradigm shift toward proactively managing wellness and
changing personal lifestyle. It is easy to find accessories
in various forms that integrate miniature and low-power
biosensors continuously and unobtrusively sensing, pro-
cessing, and transferring our physiological data.

90 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/17©2017IEEE

 Electrodes are one of the most
widely utilized transducers for physi-
ological signal measurement. They
convert ionic information inside the
human body into electrical voltage sig-
nals. In general, a dedicated readout
circuit is required to amplify weak elec-
trical signals from electrodes buried
by unwanted noise signals. This article
introduces fundamentals on physi-
ological signal measurements using
electrodes helping readers to under-
stand instrumentation challenges.
Understanding the Challenges
of Electrode Interfaces
Electrode Interfaces
Figure 1 shows a biopotential sig-
nals acquisition system with an elec-
trode interface. Electrocardiogram
(ECG), electromyograph (EMG), and
electroencephalogram (EEG) are the
most widely monitored physiologi-
cal signals that represent activity
of the hear t, muscle, a nd brain,
res­­pectively. In general, the signal
(bandwidth and amplitude) char-
acteristics of the ECG, EMG, and
E EG a r e in t he r a nge of 0.05 –
250 Hz/0.5–4 mV, 20–1,000 Hz/0.1–
5 mV, a n d 0.5-150 Hz/5-300 nV ,
EEG
ECG
EMG
EEG: 5–300 µ V
0.5–150 Hz
ECG: 0.5–4 mV
0.05–250 Hz
EMG: 0.1–5 mV
20–1,000 Hz
FIGURE 1: A biopotential signals acquisition system with an electrode interface.
respectively [1]. Notice that their
bandwidths are located in the low fre-
quency under 1 kHz, and the signal
strength is extremely small. Given
the signal bandwidth and amplitude,
a good circuit designer needs to de­­
sign a biopotential readout circuit tol-
erable to a large degree of unwanted
noise signal such as 50/60-Hz inter-
ference, flicker noise, and dc offset of
the amplifier. Biopotential electrodes,
as the first component of a signal
acquisition chain, play an important
role in biopotential measurements as
the characteristics of the electrode-tis-
sue interface can be a limiting factor
of system performance. The proper
topology of a readout circuit and
the minimum required performance,
such as, noise, common-mode rejec-
tion ratio (CMRR), input impedance,
and power consumption are usually
derived from this interface.
The electrode-tissue interface
can be modeled w ith electrode-
tissue impedance and polarization
voltage. C elec and R elec represent the
impedance related with the electrode-
electrolyte interface, and R Gel is
the resistance of the electrolyte (gel)
solution. The half-cell potential, VH,
is due to the built-up charge gradients
Electrode System
Celec
Electrode
Gel
Stratum Corneum Half-Cell
Epidermis
Potential
Cepi
Subcutaneous
Layers
Dermis
ex. Ag/AgCl
Relec = 51 kΩ /Celec = 47 nF/VH = 0.22 V
IEEE SOLID-STATE CIRCUITS MAGAZINE
at the electrode-electrolyte interface
[2]. The impedance with C epi, R epi,
and R D is the representation of the
skin and its equivalent circuit model.
The circuit model parameters large­
­ly depend on the electrode material,
area, skin condition, invasiveness,
and pressure of electrode contact. A
typical wet electrode with Ag/AgCl
and hydrogel is widely used in clini-
cal practice due to its low polariza-
tion voltage (0.22 V), low impedance
(51 kΩ in parallel to 47 nF), and low
baseline drift (0.13 mV at room tem-
perature). Dry contact electrodes,
however, eliminate the use of gel
at the cost of a significant higher
impedance (high resistance and small
capacitance), which requires further
efforts for amplifier design.
Electrode Configuration
Practical electrode applications for
the biopotential signal measure-
ments are shown in Figure 2. To pick
up signals from the body, a pair of elec-
trodes, E1 and E2, is used. Z E1 and Z E2
represent contact impedance of the
electrodes E1 and E2, and V1 and V2
are voltage-converted signals through
the electrodes. Suppose that a differ-
ential amplifier powered by a battery
Relec
RGel
AMP
VH
Repi
RD
fa l l 2 0 17 91
 Displacement Current (Id)
from Mains
Id = 1µA
V1 Meas. V1
E1 ZE1 + + ZE1 +
Electrode E1 Vout = AV × (V1–VBIAS)
V2 +
E2 ZE2 – 3V ZE2 –
Ref./Bias E2
– Electrode Id V VBIAS Sensitive to
VCM = Id × Zg VBIAS
= 26 V Battery GND
VCM = VDM
= Id × ZE
Zg = 100 pF Ground
Coupling (Zg) –
Earth GND
(a) (b)

Meas. V1 Meas. V1
Electrode E1 ZE1 + Electrode E1 ZE1 +
V2 Vout = AV × (V1–V2) V2
Ref. E2 – Ref.
ZE2 Electrode E2 ZE2 –
Electrode
E3 Insensitive to (V1+V2)/2
Bias VBIAS VBIAS
ZE3 V
Electrode RLD E3
Id VCM = Id × ZE Electrode ZE3 A
VCM = Id × ZE /(1+A)
VDM = V1 – V2 VDM = V1 – V2
(c) (d)

FIGURE 2: Electrode usage for biopotential signal measurements. (a) A common-mode signal, (b) unipolar electrode readout, and (c) bipolar
electrode readout, and (d) common-mode feedback electrode readout.

is used to amplify signals (V1-V2) .
The question is, “Can we measure
reliable biopotential signal with
such electrode configuration shown
in Figure 2(a)?” Before answering, we
need to figure out the common-mode
potential (VCM) of the human body.
The human subject is always exposed
to 50/60-Hz environments, which
means that there is a displacement
current (I d) coupling with a few nA
to several nA, depending on the sur-
roundings. For instance, the body is
coupled (100 pF) to the earth ground,
where 1 nA displacement currents
are flowing. This implies the value of
VCM is as high as 26 V from the earth
ground. Furthermore, the VCM might
change with respect to the coupling
strength between earth ground and
battery ground, resulting in the read-
out amplifier easily missing the signal
due to its limited dynamic range.
To secure the biopotential signal
always within the dynamic range of
the readout amplifier, one must form
a closed-loop circuit to the subject by
proper subject biasing. Exerting the
well-defined bias voltage to the sub-
ject not only provides a low imped-
ance path between the subject and the
battery ground but also eventually
lowers the common-mode voltage of
the body. Figure 2(b) shows a unipo-
lar electrode readout configuration,
where E1 is a measurement electrode
and E2 is a bias electrode. Therefore,
any signals on E1 will be amplified. It
is, however, susceptible to the noise
and interference since the com-
mon-mode and differential-mode
voltages are identical. Figure 2(c)
impr oves the readout configura-
tion by separating the bias electrode
using another electrode, E3. In this
bipolar electrode readout, the VCM is
determined by the impedance of E3,
whereas the common-mode noise
will be mitigated by the differen-
tial measurement from E1 and E2.
Common-mode feedback shown in
Figure 2(d) can be applied to further
reduce the level of VCM from E3. The
principle is that common-mode sig-
nals from E1 and E2 are extracted by
averaging V1 and V2. With a gain of
A, the effective impedance of E3 signifi-
cantly gets reduced. In practical ECG
recording, this scheme is known as
driven-right-leg to suppress 50/60 Hz
interference [3].
Challenges of Biopotential Readout
As previously mentioned, electrodes
may develop dc polarization voltage
across the electrode interface. Some-
times, this polarization voltage in the
electrode system brings up signifi-
cant challenge. Figure 3(a) addresses
the dc polarization issue, assuming
that each electrode has 300-mV polar-
ization voltage. Suppose that subject
is biased with 1.5 V, and the bipolar
electrode readout is configured. In the
worst case, the bias voltage through
E3 can be either 1.8 or 1.2 V. And E1
and E2 may also introduce polariza-
tion voltage on top of this. This may
change the common-mode signal on
E1 or E2 either down to 0.9 V or up
to 2.1 V. Considering that biopotential
signals of near dc are only a few nVs,
a huge dynamic range must be guar-
anteed by readout circuits.

92 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 The second challenge is about the
large impedance of the electrode as
shown in Figure 3(b). For example, ∆V1
Bias + +
a dry electrode has large Rc, as high ∆V3 ∆V1, ∆V2 E1 +–
Voltage
as several MXs. Such large electrode +– – 3V
2.1 V E2
impedance may attenuate the bio- 1.8 V ∆V2
potential signal before amplification 1.5 V E3 + 1.5 V – –
1.5 V
due to limited input impedance (R in) 1.5 V +– V
of the amplifier. More seriously, a 1.2 V ∆V3
0.9 V
low-frequency biopotential signal near
dc is prone to be distorted since
the capacitance Cc reduces the elec- (a)
Rin
trode impedance as the frequency Gain from
CC Subject to Amp RS + Rin
increases. Unless R in is high enough,
the phase shift of the low-frequency Skin Rs
VH Gain Rin
signal can be pronounced [4]. Frequency
Rc Rin RS + RC + Rin
The third challenge [Figure 3(c)]
1 1
is associated with the impedance
RCCC RC ||(RS + Rin)CC
mismatch between electrodes E1 and (b)
E2. Even if the CMRR of the ampli-
VCM = Id × ZE3
fier itself is infinite, the VCM on the Zin ZIN
subject can be converted into the V+ V+ = VCM ×
Meas. Electrode E1 ZE1 + ZIN + ZE1
differential signal provided that the V– ZIN
impedance mismatch between E1 Ref. Electrode E2 ZE2 – V– = VCM ×
ZIN + ZE2
and E2 (Z E1-Z E2) is comparable to the
E3 Zin
input impedance (Z IN) of the ampli- V+ – V– ZE1 – ZE2
Bias Electrode ZE3 V CMRR = =
fier. This is another important rea- VCM ZIN
son why the (common-mode) input Id
impedance of the amplifier must be
high enough. (c)
The last, but not least, motion arti-
fact is emphasized in Figure 3(d). ZIN
ZE + ∆ZE
In the steady state of the electrode ∆VH
VH
interface, the electrolyte balances the Iin
Skin

charge at the electrode-tissue inter-
face. Once the subject moves, the
charge balance is disturbed, trans-
lating the change of the charge into
the contact impedance Z E and half-
cell potential VH . The change of VH
directly affects the input voltage sig-
nal, and the change of Z E modulates
the VH building-up motion potential
signal, leading to the baseline signal
fluctuation. Especially when it comes
to the dry electrode, the motion arti-
fact is much more severe since there
is lack of electrolyte at the elec-
trode interface.
In summary, it is important to
understand 1) the existence of the
large common-mode signal on the
subject through the displacement cur-
rent and bias electrode, 2) the large
dc offset signal due to the electrode
polarization, 3) the requirements of
Gain
ZE
VH
ZIN
∆Vout = Gain × (∆VH + VH × ∆ZE /ZIN + ∆ZE × Iin)
ac Coupling Minimize
or Large Zin Input Current
(d)
FIGURE 3: Electrode interface challenges: (a) dc polarization voltage, (b) amplitude attenua-
tion, (c) CMRR degradation due to electrode impedance mismatch, and (d) motion artifact.
the high-input impedance amplifier high input impedance, low noise with
to support high electrode impedance low power consumption. The circuit
and its mismatch, and 4) the motion designer has to be able to trade those
artifact due to the change of the elec- performance parameters off with
trode interface in motion. With these res­­pect to the application require-
challenges in mind, the readout cir- ments. According to the applications,
cuit design must focus on achieving the minimum requirements for the
high CMRR, large dc filtering range, readout circuits can vary as shown in

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 93

 Table 1. The Minimum
Table 1. For ECG signal acquisition from Instrumentation Amplifier
requirements for ECG and EEG. the chest, 60-dB CMRR might be suf- For the biopotential acquisition sys-
ficient while EEG signal measurement tem, the first circuitry to interface
Parameters ECG EEG
from the head needs more than 100-dB with the electrode is an instrumenta-
CMRR 60 dB 110 dB CMRR because the EEG signal is much tion amplifier (IA). Then the ampli-
Noise 5 nVrms 0.5 nVrms weaker than the ECG and uses a much fied and conditioned signal is applied
smaller electrode. For the same rea- to an analog-to-digital converter (ADC)
Input 10 MX 100 MX
impendance son, low noise with high input imped- for further-stage digital signal pro-
ance readout circuits are required for cessing. Figure 4 compares two ap­­­­­
dc headroom ±300 mV ±50 mV
EEG application. proaches to constitute the combination
of an IA and an ADC. The first approach
(a) employs a dc-coupled low-gain IA
followed by a high-resolution ADC.
Electrode Owing to a large dc offset from the
Electrode

electrode, the maximum gain of the

HPF
AMP ADC AMP ADC
IA is usually limited not to make the
< x10 > 16 bit > x100 10–14 bit IA saturated to the supply voltage. For
At Low-Gain High- At High-Gain Low- a high signal-to-noise ratio (SNR), the
Electrode Amplified Res. ADC Electrode Amplified Res. ADC
low-gain IA is compensated by the
high resolution of the ADC to resolve
SNR
the small analog signal in a fine scale.
Amplitude

Amplitude

On the other hand, another approach

SNR ADC [Figure 4(b)] filters out a large dc off-
Noise set signal with a high-pass filter (HPF)
Signal Chain Signal Chain
at inputs. Then the gain of the dc-free
IA need not be limited and is able to
FIGURE 4: Readout system approaches. be high, enabling the system to adopt
a low- resolution ADC for the same
SNR as the dc-coupled system [Fig-
ure 4(a)]. As you can easily figure out,
+ the approach in (a) is much simpler at
V1
A1 R2 R3 the cost of higher power consumption
– as it needs low-noise delta-sigma ADC
R1 – with wide bandwidth but low-noise
A3 IA. It preserves challenge at the elec-
RG

VOUT
+ trode handing it over to the ADC. On
R1
the contrary, the system in [Figure
–
A2 R2 R3 VREF 4(b)] eliminates dc challenges at the
V2 + IA stage, allowing for a high-gain IA
followed by a successive approxima-
Parameters First Stage Second Stage tion register ADC, which makes it
Differential Gain 1+2R1/RG R3/R2 much more power efficient. None-
Common-Mode Gain 1 σR × R3/R2 theless, since the HPF requires a
very high time constant, it is rather
(a)
Noise RTI R area consuming and slow to respond
2 to the abrupt potential change at
C + C2 + Cp a 2
C2
a 1 × VOTA V1 C1 the electrodes.
C1
–
Cp VOUT Classical 3-Op-Amp
CMRR + ­Instrumentation Amplifier
1
Figure 5(a) represents a dc-coupled
σC21 + σC22 + σC2p V2 C1 C2 VREF classical three-op-amp IA that has
been widely adopted in commercial
R
(b) products. It consists of two-stage
amplifiers with resistive feedback.
FIGURE 5: A popular IA architecture: (a) classical 3-op-amp IA and (b) capacitive IA. The first stage has balanced and high

94 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

input impedance with a differen- Current-Balanced buffer and R2. The input differential
tial gain of (1+2R1/RG) and common Instrumentation Amplifier voltage is converted into current IIN at
mode gain of one. Meanwhile, the Figure 6(a) shows another class of IA the TC stage, and the output voltage is
second-stage amplifier is a differ- topology [6] using resistors for defining generated at the TI stage with the cur-
ential to single-ended converter with the gain to refine the 3-Op-amp IA. It is rent flow through R2. Therefore, the
a differential gain of (R3/R2). Notice referred to as current-balanced IA (CBIA) differential gain is R2/R1, whereas the
that the common-mode gain is pro- since it works in the current domain. common-mode gain is defined by the
portional to the resistor mismatch. It comprises a transconductance (TC) mismatch of the gain at the input buffers,
The CMRR is then mismatch depen- stage with input buffer and R1 and a making CMRR buffer-mismatch depen-
dent, and the matching between R2 transimpedance (TI) stage with output dent rather than resistor-­ m ismatch
and R3 is of significant importance.
Increasing the gain of the first stage
not only helps to improve CMRR but Table 2. A Comparison of classical 3-Op-amp IA and Capacitive IA.
also has an effect to reduce the total SPEC 3-Op-amp IA Capacitive IA
noise of the circuit as the noise of the
Gain (1+2R/RG) C1/C2
second stage is scaled by the first
stage gain when it refers to the input. CMRR 1/vR 1/vC
It is worth noting that increasing the Noise RTI V2R +V2Thermal + V2Flicker b × (V2Thermal + V2Flicker)
first-stage gain is not as easy as the
Input impedance 1/j~Cp 1/j~C1
dc-coupled input contains large dc
offset voltage. Power 3 × Pop-amp POTA
dc headroom VDD/gain VDD
Capacitive IA Input CM range < VDD VDD
To circumvent the dc offset issue,
Figure 5(b) introduces an ac-coupled
capacitive IA (popular for implant
applications where low power con-
Transconductance (TC) Transimpedance (TI)
sumption is the primary concern [5]). It
is composed of an operational trans- CP IIN IIN
conductance amplifier (OTA) with ca­­ VIN+ ×1 ×1 VO+
pacitive feedback, defining the gain
R1

R2

of IA (C2/C1). The great merit of this Gain = R2/R1

IA is that C1 completely blocks any dc
voltage (electrode polarization volt- VIN– ×1 ×1 VO–
CP IIN
age) at inputs, achieving maximum
rail-to-rail dc headroom. The feedback
Gain Input Noise RTI Dynamic
resistor, R, plays a role in biasing the CMRR
(AV) Impedance (Thermal + 1/f) Range
high impedance input nodes and
2 2 2
determining high-pass corner fre- R2/R1 1/σBUF 1/CP 2 × VBUF +VR1 +VR2/AV IIN × R1
quency with C2. A single OTA, which
(a)
drives only high-impedance capaci- IIN + IDC+
tive nodes, means that it can be IIN
VIN+ ×1 ×1 VO+
designed with extremely low power
consumption. C1 needs to be high IIN
R1

R2

enough to mitigate the noise elevation

by parasitic capacitance Cp, consid- VIN– ×1 ×1 VO–
ering the required input impedance. IDC+
IIN + IDC–
The CMRR is capacitor mismatch
fCHOP fCHOP
dependent. Table 2 summarizes and IDC–
compares the performance of two
VDC, Electrode = IDC × R1 dc
popular IA architectures. While the Extraction
3-Op-amp IA has high input imped- dc Servo Loop (DSL) Cancels Out
ance, the capacitive IA has advantages dc Offset Current Flowing Through R1
in dc headroom, low power consump- (b)
tion, and rail-to-rail input common-
mode range. FIGURE 6: Current-balanced IA: (a) CBIA topology and (b) CBIA with chopping and dc servo.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 95

 When designing readout circuits for physiological
signal measurement, one needs to understand
that applications define the required signal
quality and the circuit architecture.
dependent. High input impedance is
easy to achieve (usually limited by the
parasitic capacitance, Cp of the input
buffer). Moreover, the noise is mainly
limited by buffers and R1. One of the
design tradeoffs is between power
consumption and noise. To achieve
large dynamic range at the input
stage, either large currents through
the resistor (meaning more power
consumption) or a large resistor (mean-
ing more noise) is required. It is,
however, superior to the 3-op-amp IA
from power and CMRR (nothing to do
with mismatch of the resistors) per-
spective. Still, other performances,
such as offset, 1/f noise, and CMRR,
need to be further improved by apply-
R ance measurement possible. This is
C C
VIN+
R2/R1 VO
VIN–
C R
Classical HPF
CM Input Impedance = R
High-Pass Cut Off = 1/2πRC
FIGURE 7: A passive high-pass filter.
IBIO ZT
ZBIO V ZBIO
ZT
IBIO
Voltage Excitation
IBIO = V/(2 × ZT + ZBIO)
FIGURE 8: Voltage versus current excitation.
96 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
ing a compensation circuit technique,
which is addressed in Figure 6(b) [6].
With the help of chopping, not only
can mismatches of input buffers
be compensated but also significant
improvements in low-frequency noise
(1/f) can be achieved.
High-Pass Filter Implementation
A chopper amplifier is basically a dc-
coupled amplifier that won’t be able to
achieve input dc blocking. Figure 6(b)
shows the concept of the dc servo
loop having the same effect as an ac-
coupled input for a chopper amplifier.
The purpose of the dc servo loop is to
sense the output dc level and regulate
the input of the amplifier such that
VIN+
R R
R2/R1
R R
VIN–
C One way to implement a current signal
Floating HPF
CM Input Impedance = ∞
High-Pass Cut Off = 1/2πRC
ISOURCE
IBIO ZT
ZT
IBIO ISINK
Current Excitation
IBIO = IEXCITED
the dc component of the input signal
can be properly removed. When the
negative feedback loop contains an
extremely large time-constant, low-
pass filter, the overall response ends
up with high-pass filter characteristics
near dc once the loop settles.
Instead of a dc servo loop, a pas-
sive HPF can be utilized before the IA.
Fig­­­­u re 7 presents the circuit im­­­­
plementation for ac-coupling input
to the IA with a cutoff frequency
of 1/2rRC. The classical HPF suf-
fers from finite common-mode input
impedance that may degrade the CMRR.
Alternatively, the floating HPF has very
large common-mode input impedance
by eliminating resistors to ground
while still having the same cutoff fre-
quency. Notice that the floating HPF is
very useful to sustain high CMRR of
the system at the cost of using several
discrete pas­sive components.
Bioimpedance Measurement
Electrical current excitation and volt-
age signal readout (or vice versa)
through electrodes lead bioimped-
an emerging research area that has
received more and more attention as
VO bioimpedance is an important param-
eter to analyze body composition.
is to utilize a voltage source through
electrodes (voltage excitation), and
the other method is to directly inject
a current signal through the current
source (current excitation), as shown
in Figure 8. For the voltage excitation,
the electrode impedance Z T is added
to the bioimpedance Z BIO leading the
current through the tissue (I BIO) con-
tains error. Alternatively, the current
excitation is more accurate as the
amount of current through the tis-
sue (I BIO) identical to the I SOURCE/SINK .
However, voltage across electrode im­­
pedance challenges current source
design, and usually high supply volt-
age is required to overcome this.
A bipolar or tetrapolar electrode
system is utilized to measure elec-
trode-tissue impedance (ETI) and
bioimpedance (Bio-Z), respectively.
As shown in Figure 9, the ETI can be

ISOURCE/SINK
Z1
+ ZBIO
Gain Vout
I (0°)
– ZV
Z2 I (180°)
Vout = I × (Z1 + Z2) × Gain
ETI
FIGURE 9: ETI versus Bio-Z measurements.
obtained by measuring the voltage
between two electrodes using current
source ISOURCE and ISINK. One of the pur-
poses of measuring the ETI is to sup-
press the motion artifact as ETI highly
correlates to the electrode impedance
mismatch depicted in Figure 3(d).
In practice, the ETI and biopotential
signal are monitored simultaneously
and their correlation is extracted to
get an artifact-free signal through an
adaptive filtering [7]. The Bio-Z, on the
other hand, utilizes tetrapolar elec-
trodes configuration (two for current
injection and two for voltage readout)
to mitigate the effects of the ETI by
picking up voltage signal across the
tissue only. It is worth noting that
the output impedance of the current
source and input impedance of the
amplifier must be sufficiently high
for Bio-Z measurement. Determining
the waveform of the injection current
is also important. For the purpose of
high-resolution Bio-Z measurements,
a sine wave [8] is preferred to a square
wave [7] at the cost of much more
power consumption. A reasonable
design tradeoff can be considered to
implement quantized sine wave-atten-
uating low-frequency harmonics with
low po­­wer dissipation [9].
Conclusions
When designing readout circuits for
physiological signal measurement,
one needs to understand that appli-
cations define the required signal
quality and the circuit architecture.
In addition, a clear understanding of
ZI
ISOURCE
ZV
+ Long Yan (yanlong.ee@gmail.com)
Gain Vout
–
ZI
ISINK
Vout = I × ZBIO × Gain
Bio-Z
electrode interface is as important
as the circuit design since it is first
and an integral part of the readout
circuits. It is also necessary to be
aware of signal aggressors so that
they can be removed properly. The
readout circuits are part of the over-
all system; therefore, various chal-
lenges and issues can be addressed
in other parts of the system.
References
[1] J. G. Webster, Medical Instrumentation:
Application and Design, 2nd ed. Boston,
MA: Houghton Mifflin, 1992.
[2] Y. M. Chi, T. P. Jung, and G. Cauwenbergh-
si, “Dry-contact and noncontact biopoten-
tial electrodes: Methodological review,”
IEEE Rev. Biomed. Eng., vol. 3, no. 1, pp.
106–119, 2010.
[3] A. M. Van Rijn, A. Peper, and C. A. Grim-
bergen, “High-quality recording of bio-
electric events: Part 1, interference reduc-
tion, theory, and practice,” Med. Biol. Eng.
Comput., vol. 28, no. 5, pp. 389–397, 1990.
[4] M. J. Burke, and D. T. Gleeson, “A micro-
power dry-electrode ECG preamplifier,”
IEEE Trans. Biomed. Eng., vol. 47, no. 2, pp.
155–162, Feb. 2000.
[5] L. Yan, P. Harpe, M. Osawa, Y. Harada, K.
Tamiya, C. Van Hoof, and R. F. Yazicioglu, “A
680nA fully integrated implantable ECG-ac-
quisition IC with analog feature extraction,”
in Proc. ISSCC Tech. Dig., 2014, pp. 418–419.
[6] R. F. Yazicioglu, P. Merken, R. Puers, and
C. Van Hoof, “A 60μW 60nV/√Hz readout
front-end for portable biopotential acqui-
sition systems,” IEEE J. Solid State Circuits,
vol. 41, no. 5, pp. 1100–1110, , May 2007.
[7] R. F. Yazicoglu, S. Kim, T. Torfs, H. Kim, and
C. Van Hoof, “A 30μW analog signal proces-
sor ASIC for portable biopotential signal
monitoring,” IEEE J. Solid State Circuits, vol.
46, no. 1, pp. 209– 223, Jan. 2011.
[8] ] L. Yan, J. Bae, S. Lee, T. Roh, K. Song, and
H. J. Yoo, “A 3.9mW 25-electrode reconfig-
ured sensor for wearable cardiac moni-
toring system,” IEEE J. Solid State Circuits,
vol. 46, no. 1, pp. 353– 364, Jan. 2011.
[9] L. Yan, J. Pettine, S. Mitra, S. Kim, D. W.
Jee, H. Kim, M. Osawa, Y. Harada, K. Tami-
ya, C. Van Hoof, and R. F. Yazicioglu, “A
13μA analog signal processing IC for ac-
curate recognition of multiple intra-car-
IEEE SOLID-STATE CIRCUITS MAGAZINE
diac signals,” IEEE Trans. Biomed. Circuits
Syst., vol. 7, no. 6, pp. 785–795, Dec. 2013.
About the Authors
received the B.S., M.S., and Ph.D.
degrees from the Korea Advanced
Institute of Science and Technology, in
2007, 2009, and 2011, respectively. In
2010, he was with the Massachusetts
Institute of Technology Microsystems
Technology Laboratory as a visiting
student, where he developed a low-
power EEG readout front-end. From
2011 to 2014, he was with IMEC, Bel-
gium, as a senior scientist. His research
at IMEC focused on the development
of low-power mixed-­ signal circuits
for wearable and im­­­ plantable appli-
cations. In December 2014, he joined
Samsung Electronics, Korea, where he
is now leading analog interface circuit
developments for nex-generation bio-
sensors. He is a Senior Member of the
IEEE and serves on the Technical Pro-
gram Committee of the International
Solid-State Circuits Conference.
Joonsung Bae (baej@kangwon
.ac.kr) received the B.S., M.S., and
Ph.D. degrees in electrical engineering
from the Korea Advanced Institute of
Science and Technology (KAIST), Dae-
jeon, in 2007, 2009, and 2013, respec-
tively. Since 2017, he has been with
the Department of Electrical and Elec-
tronics Engineering, Kangwon National
University, where he is an assistant
professor. From 2013 to 2014, he was
with the Memory Business of Sam-
sung Electronics, Korea. In 2014, he
joined the Information and Electronics
Research Institute of KAIST as a post-
doctoral researcher. Before joining
Kangwon National University, he was
an analog circuit designer with IMEC,
Belgium. His current research inter-
ests are energy-efficient mixed-signal
circuits and systems for the Internet
of Things, biomedical sensors, and
body area networks. He received the
Asian Solid-State Circuits Conference
Best Design Awards in 2011 and 2014
and the Global Internship Scholarship
of National Research Foundation of
Korea in 2012.

fa l l 2 0 17 97
 Chap ters

SSCS Singapore Chapter Organizes Distinguished Lecture

by Prof. Jerald Yoo

T
The IEEE Solid-State Circuits Society
(SSCS) Singapore Chapter, together
with A*STAR Institute of Microelec-
tronics (IME), jointly organized a
presentation, “Low Noise, Low Power
Sensor Interface Circuit Design,” given
by Distinguished Lecturer (DL) Jer-
ald Yoo, an associate professor with
National University of Singapore. The
lecture, held on 24 May 2017 at IME,
was attended by over 50 researchers,
students, and engineers from aca-
demia and industry.
Yoo presented the design strat- DL Prof. Yoo presents “Low Noise, Low Power Sensor Interface Circuit Design.”
egies of sensor interface circuits.
Starting from a basic op-amp, he dis-
cussed the difficulties, limitations,
and potential pitfalls in sensor inter-
face as well as strategies to overcome
such issues. Low noise operation leads
to two dynamic offset compensation
techniques, auto-zeroing, and chop-
per stabilization. After that, system-
level considerations for better key
metrics such as energy efficiency
were introduced. Several state-of-
the-art instrumentation amplifiers
that emphasize different parameters
were analyzed to see how the signal
Audience members listening intently to DL Yoo’s presentation.
analysis impacts the analog sensor
interface circuit design.
The lecture concluded with inter- issues, and support vector machine.
esting aspects and opportunities that The presentation was interactive and
Digital Object Identifier 10.1109/MSSC.2017.2746158 lie ahead. Audience members asked was well received by the attendees.
Date of publication: 16 November 2017 questions about the offset, mismatch —Zhu Yao

98 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. Sorin P. Voinigescu Gives Talk at Aarhus University

P
Prof. Sorin P. Voinigescu, Stanley Ho
Chair in Microelectronics and direc-
tor of the VLSI Research Group in the
Electrical and Computer Engineer-
ing Department at the University of
Toronto, gave the lecture “Si-Based
Transistor and Analog-Mixed-Signal
Circuit Scaling and the Natural Pro-
gression of Moore’s Law to Silicon
Quantum Computing at the Atomic
S c a le .” The lecture was held on
14 August at Aarhus University, De­­
partment of Engineering, Denmark.
Semiconductor devices and ICs
have revolutionized life on Earth,
and the projections about future
electronics show that we are still
in the infa nc y st age. Silicon has
been the “magic” material behind
Prof. Domenico Zito (left), of Aarhus University, introduces SSCS DL Prof. Sorin P. Voinigescu,
the many ongoing societal and eco- from the University of Toronto.
nomic transformations, and in the
last decade, the progression through
Moore’s law has been the dominant
theme in almost ever y talk and
technical discussion in the IC inter-
national community. What’s next is
still the subject of many thoughts
and debates, but quantum phys-
ics will still be the engine of future
science and technology. About 100
years after its birth with Niels Bohr
in Copenhagen, Denmark, quantum
physics is more relevant than ever
and likely to dictate the future pro-
gression of Moore’s law.
Voinigescu touched on these
thoughts and many more during his
talk. He is a world-renowned expert
on high-frequency IC and atomic-scale
semiconductor device technologies.
He highlighted current op­­­portunities
and challenges in scaling silicon-based Prof. Voinigescu explains the electron-spin qubit based on five coupled quantum dots during
transistors and ICs toward future the lecture.
emerging technologies and, in particu-
lar, quantum computing. Students and staff members of attendance were scientists from uni-
the Department of Engineering, versities and companies from Den-
the Department of Physics, and the mark and Europe.
Digital Object Identifier 10.1109/MSSC.2017.2746160 multidisciplinary research institute
Date of publication: 16 November 2017 iNano attended the lecture. Also in —Domenico Zito

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 99

Prof. Pietro Andreani Speaks at the University of Pisa

I
IEEE Solid-State Circuits Society (SSCS)
Distinguished Lecturer Prof. Pietro
Andreani, Lund University, Sweden,
gave the talk “RF Harmonic Oscillators
Integrated in Silicon Technologies”
at the Dipartimento di Ingegneria
dell’Informazione, University of Pisa,
Italy, on 11 June 2017. Approximately
14 people were in attendance includ-
ing a mix of faculty, Ph.D. students,
and master’s students. Andreani’s lec-
ture was well received with a fruitful
discussion and many questions from
the audience.

Pietro Andreani presents his talk,“RF Harmonic Oscillators Integrated in Silicon Technologies.”
Abstract
As one of the truly f unda menta l
analog functions in any wireless/
wireline application, the voltage-
controlled oscillator attracts a great
deal of well-deserved attention. In
this presentation, we will investi-
gate the mechanisms of phase noise
generation in harmonic oscillators,
including some recently published
general results, after which we will
analyze both classical and emergent
oscillator architectures, describing
the pros and cons for each. Various
techniques to achieve a very wide
oscillator tuning range will be illus-
trated as well.

—Abira Sengupta

Digital Object Identifier 10.1109/MSSC.2017.2746161

Date of publication: 16 November 2017 Prof. Giuseppe Iannaccone (left), who organized the talk, stands with Prof. Pietro Andreani.

SSCS DL Marian Verhelst Gives Talk on Machine Learning

O
On 4 July 2017, Prof. Marian Ver-
helst, assistant professor, MICAS, KU
Leuven, Belgium, gave a lecture on
Digital Object Identifier 10.1109/MSSC.2017.2746162
Date of publication: 16 November 2017
machine learning at CEA-Leti, Greno-
ble, France. The talk, “Energy-Effi-
cient Processors for Deep Learning,”
attracted around 70 attendees. The
audience asked Verhelst many ques-
tions about the topic, including what
the new technologies are for deep
learning and how deep learning can
be embedded into devices. Ques-
tions also focused on spiking neu-
rons perspectives. After the lecture,
audience members talked to Verhelst

100 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

about their resea rch rega rding
machine learning.

Abstract
Deep learning has become popular
for image recognition and, more re-
cently, for other pattern matching
tasks (such as speech processing and
text analysis). Deep learning, how-
ever, is associated with significant
computational complexity that, until
recently, made it feasible only on
power-hungry server platforms. We
now see a trend toward the embed-
ded processing of deep-learning net- Prof. Marian Verhelst gives a talk on machine learning at CEA.
works. After an introduction into
deep learning and its implementation
challenges, this tutorial will provide tion-driven algorithmic innovations implementation challenges in embed-
an overview of processing architec- to assist in understanding the impact ded deep learning and enable them to
tures to enable efficient network evalu- of new deep-learning algorithms on comprehend research on deep-learn-
ations on embedded platforms. This embedded hardware design. The tuto- ing processors.
discussion is tightly interwoven with rial will give the audience an un-
coverage of emerging implementa- derstanding of the opportunities and —Abira Sengupta

First Annual Advanced CMOS Technology Summer School

a Success in Beijing

T
The first Advanced CMOS Technol-
ogy Summer School (ACSS) 2017 was
held 23 July–4 August 2017. ACSS
was a joint activity supported by the
IEEE Circuits and Systems Society
(CASS) and the IEEE Solid-State Cir-
cuits Society (SSCS). ACSS 2017 was
sponsored by Synopsys China, Bei-
jing IC Park, and the CASS summer
Digital Object Identifier 10.1109/MSSC.2017.2746163
Date of publication: 16 November 2017
school project. The summer school
was attended by leading academic
researchers and industry experts,
who presented lectures on top-
ics covering process technology,
electronic design automation skill,
and design skills. These activities
were great examples of high-level
conti­ n uing education for junior
engineers, teachers, and students.
ACSS also illustrated the collabo-
r at ion among the Societies, local
Chapter leaders, and industry lead-
ers. This summer school was first
suggested by Dr. Zhihua Wang and
then supported by volunteers from
both SSCS and CASS. Local com-
panies Synopsys China and Beijing
IC Park prov ided financial sup-
port. This two-week-long school
was hosted and organized by the
CASS Beijing ­Chapter, the SSCS Bei-
jing Chapter, and SSCS T ­ singhua
Student Chapter. The cochairs of

The summer school attendees; organization committee members including Prof. Zhihua Wang; and several of the invited speakers, Dr. Jan
Van der Spiegel, Dr. Rakesh Kumar, and Dr. Cor Claeys.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 101

Dr. Van der Spiegel gave a talk at the
opening ceremony of the ACSS.
The general cochair of ACSS 2017,
Dr. Milin Zhang (right), thanked Dr. Van
der Spiegel.
ACSS 2017 were Dr. Milin Zhang,
Dr. Hanjun Jiang, and Dr. Liyuan
Liu. The Student Chapter members
took care of the itinerary: planning
for the speaker, preparing tuto-
rial handouts, and overall organiza-
tion of the attendees. A summary of
each day’s events was posted on the
SSCS WeChat public account, and
the organizers created a discussion
group so participants could keep in
touch after the school’s conclusion.
ACSS received good publicity and
was reported in various media out-
lets, including Xinhua News, one
of the most popular news channels
in China.
On 23 July, an opening ceremony
for invited guests and sponsors
was held, and the following indi-
viduals spoke: Dr. Jan Van der Spie-
gel, professor at the University of
Pennsylvania and SSCS president;
Aiguang Ren, director at Ministry of
Industry and Information Technol-
ogy of China; Guangming Su, secre-
tary-general at China International
Talent Exchange Foundation; Dr.
Shaojun Wei and Dr. Zhihua Wang,
professors at Tsinghua University;
Qun Ge, China country manager at
102 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Rakesh Kumar
Cor Claeys
Synopsys; and Jun Miao, chair at
Beijing IC Park. In Dr. Van der Spie-
gel’s opening speech, he said he was
very happy to see the growth of the
China IC industry over the past few
years. He said that the SSCS would
be very happy to have future confer-
ences in China.
On 24 July, the first official day
of the school, Van der Spiegel spoke
about the importance of the IEEE
and the SSCS. He encouraged attend-
ees to join the Society. He also gave
a keynote speech, “Integrated Cir-
cuits: Past, Present and the Road
Ahead—The Best Is Still to Come.”
He started his speech with a review
of key milestones of the semicon-
ductor industry over the past 70 years
that have changed the world and
will continue to change it at an
even faster pace. He reviewed how
inexpensive low-power transistors
have opened the door to many
new applications and enabled the
IC revolution.
Van der Spiegel discussed the
challenges of current complemen-
tary metal– oxide–semiconductor
devices and new technologies on the
horizon. He claimed that the revo-
Yervant Zorian
Alan Hasting
lution has just started, and the best
is still to come. He suggested that
circuit designers need to be able
to w o r k i n a m u lt i d i s c ip l i n a r y
environment and adopt new tech-
nologies. He also shared his opinion
on the future of China’s IC indus-
try and told the audience that he
believes the future is very promis-
ing through the great support from
the government and the great ef­­
fort from all the smart and aspir-
ing engineers.
Leading Experts Presented
at ACSS 2017
Ten leading experts presented at
ACSS 2017, including one IEEE Life
Fellow, seven IEEE Fellows, and two
IEEE Senior Members. Six hours of
lectures were given to the audience
daily, covering topics such as pro-
cess technology, simulation, and
design skills.
On 24 July, IEEE Life Fellow and
president and chief executive offi-
cer of TCX Technology Connexions,
Dr. Rakesh Kumar, gave the lecture
“Semiconductor Innovation—A Con-
tinuum of Opportunities.” He talked
about the booming semiconductor
Kevin Zhang
Albert Wang
industry, innovation, and entrepre-
neurship. He offered guidelines for
researchers interested in starting
their own company.
On 25 July, Dr. Cor Claeys, IEEE Fel-
low, Electrochemical Society fellow,
professor at KU Leuven and IMEC,
presented the lecture, “Ad­­vanced Ma-
terial and Device Aspects for Future
CMOS Technologies.” He discussed
challenges of key process modules
used in advanced device processing
and also introduced the advantages
and challenges of Ge technology.
On 26 July, IEEE Fellow, chief archi-
tect, and fellow at Synopsys Dr. Yer-
vant Zorian, gave a lecture, “Trends
and Solutions for Test and Reliability
in Advanced Technologies.” He dis-
cussed hierarchical tests and testing-
related IEEE standards.
IEEE Senior Member and Texas
Instruments Fellow Alan Hastings
presented “The Art of Analog Lay-
out” on 27 July. He introduced basic
steps in fabrication and talked about
important issues in layout, such as
mismatch and latchup.
On 28 July, Dr. Kevin Zhang, IEEE
Fellow and vice president of Tai-
wan Semiconductor Manufacturing
Minoru Fujishima
Hoi-Jun Yoo
Company (TSMC), gave the speech
“Design Challenges on Nano-Scale
COMS.” He reviewed the current
technology landscape and discussed
new design challenges. Afterwards,
four of his colleagues introduced
TSMC’s 16-nm technology in detail.
Dr. Albert Wang, IEEE Fellow and
professor at the University of Cali-
fornia, Riverside, delivered a lec-
ture, “How to Design Electrostatic
Discharge (ESD) Protection as an
Integrated Circuits (IC) Designer,” on
31 July. He introduced every aspect
of from standards and ESD protec-
tion circuits to failure analysis and
technology influence. He also dis-
cussed ESD protection for radio fre-
quency and high voltage.
On 1 August, Dr. Minoru Fuji­
shima, IEEE Senior Member and
professor at the Hiroshima Univer­
sity, gave the lecture, “Ultimate High-
Speed Wireless Link.” He introduced the
advantages of terahertz and discussed
some considerations for high-fre-
quency complementary metal-oxide-
semiconductor (CMOS) design. Dr.
Ruibing Dong, Fujishima’s assistant,
introduced CMOS ultra-wideband
transceiver design in detail.
IEEE SOLID-STATE CIRCUITS MAGAZINE
Seng-Pan U
Alice Wang
On 2 August, Dr. Hoi-Jun Yoo, IEEE
Fellow, professor at KAIST, delivered
his lecture, “Mobile Embedded DNN
(Deep Neural Network) and AI (Arti-
ficial Intelligence) System on Chip
(SoCs).” Dr. Yoo introduced some key
points in mobile/embedded DNNP
design. He also demonstrated SoC
projects done in his research group.
On 3 August, Dr. Seng-Pan U, IEEE
Fellow, professor of the University
of Macau, R&D director of Synop-
sys, gave the talk “Integrated Analog
Front-End (AFE) Design for Mobile
and Multimedia SoC” on 3 August.
He introduced AFE design for com-
munication SoCs and audio codec
systems. He also discussed analog-
to-digital converter design.
On 4 August, Dr. Alice Wang, IEEE
Senior Member, assistant general
manager of Mediatek, gave the lec-
ture “Low Power for Mobile Comput-
ing.” She introduced some techniques
for power optimization and pointed
out future development directions
and opportunities for central process-
ing unit design.
The summer school attendees
were very engaged and asked many
questions during these lectures. The
fa l l 2 0 17 103

Dr. Alice Wang hosts a leadership training
activity, “Can You Achieve $10B?”
Dr. Van der Spiegel (center) with some
of the SSCS Tsinghua Student Chapter
members on ACSS 2017.
A WiC group photo at ACSS 2017.
discussions usually continued until
lunch breaks and after the sessions
ended. In addition to academic ques-
tions, experts also interacted with
the audience. A few students spoke
to Kumar about their own ideas on
innovation and entrepreneurship.
Students asked Hastings for a sig-
nature on his well-known book, The
Art of Analog Layout. The students
found the speakers’ experiences on
Ph.D. study, career paths, research
104 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
The SSCS Tsinghua Student Chapter
members hard at work.
The hosts from the SSCS Tsinghua Student
Chapter organized a one-day tour of
Tsinghua Campus during the summer school
weekend break. The attendees visited
the Tsinghua Nanofabrication Technology
Center. Dr. Xiaoming Wu welcomed the
visitors and gave them a tour.
topics, and personal anecdotes very
interesting. On the last day of the
­ from being a shy, fresh graduate
program, Wang organized the lead-
ership training activity, “Can You
Achieve $10B?” She emphasized that
effective communication is vital in
maximizing performance.
WiC on ACSS 2017
Dr. Wang, chair of the SSCS Women
in Circuits (WiC) Committee, Dr.
Milin Zhang, assistant professor at
Tsinghua University and advisor to
the SSCS Tsinghua Student Chapter,
and Chang Cheng, female student
m e m b e r f r o m t h e S S C S Ts i n g -
hua Student Chapter, coorganized a
WiC lunch social gathering. Women
such as Elva Ma from Synopsys and
Wenli Lan from Beijing National IC
Design Industrial Base attended
the luncheon.
Wang shared her experiences as
a female engineer in the IC indus-
Chang Cheng, from the SSCS Tsinghua
Student Chapter, led the WiC activity on the
last day during the lunch break.
Dr. Alice Wang, chair of the SSCS WiC
Committee, shared her experience as a
female engineer in the IC industry.
try. She talked about her journey
Ph.D. student to a technical leader
in her company and in the research
field. She said the training that a
Ph.D. student gets from school-
ing is not enough for a workplace
since leadership is just as impor-
tant as tech­nical skills. She encour-
aged the ladies to be brave, express
themselves, and be confident. She
also gave advice on how to balance
personal life and work as a female
­engineer while en­­­couraging them
to get involved in both the IEEE and
SSCS. Zhang, Ma, and Lan also shared
their experiences as female engineers
in the industry, as faculty members,
and government employees.
—Milin Zhang
Cochair, Advanced CMOS
Technology Summer School
SSCS DL Antonio Liscidini Lectures at Lund University

I
IEEE Solid-State Circuits Society
(SSCS) Distinguished Lecturer (DL)
Prof. Antonio Liscidini, assistant
professor, Electrical and Computer
Engineering, University of Toronto,
spoke at Lund University on 21 June
2017. The title of the lecture was
“Emerging Analog Filtering Tech-
niques.” Approximately 15 people
attended, including researchers
from Lund University, Ericsson, Eric-
sson Research, and ARM. Audience
members were immersed in the talk
and asked questions about active fil-
ters and the issues arising from the
use of such filters in radio receivers
qualified for production.
Antonio Liscidini presented a talk, “Emerging Analog Filtering Techniques.”

Abstract
This talk will introduce three different
techniques tailored to the implemen-
tation of channel selection filters in
wireless transceivers: adaptive analog
filters, filtering analog-to-digital con-
verters (ADCs), and passive switched
capacitor circuits.
The adaptive filters presented
succeed in shaping the f ilter ing
profile as a function of the operative
scenario, without the need of any
control loop. This allows for the
optimization of the filter design by
minimizing the average power con-
sumption instead of the peak-dissi-
pation occurrence in the worst-case
scenario, which has a very low prob-
ability to appear. Pietro Andreani (right) presents Antonio Liscidini with a token of thanks.
In the second part of the talk, a
filtering ADC is presented. Although
the interferers are suppressed be­­­ filter, able to track and suppress un­­ order topologies, even with complex
fore the ADC conversion, the filter wanted interferers. conjugates poles, without the need
profile is entirely defined in digital The talk concludes with a discus- of any active device. Measurement
domain through a reconfigurable sion on passive switched capacitors results on three different prototypes
filters. A new intuitive continuous- will be provided.
Digital Object Identifier 10.1109/MSSC.2017.2746164 time model will be introduced, which
Date of publication: 16 November 2017 easily allows for the design of high- —Abira Sengupta

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 105

“It Is Time to Use Time“
A Lecture Held by the SSCS Thailand Chapter

T
The IEEE Solid-State Circuits Soci-
ety (SSCS) Thailand Chapter invited
Prof. Bogdan Staszewski, from Uni-
versity College Dublin, to give a spe-
cial lecture, “It is Time to Use Time,”
on 25 July 2017. Staszewski is one of
the world’s most renowned research-
ers in digital radio frequency (RF), and
he shared his knowledge and experi-
ence on the utilization of time-domain Prof. Bogdan Staszewski (front row, center) accompanied by SSCS Thailand executive officers
information, including the evolution of Prof. Amorn Jiraseere-Amornkul (left) and Dr. Sitt Tontisirin (right).
digital RF, one of the important tech-
nologies for the Internet of Things.
The lecture was followed by a poster
session by students from local uni-
versities in Thailand. There was also
a presentation by Synopsys about its
low-power digital design flow. The
event attracted 50 participants from
both academia and industry and was
hosted at Kasetsart University by
the Low Power Integrated Circuits and
Systems Research Group, headed by
Dr. Woradorn Wattanapanitch.

Digital Object Identifier 10.1109/MSSC.2017.2746165

Date of publication: 16 November 2017 Attendees engaged in discussions during the poster session.

Recent Silicon Valley SSCS Chapter Activities

Seminars, Workshops, and Distinguished Lecturer Talks

T
The IEEE Solid-State Circuits Soci-
ety Santa Clara Valley (SCV-SSCS)
Chapter held a number of semi -
na rs, webina rs, work shops, a nd
Dis­­­t inguished Lecturer (DL) talks
in the spring and summer of 2017.
This article highlights recent events
held and sponsored by the Chapter.
Please feel free to contact the SCV-
SSCS Chapter if you are interested in
presenting at our meetings, would
like to attend the Chapter events, or

Digital Object Identifier 10.1109/MSSC.2017.2746166 Dr. Gunnam explains convolutional neural network applications in a hands-on workshop at
Date of publication: 16 November 2017 the SCV-SSCS Chapter.

106 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

are interested in volunteering. Full
information on Chapter activities and
upcoming seminars is available on
the Chapter website.

“Machine Learning and

Convolutional Neural Networks”
A two-night, hands-on workshop
series on machine learning and con-
volutional neural networks was orga-
nized on 30–31 May 2017 by the IEEE
SVC Section’s Chapters of the SSCS,
IEEE Circuits and System ­S ociety
(CASS), IEEE Communications Society,
IEEE Information Theory Society, and
IEEE Robotics and Automation Society
with sponsorship from Texas Instru- SSCS workshop speaker Dr. Gunnam receives a certificate of appreciation from the SCV-SSCS
Chapter at Texas Instruments, Santa Clara.
ments. Dr. Kiran Gunnam, technical
director of Algorithms and DSP, Velo-
dyne LiDAR, Inc., provided instruc-
tion in this seminar series, which
attracted more than 150 attendees.
IEEE SCV-SSC Chapter Vice-Chair Dr.
Mohammad (Vahid) Vahidfar led the
organization of the seminar series at
the Texas Instruments Silicon Valley
Auditorium. The collaborative effort
between the CASS and the SSCS was
initiated by CASS President Prof.
Franco Maloberti and SSCS President
Jan Van der Spiegel. The course slides,
made available to registered attend-
ees, will be available free of charge
to IEEE members in e-book format as
part of the IEEE CASS series, “Tutori- Prof. Razavi giving an SSCS DL webinar at the SCV-SSCS Chapter.
als in Circuits and Systems.” A print
edition will also be available by Ri­­
ver ­Publishers.
This series focused on explain-
ing the foundations and intuitions of
machine learning along with guided
programming exercises. The seminar
covered deep-learning techniques
used by practitioners in industry, in­­
cluding classic machine-learning tech-
niques, deep convolutional neural net-
works, regularization, optimization
algorithms, and practical methodol-
ogy with a focus on guided examples
in computer vison applications using
Tensor Flow and Octave. Dr. De receives a certificate of appreciation from the SCV-SSCS Chapter with Chapter officers,
The first workshop offered an intu- scientific and industry advisors, and seminar attendees.
itive treatment of important machine-
learning approaches and covered deep-belief networks were ­covered. ing algorithm, data preproces­sing,
supervised and unsupervised learn- How to build an end-to-end applica- and evaluating model.
ing. Various classic machine-learning, tion was covered in depth, focusing The second workshop offered an
modern deep neural networks, and on selecting the right machine-learn- in-depth treatment of convolutional

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 107


Prof. Hanumolu explaining a recent publication in response to seminar attendees at the SCV-
SSCS Chapter.
neural networks (CNNs) and ex­­
plained each layer in detail. Vari-
ous architecture optimization tech-
niques were also covered, including
data optimization, drop outs, layer
patterns, and sizing. A comprehen-
sive case study of recent CNN archi-
tectures including AlexNet, ZFNet
and GoogleNet was provided.
This hands-on workshop series
was very well received with all 150
attendees actively performing progra­­
mming-guided exercises on machine
learning. SSCS Chapter Chair Mojtaba
Sharifzadeh concluded the event by
thanking the speaker and announced
upcoming sponsored and cosponsored
2017 seminars.
“Channel Selection at RF”
Prof. Behzad Razavi held a seminar as
part of the SSCS DL webinar series at
the SCV-SSCS Chapter on 15 June. This
seminar was recorded at the Texas
Instruments venue and is scheduled
to become an SSCS webinar for mem-
bers. Prof. Razavi will be available
online after the webinar to answer
questions. Stay tuned for announce-
ment e-mails from the Society.
Abstract
A holy grail in radio-frequency (RF)
design has been to perform channel
108 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
selection at RF to remove strong inter-
ferers and even out-of-channel noise
at the receiver input rather than in the
baseband. Such an ap­­proach is attrac-
tive for it obviates the need for sur-
face acoustic wave filters and greatly
relaxes the linearity requirements of
the receiver chain, ultimately leading
to a lower power consumption and a
more com­­­pact design.
This research demonstrates a uni-
versal complementary metal-oxide-
semiconductor (CMOS) receiver by
employing RF channel selection and
meeting the exacting demands of the
Global System for Mobile Communica-
tions and wideband code division multi-
ple access. Drawing upon commutated
networks, we introduce the concept
of the “Miller bandpass filter” and sev-
eral of its variants to create a receiver
that achieves a narrow channel band-
width and can withstand large block-
ers. Realized in 65-nm technology, the
prototype provides a programmable
bandwidth from 350 kHz to 20 MHz and
draws 20 mW. The noise figure is 2.9 dB
in the absence of blockers and 5 dB with
a 0-dBm blocker at 20-MHz offset.
“Energy Efficient Computing
in Nanoscale CMOS”
Dr. Vivek De, Intel Fellow and direc-
tor of Circuit Technology Research
in Intel Labs, held a DL seminar at
the SCV-SSCS Chapter on 20 July.
The talk covered an overview of the
history of computing and challenges
and recent developments from her
team at Intel. Over 100 SSCS mem-
bers in the San Francisco Bay area
attended the seminar to hear about recent
advancements and ask the speaker
questions. The slides for this semi-
nar are available on the SCV-SSCS
Chapter website under previous events,
and the video recording will be avail-
able online.
Abstract
Future computing systems spanning
exascale supercomputers to wear-
able devices demand orders of ma­­
gnitude improvements in e n e r g y
ef­­­fi­­ciency while providing desired per-
formance. The system-on-chip (SoC)
designs need to span a wide range of
performance and power across diverse
platforms and workloads. The designs
must achieve robust, near-threshold-
voltage operation in nanoscale CMOS
process, while supporting a wide volt-
age-frequency operating range with min-
imal impact on die cost.
We will discuss circuit and design
technologies to overcome the chal-
lenges posed by device parameter
variations, supply noises, tempera-
ture excursions, aging-induced deg-
radations, workload and activity
changes, and reliability consider-
ations. The major pillars of energy-
efficient SoC designs are 1) circuit/
design optimizations for fine-grain
multivoltage and wide dynamic range,
2) fine-grain on-die power delivery
and management, 3) dynamic adapta-
tion and reconfiguration, 4) dynamic
on-die error detection and correction,
and 5) efficient interconnects.
“Applications of Time-Based Circuits
in Data Conversion, Filtering, and
Control, Part 2”
As part of the SSCS webinar program,
the SCV-SSCS Chapter organized a
comprehensive two-part seminar on
time-based circuits. The presen­tation
materials of these seminars will be
available on the SCV-SSCS Chapter web-
site, and the video recording will be
broadcast as a webinar to SSCS mem-
bers worldwide. For more information
on the upcoming webinar, please see
the SSCS website. Part 1 of this seminar,
“Time-Based Circuits—Not Just the Sin-
gle Slope!,” was recorded on 18 May by
Dr. Matt Straayer from Maxim Integrated
Inc. Part 2 was recorded on August 17
by Prof. Pavan Hanumolu, the University
of Illinois, Urbana-Champaign, “Appli-
cations of Time-based Circuits in Data
Conversion, Filtering, and Control.”
Hanumolu started his talk with a sum-
mary of part 1 and later covered different
applications such as data conversion,
IEEE SSCS and EDS Baltimore Joint Chapter Holds Spring Meeting
T
The IEEE Solid-State Circuits Society
(SSCS) and IEEE Electron Devices
Society (EDS) Joint Chapter held their
spring meeting on 25 April 2017.
The event was held at the National
­E lectronics Museum near the Bal­­
timore–Washington Intern at ion a l
Airport. Dr. Naghmeh Karimi, Uni-
versity of Maryland, Department
Digital Object Identifier 10.1109/MSSC.2017.2746167
Date of publication: 16 November 2017
SSCS and CASS Joint Sweden Chapter Hosts Workshop
on Energy-Efficient Electronics
T
The IEEE Solid-State Circuits Society
(SSCS) and IEEE Circuits and Systems
Society (CASS) Joint Sweden Chap-
ter hosted a workshop on energy-
efficient electronics. The workshop
Digital Object Identifier 10.1109/MSSC.2017.2746168
Date of publication: 16 November 2017
filtering, and control in power man-
agement. For the last part of the seminar,
he covered the recent publications on
time-based circuits from his research
group at the University of Illinois,
Urbana-Champaign. A list of related
references and recent publications, done
in collaboration with Dr. Mike Perrott
and Dr. Straayer, was provided.
Abstract
In the second part of this two-part
series on time-based circuits, I will pres-
ent time-based signal representation
as an alternative to classical voltage or
of Computer Science and Electrical
Engineering, gave a talk on malicious
aging in integrated circuits/cores
(MAGIC). The event was attended by
22 people.
Upcoming Fall Colloquium
On Thursday, 12 October 2017, the
Baltimore Chapter held their 6th
Annual Fall Colloquium, with the
topic “Flexible and Wearable Elec-
tronics.” The event, sponsored by
took place in beautiful Ystad, on the
south coast of Sweden and was or­­­­
ganized by Ch apter Ch a ir P r of.
J o a c h i m Rodrig ues at Lund Uni-
versity. This biannual event brings
together experts, from both industry
and academia, in system architec-
ture, circuit design, and t­echnology
IEEE SOLID-STATE CIRCUITS MAGAZINE
charge-based signal representations.
I will then show how this representa-
tion enables the implementation of
fundamental building blocks, such
as integrators using mostly digital cir-
cuits. Finally, I will present case stud-
ies of time-based analog filters, analog
to digital converters, and direct current-
direct current converters to highlight
the advantages, opportunities, and
drawbacks of the time-based approach.
—Mojtaba Sharifzadeh
Chair, Santa Clara Valley Chapter
the EDS’s Mini Colloquia Program, ad-
dressed the interests of local indus-
try, government, and academia. The
colloquium was held at the American
Center for Physics near the Univer-
sity of Maryland, College Park cam-
pus. For more information about the
event, contact Chapter Chair Paul A.
Potyraj at papotyraj@ieee.org.
—Paul Potyraj
to discuss the challenges and lat-
est trends in the development of
low-power and ultra-low-power em­­
bedded systems. The event was co-
organized by EPFL , L ausanne,
Switzerland, and Bar-Ilan University,
Israel. The 60 people in attendance
listened to invited speakers from top
fa l l 2 0 17 109
The Cadence training session at the workshop.

Vivek De presents his talk, “Challenges and Opportunities for Efficient and Scalable
Neuromorphic Systems.” Prof. Joachim Rodrigues spoke about the
workshop’s focus and goals.

universities and industry in Europe.

The highlight of the workshop was
the keynote, “Challenges and Oppor-
tunities for Efficient and Scalable
Neuromorphic Systems” by Vivek De,
Intel fellow at Intel Labs and director
of Circuit ­Technology at Intel Labs.
The second part of the workshop
The workshop’s social event went into the wee hours of the morning.
was a day and a half training session
sponsored by the Cadence Academic
Network. More than 30 Ph.D. students
received the latest insights on Genus,
Innovus, and Liberate.
“The socializing part of the work-
shop ended at 4 a.m. in the morning,”
said one participant, “so I bet some
good ideas were born that evening
and morning for further collaboration
and research.”

Andreia Cathelin, fellow, STMicroelectronics, gave a talk at the workshop. —Joachim Rodrigues

110 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. Patrick Yue Gives Distinguished Lecture
at SSCS Central Texas Chapter

I
IEEE Solid-State Circuits Societ y
(SSCS) Distinguished Lecturer (DL)
Prof. Patrick Yue visited the Univer-
sity of Texas at Austin on 4 August
2017. He gave an inspiring talk,
“LED-based Visible Light Communi-
cation Systems—Driver SOC Design
and Practical Applications,” that drew
over 30 attendees, including Uni-
versity of Texas faculty, graduate
students, and local professionals,
many of whom are SSCS members
or student members. After the talk,
students asked many questions, and
Yue gave very thoughtful answers.

Abstract
This talk presents two advanced vis-
ible light communication (VLC) mod-
ulator system-on-chips (SoCs). The
first is an IEEE 802.15.7 PHY-I stan-
dard compliant VLC transmitter. The
second is an active matrix light-emit-
ting diode (LED) microdisplay driver
SoC with embedded VLC function.
Using ordinary LED lights for VLC
has received a great deal of research
interest over the past decade due to a
number of novel applications, includ-
ing location-based wireless broad-
casting through LED lighting, signs
with LED backlights, and digital LED
displays. Most of the development
of VLC SoCs has focused on wireless
optical receiver design including cus-
tom complementary metal–oxide–
semiconductor imagers, whereas,
until recently, VLC transmitters have
Digital Object Identifier 10.1109/MSSC.2017.2746169
Date of publication: 16 November 2017
(From left) Prof. Nan Sun (SSCS Central Texas Chapter cochair), Shaolan Li (University of
Texas at Austin Ph.D. student), SSCS DL Prof. Patrick Yue, and Dr. Nagaraja Revanna (SSCS
Central Texas Chapter chair).
been predominately based on dis- modules have attracted significant
crete implementation. More impor- research efforts due to their superior
tantly, the power consumption of brightness and reliability compared
dedicated VLC transmitters is pro- to organic LED microdisplay. Com-
hibitively high with bit efficiency bining these two technology trends,
in the 100 nJ/b range. To overcome this paper also describes an active
these issues, this work demonstrates matrix LED (AMLED) driver SoC with
the first fully integrated VLC trans- built-in VLC modulation capability to
mitter SoC compliant with the IEEE demonstrate a WQVGA smart micro-
802.15.7 standard embedded with a display featuring 1.25-Mb/s VLC for
built-in 8-W LED driver. Excluding the enabling LED digital signage as loca-
power consumed by the LED driver, tion-based information broadcaster
the SoC achieves a record VLC trans- and indoor positioning beacons.
mission efficiency of 5 nJ/b. On the
other hand, the miniaturization and —Nan Sun
integration of inorganic LED display Chapter Chair, SSCS Central Texas

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 111

SSCS-Singapore Holds Distinguished Lecture
on Enabling and Exploiting
Machine Learning in Ultra-Low-Power Devices by Prof. Naveen Verma

T
The IEEE Solid-State Circuits Society
(SSCS) Singapore Chapter, jointly
with the Institute for Microelectronics
of Agency for Science, Technology and
Research (IME, A*STAR), held a Dis-
tinguished Lecture by Prof. Naveen
Verma from Princeton University,
New Jersey. The lecture, “Enabling
and Exploiting Machine Learning in
Ultra-Low-Power Devices,” was pre-
sented on 7 August 2017 in the Fusio-
nopolis high-tech campus, attended by
50 participants.
Verma motivated the topic, with
the emerging concept of enabling
natural interaction between us and Prof. Verma speaks with lecture attendees.
our environment. He briefly men-
tioned the hybrid large-area elec-
tronic systems being developed
in his lab toward this goal. Verma
then delved into the main topic of his
lecture, which presents cross-layer
techniques to design ultra-low-power
ICs for intelligent sensing and data
processing applications. First, on the
enabling aspect, machine learning
and artificial intelligence algorithms
are playing an ever-more increasing
role in sensing applica­tions, and the
computationally in­­t ensive nature
of these algorithms calls for ultra-
low-power circuit design techniques Prof. Verma presents his talk, “Enabling and Exploiting Machine Learning in ­Ultra-Low-
Power Devices.”
during their im­­plementation. Second,
on the exploiting aspect, by under-
standing these algorithms that are
dat a- dr iven, we can develop new
circuits that take advantage of such
data-driven properties to compen-
sate for (analog) imperfections in the
hardware system, i.e., sensor imper-
fections/faults, or nonideal proper-
ties in the analog part of the system.
The key idea is to perform/enable a
machine-learning training phase on
the nonideal system as opposed to

Digital Object Identifier 10.1109/MSSC.2017.2746170

Date of publication: 16 November 2017 The lecture attendees with Prof. Verma (seated, fourth from right).

112 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

implementing an as-is model trained
assuming ideal systems. For exam-
ple, an electroencephalogram-based
arrhythmia detector was presented
that can tolerate about 500 faulty
nodes out of 18,00 nodes with no
significant drop in true positive rate,
whereas conventional approaches
drop from 95+% baseline to under
60% with 30 faulty nodes and to 20%
with 120 faulty nodes. Furthermore,
memory consumption during train-
ing was addressed by a resource-
aware training algorithm to facilitate
training on the chip.
Verma went on to discuss addi-
tional ways machine learning can
interact with ultra-low-power circuit
design. For example, trained weights
in machine-learning algorithms are
usually floating points in software-
based implementations, while, to
enable ultra-low-power design, an
analog approach is preferred, requir-
ing low precision to keep dynamic
range and power/area under control.
A 4-b weak classifier system called
SSCS Hong Kong Chapter Hosts a Workshop on High-Performance
Wireless and Optical Communication Transceiver SoC Design
T
The IEEE Solid-State Circuits Soci-
ety (SSCS) Hong Kong Student Chap-
ter organized a two-day workshop,
“High-Performance Wireless and
Optical Communication Transceiver
SoC Design,” on 18–19 August 2017 at
the Hong Kong University of Science
and Technology (HKUST), Hong Kong.
The workshop focused on the latest
trends and challenges in wireless and
optical communication transceiver sys-
tem-on-chip (SoC) design. A crowd
Digital Object Identifier 10.1109/MSSC.2017.2746171
Date of publication: 16 November 2017
constrained resolution regression was
presented that can achieve almost
the same accuracy as the full-preci-
sion digital version.
Finally, the memory wall bottle-
neck was tackled for weak classifier
implementation by modifying SRAM
to function both as trained classi-
fier weight storage and as the clas-
sification engine itself. The latter part
works by activating all bit cells in
the array with word-line voltages cor-
responding to the input stimulus, in
a spirit similar to content address-
able memory, but mathematically
it is in the form of a mixed-signal
dot-product circuit. By considering
the very limited precision in classi-
fier weights (1 b in this case) and the
imperfect analogue components (a
nonideal digital-to-analog converter
that drives each word line), the pro-
posed system was able to achieve
near 90% accuracy when a conven-
tional system achieved about 92%
accuracy, while saving 113 times the
amount of energy.
Prof. Sam Palermo shares his research on advanced modeling and design of high-
performance ADC-based serial links.
IEEE SOLID-STATE CIRCUITS MAGAZINE
Verma presented a new approach
to ultra-low-power circuit design.
By leveraging the data-driven and
robust nature of today’s machine-
learning algorithms that will be at
the heart of many sensor systems
in the future, new design spaces
are opened up to researchers and
IC designers. Instead of optimizing
the circuit in isolation, cross-layer
optimizations spanning circuit and
algorithm/system/application allow
new circuit design techniques that
are both ultra-low power (e.g., low
precision classifier weights) and yet
robust through data-driven resil-
iency. Such cross-layer and multi-
disciplinary approaches breathe
new life into the maturing field of
circuit design, and we hope this can
inspire more hardware research-
ers to learn about machine learning
and other upstream technologies to
develop holistic systems.
—Jiang Wenyu
fa l l 2 0 17 113
 Prof. C. Patrick Yue describes the design
IEEE SSCS HKSC two-day workshop speakers (from left): Prof. C. Patrick Yue, HKSC advisor; considerations for a 10-Gb/s baseband-
Prof. Sam Palermo, Texas A&M University; Dr. Hirotaka Tamura, Fujitsu Laboratories; and over-fiber I/Q modulator SoC with
Prof. Jri Lee, National Taiwan University. integrated mm-wave power amplifier.

of more than 30 attendees, includ-

ing research postgraduate students
from HKUST, University of Macau,
and ten representatives of industry
from eTopus Technology, Brite Semi-
conductor, and Semiconductor Manu-
facturing International Corporation,
were in attendance. The workshop
featured SSCS D ­ istinguished Lectur-
ers (DL) Prof. Sam Palermo, Texas
A&M University; Dr. Hirotaka Tamura,
Fujitsu Laboratories and IEEE Fellow;
Prof. C. Patrick Yue, HKUST and IEEE
Fellow; and Prof. Jri Lee, National Tai-
wan ­University.
Dr. Hirotaka Tamura takes questions from the workshop participants. Yue, professor and director of
the Optical Wireless Lab and HKUST-
Qualcomm L ab, HKUST, gave the
welcoming remarks and introduced
Palermo, the first Distinguished
Lecturer (DL), who gave the opening
talk, focusing on advanced model-
ing and design of high-performance
analog-to-digital converter (ADC)-
based serial links. He discussed the
statistical modeling framework, low-
power >10GS/s ADC designs, and
novel receiver architectures, which
leverage partial analog equalization
embedded in the ADC. Yue then intro-
duced the second DL, Tamura, who
presented his industrial point of view
on the future of chip-to-chip com-
Prof. Jri Lee presents a comprehensive overview of advanced clock and data recovery circuits munications technology. He also dis-
for high-speed wireline systems. cussed the roles of high-bandwidth

114 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Students and professionals gather for the IEEE SSCS HKSC two-day workshop.

A dinner gathering of workshop speakers with IEEE SSCS HKSC committee members (from left): K.Q. Maqbool, HKSC chair; Wang Li, HKSC
member; Duona Luo, HKSC Publicity head; Salahuddin Raju, HKSC cochair; Prof. C. Patrick Yue, HKSC advisor; Dr. Hirotaka Tamura; Prof. Jri
Lee; Prof. Sam Palermo; Guang Zhu, HKSC treasurer; Liusheng Sun, HKSC member; and Babar Hussain, HKSC member.

inputs–outputs (I/Os) for the future
ICT systems, with reviewing the imp­
lication of CMOS scaling on the
I/O performance.
On the second day, Dr. Salahuddin
Raju, a postdoctoral student at HKUST,
introduced the invited speaker, Lee.
Lee spoke about advanced clock and
data recovery circuits for high-speed
wireline systems. Yue gave the work-
shop’s closing talk about recent devel-
opments in transceiver SoC design for
next-generation optical networks. He
presented a 4-Gb/s fiber-to-mm-wave were followed by Q&A sessions and
baseband-over-fiber (BoF) modula- a panel discussion.
tor SoC using 65-nm CMOS with a
fully integrated 850-nm wavelength
optical receiver front-end for short-
range backhaul. He also described —Khawaja Qasim Maqbool
the design considerations for an Chair, IEEE SSCS Hong Kong
improved 10-Gb/s BoF I/Q modulator Student Chapter
SoC with integrated mm-wave po­­
wer amplifier.
The four speakers interacted with —Prof. C. Patrick Yue
the students and other attendees du­­­­ Advisor, IEEE SSCS Hong Kong
ring the two-day event. The lectures Student Chapter

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 115

Distinguished Lecture by Dr. Dennis Sylvester
Organized by SSCS-Seoul

T
The IEEE Solid-State Circuits Soci-
ety (SSCS) Seoul Chapter organized
a Distinguished Lecture, “Ultra-Low
Power Circuits and System Design,”
by Dr. Dennis Sylvester, Univer-
sity of Michigan, Ann Arbor. The
lecture was held on 18 July 2017
at Seoul National University, Korea,
and attracted a number of students,
researchers, and engineers from
academia and industry.
The lecture started with the fun-
damentals of the low-power circuit
design technology including relax-
ation oscillators, digital logic, and
power management. Sylvester pre- Dr. Dennis Sylvester presents his talk, “Ultra-Low Power Circuit and System Design.”
sented recent progress in ultra-low-
power circuit and system design,
with application to the Internet of
Things and wireless sensing micro-
systems. Following his lecture, he
answered questions from the audi-
ence and shared the future direc-
tions for the ultra-low-power circuit
and system design.

—Prof. Yong Moon

Chapter Chair, SSCS Seoul

Digital Object Identifier 10.1109/MSSC.2017.2746172

Date of publication: 16 November 2017 Dr. Dennis Sylvester with the members of the SSCS-Seoul Chapter and event attendees.

Pietro Andreani Gives Distinguished Lectures

in Honolulu and Toronto

P
Prof. Pietro Andreani gave two Dis-
tinguished Lectures at the IEEE Solid-
State Circuits Society (SSCS) and
IEEE Electron Devices Society Joint
Honolulu Chapter and the SSCS
Toronto Chapter. Andreani’s first stop
Digital Object Identifier 10.1109/MSSC.2017.2746173
Date of publication: 16 November 2017
was the Honolulu Chapter, where he
gave a talk, “RF Integrated Harmonic
Oscillators in Silicon Technologies,”
which was held at the University of
Hawaii Manoa Campus on 6 June 2017.
The lecture was organized by Dr.
Kishore Erukulapati, vice-chair of the
Hawaii Chapter. Six people attended
the lecture.
Andreani’s next stop was the
Toronto Chapter, where he presented
the same talk. There were 15–20 peo-
ple in attendance, including faculty,
Ph.D. students, and people from
industry. Andreani received many
questions from the audience, includ-
ing some about phase accuracy and
phase noise.

116 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Abstract
As one of the truly fundamental ana-
log functions in any wireless/wireline
application, the voltage-controlled
oscillator keeps attracting a great
deal of well-deserved attention. In
this presentation, we will investi-
gate the mechanisms of phase noise
generation in harmonic oscillators,
including some recently published
general results, after which we will
analyze both classical and emergent
oscillator architectures, describ-
ing pros and cons for each. Vari-
ous techniques to achieve a very wide
oscillator tuning range will be illus- Prof. Pietro Andreani (right) at the Honolulu Chapter with lecture organizer Dr. Kishore
trated as well. Erukulapati.

SSCS Saintgits Student Chapter Holds Workshop on

Modeling and Simulation of MEMS Using Intellisuite Software

T
The IEEE Solid-State Circuits Society sensors in detail and started with criteria. For example, participants
(SSCS) Saintgits Students Chapter the design procedure of the sensor were asked to design a maximum
organized a workshop, “Modeling using Intellisuite 8.2. He also empha- deflection of the membrane smaller
and Simulation of MEMS (Micro- sized the different criteria that had to than 1/5th of the thickness. He also
electromechanical Systems) Using be considered while designing a pressure explained that a blueprint is noth-
Intellisuite Software” on 6–7 August sensor. Following the explanation and ing but a platform that gives an idea
2017. Sripadaraja K., application demonstration, participants designed about how to arrange different lay-
engineer, IntelliSense Software Pvt. the pressure sensor according to given ers of a design.
Ltd., led the comprehension session
and interactive session.
The session began with a prayer.
Er. Ajith Ravindran, Saintgits SSCS
advisor, welcomed and introduced
Sripadaraja K. The session started
with an introduction to Intellisuite
software. Sripadaraja K shed light
on MEMS and the different applica-
tions of MEMS. He talked about the
basics of the Intellisuite software
by introducing all of its tools. He
explained the workings of pressure

Digital Object Identifier 10.1109/MSSC.2017.2746174

Date of publication: 16 November 2017 Participants of “Workshop on Modeling and Simulation of MEMS Using Intellisuite Software.”

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 117


Sripadaraja K. talks to students about MEMS and the different applications of MEMS.
Japan Chapter Holds VLSI Symposium on Circuits
Technical Seminar and Distinguished Lecturer Program
O
On 15 June 2017 at the University
of Tokyo, Japan, the IEEE Solid-State
Circuits Society (SSCS) Japan Chap-
ter held a technical seminar about
the VLSI Symposium on Circuits
2017. Held one week after the 2017
Symposia on VLSI Technology and
­Circuits, the seminar presented 12
excellent papers from Japan from
Digital Object Identifier 10.1109/MSSC.2017.2746175
Date of publication: 16 November 2017
The attendees of the technical seminar on VLSI Symposium and the Distinguished Lecture.
118 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
VLSI Symposium to those who did
not attend the conference. Prior to
the seminar, Prof. Makoto Ikeda,
VLSI Symposium on Circuits Pro-
gram chair, presented the VLSI Sym­­
posium review; he encouraged pa­per
subm ission s f r om Jap a n t o t h e
2018 symposium.
After the technical presentations,
the SSCS ­Kansai Chapter organized
a ­
technical ­
seminar by SSCS Distin-
guished Lecturer Dr. Hirotaka Tamura
On the second day of the work-
shop, Sripadaraja K. introduced
another tool used to represent dif-
ferent process flows like wafer prep-
aration, implantation, and etching
after which various simulations are
carried out. During the afternoon
session, the electrical analysis of the
sensor was completed. The dynamic
analysis of the sensor, consisting of
a plot of stress and displacement,
was then observed by participants.
There were 22 participants at the
training session, consisting of members
of faculty, academia, and students.
—Ajith Ravindran
Advisor, SSCS Saintgits
Student Chapter
about architecture- and transistor-
level design for complementarymetal-
oxide-­semiconductor high-speed sig-
naling circuits. This hot topic was well
received by the audience and resulted
in a very active discussion. The total
number of attendees was 67, includ-
ing 33 IEEE Members.
—Tetsuya Iizuka
Secretary,
SSCS Japan Chapter
IEEE SSCS Distinguished Lecture at Macquarie University

T
The IEEE New South Wales (NWS)
Circuits and Systems (CASS), IEEE Solid-
State Circuits Society (SSCS), IEEE Elec-
tron Devices Society (EDS), and IEEE
Photonics Society (PHO) Joint Chap-
Digital Object Identifier 10.1109/MSSC.2017.2746176
Date of publication: 16 November 2017
ter hosted Prof. Woogeun Rhee, Tsin-
ghua University, Beijing, China, for
a Distinguished Lecture. The talk,
“Phase-Locked Frequency Synthesis
and Modulation for Modern Wire-
less Transceivers,” took place at the
School of Engineering, Macquarie
University, Sydney, Australia, on
Thursday, 10 August 2017. The pre-
sentation generated lively discus-
sions that carried on after the event
over light refreshments.
—Ediz Cetin
Chapter Chair, IEEE NSW
CASS/SSCS/ED/PHO Joint Chapter

Prof. Woogeun Rhee (left) with Dr. Ediz Cetin, chair, IEEE NSW CASS/
SSCS/ED/PHO Joint Chapter. Prof. Woogeun Rhee delivering his IEEE SSCS Distinguished Lecture.

Attendees at the IEEE SSCS Distinguished Lecture by Prof. Rhee.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 119

SSCS Kolkata Chapter Holds Summer Training

T
The IEEE Solid-State Circuits Society
(SSCS) Kolkata Chapter held a one-
month summer training session,
“VLSI (Very-Large-Scale Integration)
and Embedded System” 27 June to
19 July 2017 at the MCKV Institute of
Engineering, Howrah, West Bengal,
India. There were 17 participants in
this course for engineering students.
Subhasish Banerjee, assistant
professor, Department of Electron-
ics and Communication Engineering
(ECE), MCKV Institute of Engineer-
The summer school organizers, coordinators, and participants.
ing, gave two talks, “Fundamentals
of Solid-State Electronics,” and “VLSI
Design Cycle,” and held a VLSI cir-
cuit design lab session. In his theory
session, he explained fundamen-
tals of metal-oxide-semiconductor
field-effect transistor (MOSFET) and
VLSI design cycles. During his lab
session, he explained the circuit
and layout design of VLSI circuits
using Tanner EDA tools, along with
Sagar ­Mukherjee.
Kalyan Biswas, assistant profes-
sor, Department of ECE, MCKV Ins­ Summer school attendees participate in lab sessions.
titute of Engineering, gave the talk
“Microelectronics Fabrication Tech-
nology.” He explained the fundamen-
tals of microelectronics fabrication
techniques required for complemen-
tary metal-oxide-semiconductors.
Dr. Swarup Kumar Mitra, associ-
ate professor, Department of ECE,
MCKV Institute of Engineering, gave
a talk, “Circuit Design Using Verilog,”
and helped with a lab session using
Verilog and field-programmable
A theory session.
gate arrays (FPGAs). Dr. Mitra talked
about the fundamentals of digital
circuit design and the application of also explained the download of the a layout design theory and lab. he
Verilog in combination with circuit Verilog program in FPGAs. explained the fundamentals of MOS-
design. During the lab session, he Sagar Mukherjee, assistant pro- FET circuit design. During the lab
explained the circuit design of VLSI fessor, Department of ECE, MCKV sessions, he explained circuit and
circuits using Xilinx EDA tools. He Institute of Engineering, talked about layout design of VLSI circuits using
VLSI circuit design and held two Tanner EDA tools.
Digital Object Identifier 10.1109/MSSC.2017.2746177 lab sessions: a VLSI circuit design
Date of publication: 16 November 2017 lab session using Tanner EDA and —Abira Sengupta

120 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Prof. Jerald Yoo Visits SSCS New York Chapter
T
The IEEE New York Solid-State Cir-
cuits Society (SSCS) and Electron
Devices Joint Chapter held a Dis-
tinguished Lecture on 1 June 2017.
Prof. Jerald Yoo, Department of Elec-
trical and Computer Engineering,
Singapore Institute for Neurotech-
nology, National University of Sin-
gapore, gave the lecture “On-Chip
Epilepsy Detection: Where Machine
Learning Meets Wearable, Patient-
Specific Seizure Monitoring.”
In his talk, Yoo first showed how
challenging a wearable environment
is, with 50/60-Hz noise, electrode dc
offset, 1/f noise, baseline drift, etc.
Starting from a basic instrumenta-
tion amplifier, he introduced design
strategies with detailed examples to
mitigate such challenges.
In the second part of the lecture,
Yoo showed how machine learning
can be used to achieve a patient-spe-
cific seizure detection system. Sei-
zure detection is very challenging
because seizure pattern is very dif-
ferent from each patient; by adopt-
ing machine learning, the circuit can
“learn” each patient’s seizure electrical
onset and monitor such events in real
time. When the seizure is detected,
Digital Object Identifier 10.1109/MSSC.2017.2746178
Date of publication: 16 November 2017
Prof. Jerald Yoo and a few of the attendees of the 1 June lecture.
a raw electroencephalogram will
be recorded for further analysis, and
transcranial electrical stimulation
may be applied at the same time. He
also emphasized that, in this case,
deep learning may not be the best
choice because there are not enough
training sets.
Despite it being summer vaca-
tion, around 25 students attended
the seminar. After Yoo’s lecture, stu-
dents asked many questions and
engaged in a fruitful discussion.
Abstract
Epilepsy is a severe and chronic neuro-
logical disorder that affects over 65 mil-
lion people worldwide. Yet current
seizure/epilepsy detection and treat-
ment largely relies on a physician in­­­­
terviewing the subject, which is not
effective in the infant/children groups.
To expand the be­­neficiary group to in-
fants, a wearable form-factor, patient-
specific system design with machine
learning is crucial to mitigate and even-
tually prevent many chronic diseases.
However, the wearable environment
is challenging for circuit designers
due to its unstable skin-electrode in-
terface. Wet and dry electrodes have
significantly different electrical char-
acteristics that needs to be addressed.
Also, in such an environment, the trad-
IEEE SOLID-STATE CIRCUITS MAGAZINE
eoff between available resources and
performance among the components,
both in the analog front end and the
digital back end, is crucial.
This lecture will cover the design
strategies of sensor interface cir-
cuits for such wearable sensors. We
will first explore the difficulties,
limitations, and potential pitfalls in
wearable interfaces and strategies
to overcome such issues. After that,
system-level considerations for bet-
ter key metrics such as energy effi-
ciency will be introduced. Starting
from a 1 op-amp instrumentation
amplifier (IA), we will cover vari-
ous IA circuit topologies and their
key metrics to deal with offset com-
pensation. Several state-of-the-art
instrumentation amplifiers that
emphasize different parameters
will also be discussed. We will then
see how the signal analysis part
impacts the analog interface circuit
design. Finally, an on-chip epilepsy
detection and recording sensor
system-on-chip will be presented,
which integrates all the components
covered during the lecture. The lec-
ture will conclude with interest-
ing aspects and opportunities that
lie ahead.
—Abira Sengupta
fa l l 2 0 17 121
ReSMiQ Annual Symposium 2017 Features
an IEEE SSCS Distinguished Lecture Seminar in Montreal

T
The IEEE Solid-State Circuits Society
(SSCS) Montreal Chapter presented
a Distinguished Lecture seminar
during the ReSMiQ Annual Sympo-
sium 2017 at Polytechnique Montreal,
Quebec, Canada, on 26 May 2017.
This event was organized by Micro-
systems Strategic Alliance of Québec
(ReSMiQ ) and supported by the SCSS
Montreal Chapter and Polytechnique
Digital Object Identifier 10.1109/MSSC.2017.2746187
Date of publication: 16 November 2017
Montreal. The main topic was “Solid-
State Circuits for the Internet of Things.”
More than 50 attendees in­­cluding
faculty members, students, and indus-
trial representatives from Quebec, Can-
ada, were present.
The event started with welcoming
remarks by Prof. Mohamad Sawan,
president of the SSCS Montreal Chap-
ter and the director of ReSMiQ. He
brief ly introduced ReSMiQ to the
audience and talked about SSCS mem-
bership benefits.
Two Distinguished Lectures were
given. Edith Beigné, from CEA-LETI,
Grenoble, France, presented “Asyn-
chronous Design: a Design and System
Solution for Ultra-Low Power Internet
of Everything,” and Dennis Sylvester
from the University of Michigan, Ann
Arbor, presented “Ultra-Low Power IC
Design 101.”
ReSMiQ member Frédéric Nabki,
from École de Technologie Supéri-
eure (ETS), Montreal, Canada, talk­­­­­
­e d about research done at Micro2

Mohamad Sawan, president of the SSCS Montreal Chapter and

director of ReSMiQ. Frédéric Nabki, ReSMiQ invited member, from ETS, Quebec, Canada.

Attendees of the Annual Symposium of ReSMiQ 2017, featuring an SSCS Seminar at Polytechnique Montreal, Quebec, Canada.

122 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

Edith Beigné, SSCS Distinguished Lecturer,
from CEA-LETI, Grenoble, France. Dennis Sylvester, SSCS Distinguished Lecturer, from the University of Michigan.

Laboratory in the lecture “From Micro-

electronics to Integrated Circuits:
the Infinite Possibilities of the Infi-
nite Small.”
Two industrial representatives
from Quebec, Geneviève Ouellet, pre­­
sident of the Electronic Industry
Group (RIE), and François Verdy-Goy-
ette, vice president, Sales and Mar-
keting Enterprise Group V3, gave
two talks concerning the current
state and challenges of the electron-
ics industry in Quebec, Canada.
The program also included a pos­
ter contest, where 19 graduate stu-
dents from eight universities in Que- The judges evaluating the student posters.
bec presented their research results.
The poster session was preceded by
plenary room, presentations where The judges evaluated the stu- ception d’un E metteur-Récep ­
students were tasked with talking dent s’ shor t pr esent at ion s a nd te­u r d’Impulsions à Bande Ultra
about their project background, the posters and awarded three prizes: Large (UWB)
methodology, and the most relevant o n e first-place and t wo second- ■ ■ second place: Ali Sarafnia, Con-

results in just 3 min. The judges
were three local professors, Yvon
Savaria, Réjean Fontaine, and Yves
Audet, and SSCS Distinguished Lec-
turers Edith Beigné and Dennis Syl-
vester. The judges were impressed
by the quality of research present­
­ed in the fields of information tech-
nology, avionics, biomedical, and
place winners:
■ ■ first place: Jonathan Bouchard,
Université de Sherbrooke, “Sys-
tème de Comptage de Photons
Corrélé en Temps à Faible Coût
pour la Tomographie Optique Dif-
fuse à Mesure Dans le Domaine
Temporal”
■■ second place: Rabia Rassil, Ecole
cordia University, Introduction du
Paramètre de Contrôle de la Direc-
tivité Adaptative pour les Tableaux
de Microphones Différentiels Ori-
entables de Premier Ordre.
The event closed with an award
ceremony and a networking cock-
tail reception.

telecommunication. de Technologie Supérieure, Con- —Mohamad Sawan

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 123

SSCS Kolkata Chapter Holds One-Day Workshop

T
The IEEE Solid-State Circuits Society
(SSCS) Kolkata Chapter held a one-
day workshop, “SoC Design Using
Ve r i log.” T h e eve nt w a s h e ld at
t h e Department of Electronics and
Communication Engineering, MCKV
Institute of Engineering (MCKVIE),
How rah, West Bengal, India, on
20 June 2017. The workshop attracted
16 participants. The course instruc-
tors were Dr. Swarup Kumar Mitra,
associate professor, Department
of Electronics and Communication
Dr. Swarup Kumar Mitra speaks about Verilog.

Mitra talked about

the fundamentals of
digital circuit design and
application for Verilog
in combination with
circuit design.

E ng ineer ing, M C K V I E ; Dr. S aga r

Mukherjee, assistant professor, De­­
partment of Electronics and Com-
munication Engineering, MCKVIE;
and Indranil Hatai, assistant profes-
sor, School of VLSI (very-large-scale
integration) Indian Institute of Engi-
neering Science and Technology. Sagar Mukherjee talks about FPGAs.
Mitra talked about the fundamen-
tals of digital circuit design and appli-
cation for Verilog in combination with
circuit design. He ex­­­plained sys-
tem-on-chip (SoC) using Verilog and
the importance of field-programmable
gate array (FPGA) as a platform of SoC
implementation. Mukherjee explained
the fundamentals of FPGA architecture
and the method of hardware software
codesign involving FPGA and Verilog in
the implementation of SoC. Hatai dis-
cussed different SoC design method-
ologies including VLSI design cycles.
He discussed the requirement of Ver-
ilog in the designing of the SoC system
and the different applications of SoC in
the world of electronics. Indranil Hatai discusses SoCs.

Digital Object Identifier 10.1109/MSSC.2017.2746188 —Abira Sengupta

Date of publication: 16 November 2017 

124 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 People

SSCS Rising Star: In Step with Reza Erfani

Meshing Art with Engineering

R
Reza Erfani is an electrical engineer
by career, but his love of art is some-
thing that he has always been pas-
sionate about. When he entered the
2016 IEEE Solid-State Circuits Soci-
ety (SSCS) Student T-Shirt Design
Contest, he was able to merge his
career with his hobby. Reza won
the contest, designing a t-shirt that
illustrated the cool technologies of
circuit design. The t-shirt was dis-
tributed at the International Solid-
State Circuits Conference to more
than 350 SSCS student members.
“I’ve been interested in art since
I was a child and had not thought
about doing a project until I entered
the SSCS t-shirt design contest,” Reza Reza’s presentation, “Amplitude-Engraving Modulation (AEM) Scheme for Simultaneous
said. ‘It was exciting that I was able Power and Data Transfer to Biomedical Implants,” at IEEE BioCAS 2013 in Rotterdam,
The Netherlands.
to merge my hobby with my career.”
Reza is currently a Ph.D. can-
didate in electrical engineering in capacitive links. Reza’s research, Technology, Tehran, Iran, in 2014.
the Electrical Engineering and Com- de­­s igning implantable biomicro- Both degrees are in electrical engi-
puter Science (EECS) Department at systems, is categorized into two neering. He worked as a senior RF
Case Western Reserve University parts: complementary metal-oxide-
(CWRU), Cleveland, Ohio, where he semiconductor IC design and the
is conducting research on develop- wireless link solution capable of
ing the next-generation implant- delivering a high level of wireless
able biomicrosystems for interfacing power and high-rate data.
with the peripheral nervous sys- Reza received his B.S. degree
tem employing novel techniques from Shahid Rajaee University, Teh-
for transcutaneous wireless power ran, Iran, in 2010 and his M.S. degree
transfer and data telemetry using from the K.N. Toosi University of

This article is part of a series highlight- Fun Facts about Reza

ing an SSCS member. Once a year, we
will highlight a “Rising Star.” To apply or
nominate someone, please e-mail Abira
Sengupta (abira.sengupta@ieee.org)
Digital Object Identifier 10.1109/MSSC.2017.2746189
Date of publication: 16 November 2017
■ Reza’s father is an artist.
■ Reza enjoys playing music and sing-
ing as a hobby.
■ He plays intramural soccer and volley-
ball at CWRU, and his team won the
Reza presented “Transcutaneous Capacitive
championship. Wireless Power Transfer (C-WPT) for Bio-
medical Implants” at ICAS 2017, Maryland.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 125

Reza (left) with SSCS Membership Chair Patrick Yue, both wearing
Reza’s winning design of the 2017 SSCS student t-shirt design (From left) Fatemeh Marefat, Prof. Amir M. Sodagar, Prof. Pedram
contest. Mohseni, and Reza Erfani.

Reza (bottom, far left) with his teammates at the Intramural

Case Western Reserve University indoor soccer championship in Reza and his wife Fatemeh at the Great Smokey Mountains in Gatlin-
March 2017. burg, Tennessee.

Electrical and Computer Engineering

Reza’s live performance at an event called Yalda Night.
engineer from 2010 to 2012 where he
focused on the design of RF ­modules
such as frequency synthesizers and
quaternary phase-shifting keying
transceivers for multiple-input, multi-
ple-output orthogonal frequency-
division multiplexing systems. In the
fall of 2011, he joined the Integrated
Circuits and Systems (ICAS) Laborato-
ry run by Prof. Amir M. Sodagar at the
De­­part­­ment, K.N. Toosi University of
Technology, where he worked on the
wireless telemetry of data and power to
biomedical implants. In January 2015,
Reza joined the BioMicroSystems Labo-
ratory run by Prof. Pedram Mohseni
at the EECS Department, CWRU.
One of Reza’s biggest aspirations
is that one day his research will help
push the limit for fully implantable,
wireless, and functional bioelec-
tronics devices to be accessible to ev-
ery patient around the world. These
devices would aid with curing most
diseases. “Even compared to the past
decade, researchers have pushed the
limits in solid-state circuits research,”
Reza said.
Reza added that the SSCS has im­­
pacted his life greatly—both profes-
sionally and personally.

126 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE


Reza and his wife Fatemeh at Yalda Night
in December 2016.
“It goes without saying that the
SSCS is well known for hosting the
highest-quality solid-state circuit
SSCS Member-at-Large Behzad Razavi Receives
the IEEE CAS John Choma Education Award
I
IEEE Solid-State Circuits Society (SSCS)
Member-at-Large Prof. Behzad Razavi
is the recipient of the 2017 IEEE Cir-
cuits and Systems (CAS) Society John
Choma Education Award for his sem-
inal books and his global impact on
circuits education.
The IEEE CAS John Choma Edu­
cation Award honors individuals with
exceptional contributions to educa-
tion in a field within the scope of the
CAS Society. The publication of text-
books, research supervision of grad-
uate and undergraduate students,
short course development, and par-
ticipation in continuing education are
contributions that a recipient must
meet to receive this award.
Digital Object Identifier 10.1109/MSSC.2017.2746190
Date of publication: 16 November 2017
conferences,” Reza said. At SSCS con-
ferences, Reza learned about state-of-
the-art technology demonstrations,
and IC career opportunities. He edu-
cated himself by attending tutorial
sessions and short courses.
“Although the main goal of the
Society is to influence members’ pro-
fessional lives and provide career
opportunities, there have definitely
been situations where SSCS has
impacted my life,” Reza said. The
student t-shirt design contest was a
great opportunity for him. “It was
a fun and fascinating opportunity,”
Reza said.
Outside of his professional life,
Reza loves to share his Persian cul-
ture. He enjoys organizing cultural
and social events with his friends
and uniting people from different
Behzad Razavi
Prof. Razavi said that it was a tre-
mendous honor to receive this award.
“I am delighted that the IEEE Circuits
and Systems Society has recog-
IEEE SOLID-STATE CIRCUITS MAGAZINE
cultures. Reza is currently the presi-
dent of the Case Iranian Society
(CIS). The CIS strives to share the
rich Iranian culture with the entire
CWRU community and unites Ira-
nian students, helping them main-
tain their heritage.
Reza also enjoys singing and playing
music. Recently, the CIS or­­ganized an
event called Yalda Night (Yalda Night
is the longest night of the year where
Persians will get together and cel-
ebrate victory of light over darkness),
where Reza per­­formed classic pieces of
Persian music for over 150 attendees.
Reza likes to keep active and is very in-
volved in sports such as hiking, skiing,
volleyball, and soccer.
—Abira Sengupta
nized my education efforts and my
commitment to inspiring students
and engineers,” Prof. Razavi said. For
almost a quarter of a century, Razavi
has educated and excited students and
engineers from all over the world. From
his textbooks and papers to lectures
and seminars, his teaching and spirit
have inspired and shaped people’s inter-
est in circuits.
Razavi published his first textbook
while working at AT&T Bell Laborato-
ries and teaching courses at Princeton
University. The book covered the analy-
sis and design of data converter cir-
cuits. He also edited and published
a compendium of IEEE papers on
phase-locked loops in 1995. In 1996,
Razavi joined the University of Califor-
nia, Los Angeles (UCLA). He created new
courses on radio-frequency (RF) circuits
and systems and data converters, both
fa l l 2 0 17 127

Prof. Razavi’s YouTube lecture on undergraduate electronics.
of which are still being offered more
than 20 years later. At UCLA, Razavi
started his own research program and
wrote a textbook on RF microelectron-
ics. This book has been translated
to multiple languages and has been
cited approximately 4,500 times.
In 1999, Razavi published Design
of Analog CMOS Integrated Circuits,
a textbook dedicated to modern
analog design. The book received
the McGraw-Hill First Edition of the
Year Award. Often called the bible
of analog design, this book has
been cited 8,000 times and has been
translated into Chinese, Japanese,
and Korean.
Why I’m an SSCS Member: Alvin Loke
A
Alvin Loke is a long-time IEEE Solid-
State Circuits Society (SSCS) mem-
ber. He first became involved with
the Society 15 years ago, where he was
a pivotal part of the SSCS Denver
Chapter. Since then, Alvin has made
Digital Object Identifier 10.1109/MSSC.2017.2746191
Date of publication: 16 November 2017
128 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
With the demand for high-speed opti-
cal transceivers growing, Razavi pub-
lished a textbook, Design of Integrated
Circuits for Optical Communications, in
2003. In 2008, Razavi published his
fifth book, the undergraduate text Fun-
damentals of Microelectronics.
Recognizing the impact of massive
online open courses and online learn-
ing, in 2014 Razavi produced a series of
videos on undergraduate electronics.
The videos have been viewed 600,000
times. Currently, Prof. Razavi is work-
ing on a series of short online videos
for the SSCS called SSCSx.
A member of the U.S. National Acad­
emy of Engineering and recipient of nu-
many major contributions to the SSCS,
including being a Distinguished Lecturer
and serving as North America’s webi-
nar coordinator.
Why Did You Join SSCS?
I joined the Solid-State Circuits Society
(SSCS) in 2002. At the time, I didn’t know
much about SSCS as I was an IEEE Elec-
Prof. Razavi with his books and their
translations
merous research and teaching awards,
Razavi has graduated more than 20
Ph.D. students and taught short cours-
es at major conferences including the
International Solid-State Circuits Confer-
ence, Custom Integrated Circuits Confer-
ence, and VLSI Symposium.
“Receiving this award reinvigorates
my dedication to teaching the members
of our community at UCLA, within SSCS,
within IEEE, and around the globe,” Razavi
said. “I have initiated several projects
along these lines working on more video
tutorials, another textbook, and a self-
driving car project for UCLA students.”
—Abira Sengupta
tron Device Society member only. As
my career transitioned from technol-
ogy development to circuit design,
it was the natural step to join the
SSCS. At the time, I was interested
in getting involved with the SSCS Den-
ver Chapter in Fort Collins, Colorado,
which was just formed thanks to the
initiative of founding Chapter Chair
Randy Rannow and encouragement
of President (then Chapters chair)
Jan van der Spiegel. It was exciting
because Fort Collins did not have a tech-
nically vital circuits community despite
extensive circuits development in the
local industry.
I wanted to bring in speakers
and learn more about what we’re so
passionate about and share it with
others, something that became a
part of me after studying in Silicon
Valley. What made the experience
so enjoyable and rewarding was the
amazing team of dedicated Chapter
volunteers—my wife Tin Tin Wee, Bob
Barnes, Don McGrath, Bruce Doyle,
and Steve Martin—who genuinely
cared about helping the community.
We never would have imagined that
a humble grassroots effort would be Eric Vittoz (DL, second from left) was hosted by IEEE Denver Chapter officers (From left): Don
recognized as the 2005 SSCS Chapter McGrath, Bob Barnes, Tin Tin Wee, and Alvin Loke). March 2004.
of the Year.

How Has SSCS Impacted

Your Career?
SSCS has been the rock in my pro-
fessional career. I was a very active
officer in the Denver Chapter for ten
years. During this time, our Chapter
organized over 90 seminars, many
by famous and prolific experts in
our global community. When you
host experts for visits and talks,
their wisdom rubs off on you. They
tell you things and offer advice—not
just technical insights but career
and life mentoring. Many high-tech
companies today are too focused
on a quick return on investment
without investing much in mentor-
The September 2013 DL tour in Porto Alegre, Brazil (from left): Alvin Loke, Sergio Bampi, and
ing relatively new and impression-
Jake Baker).
able new grads. Thankfully, we are
blessed to belong to a community
full of technical powerhouses, many the world and see how different Chap-
of whom are genuine and gener- ters ran. SSCS has given me a lot, and I
ous individuals. feel obligated to spend time helping the
The IEEE Solid-State Circuits Society My SSCS Chapter involvement be­­ Society in whatever small way I can.
(SSCS) recently introduced its new fea- came the foundation for building
ture in the “People” column. The “Why many new friendships as well as per- Why Should Someone
I’m an SSCS Member” feature highlights sonal confidence. The connections gave Become an Sscs Member?
the importance and benefits of Soci- me the opportunity to publish my work, There are many facets to being an
ety membership, and what it means to which led to participating in the Custom SSCS member. The Society truly gives
be a member of IEEE. Tell us why you’re Integrated Circuits Conference techni- you a sense of community. Being a part
an SSCS member; e-mail abira.sengupta@ cal committee. It also led to a two- of the SSCS family has unquestionably
ieee.org to be featured. year stint as a Distinguished Lecturer, become a part of my professional and
where I had the opportunity to travel personal identity. The SSCS membership

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 129

fee (and IEEE membership for that mat-
ter) is small for what you get. One of
the greatest parts of SSCS is belonging
to a community that has contributed so
much to advancing humanity. It’s a rela-
tively small community, and we’re all in
this together. I can’t emphasize the net-
working aspect enough. In a time where
the industry is moving fast and job
security is nonexistent, the network of
people you’ll meet through SSCS is the
only real insurance you have to make
sure you’re gainfully employed.
Alvin Loke
Alvin Loke received the B.A.Sc. de­­gree in
engineering physics with highest honors
JxCDC Editor-in-Chief Ian Young Receives
the IEEE Frederik Philips Award
I
IEEE Solid-State Circuits Society
member and IEEE Journal on Explor-
ator y Solid-State Computational
Devices and Circuits (JxCDC) Editor-in-
Chief Dr. Ian Young is the recipient of
the 2017 IEEE Frederik Philips Award.
The IEEE Frederik Philips Award, spon-
sored by Philips Electronics N.V., was
established in 1971. The award is
given for outstanding accomplish­ments
in the management of re­­search and
development resulting in effective
innovation in the electrical and elec-
tronics industry. Young received the
IEEE Frederik Philips Award “for leader-
ship in research and development on
circuits and processes for the evolu-
tion of mi­­c roprocessors.” A short
interview with Young follows.
Digital Object Identifier 10.1109/MSSC.2017.2746192
Date of publication: 16 November 2017
130 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
Alvin Loke
from the University of British Columbia
and the M.S. and Ph.D. degrees in electri-
Ian Young
How Did You Feel After Winning
This Award, Was it a Total Surprise?
I had never expected to be considered
for such a prestigious IEEE award,
let alone becoming a recipient. I
feel very fortunate since there are
plenty of other people who deserve
cal engineering from Stanford University.
He worked on complementary metal--ox-
ide-semiconductor (CMOS) integration
for several years and has been design-
ing circuits for a variety of wireline links
and addressing next-generation CMOS
design concerns while at Agilent, AMD,
and now at Qualcomm, where he is a
principal engineer. He has authored sev-
eral dozen publications and 21 patents.
He has served as a Custom Integrated
Circuits Conference committee member,
IEEE Chapter chair, guest editor of IEEE
Journal of Solid-State Circuits, and IEEE
Distinguished Lecturer.
—Abira Sengupta
this award. I am very thankful to the
people who went out of their way to
support my nomination. What made it
even more special was that Dr. Gordon
Moore, the cofounder of Intel, was a
recipient of this award in 1979. He
has been my inspiration throughout
my career.
How Will Winning This Award Affect
Your Work at Intel and with the IEEE?
I hope that the IEEE recognition of
my work will show Intel engineers
and scientists that our work contrib-
utes not only for the benefit of our
company but also toward the prog-
ress of the semiconductor industry
as a whole. To me, this IEEE award
reaffirms that we are part of a large
industry all working together to
make products that improve the
society. While software engineer-
ing has been getting much attention
in recent years, my hope is that the
semiconductor industry will con-
tinue to attract the next generation
of innovative technologists because
there is much challenging and excit-
ing work ahead of us.
Please Describe the Work
You’ve Done that Led to You
Receiving This Award
My work during the early 1990s contrib-
uted to Intel microprocessor speed-
performance through the in­­ vention
and implementation of the first fully
integrated phase locked loop (PLL) mi-
croprocessor clocking circuit, which
revolutionized the rate of micropro-
cessor clock frequency throughout
the semiconductor industry. This in-
vention was used on all the microproces-
sor products Intel shipped from 1991 to
the processors being shipped even today.
It was the industry’s first complex
analog circuit implemented in a di­­­­gital
logic complementary metal-oxide-
semiconductor (CMOS) process without
requiring the integration of any special
precision elements.
I developed a benchmarking meth-
odology for the cooptimization of
the process definition with circuit
requirements. It involved defining cir-
cuits that could identify the transistor
and interconnect technology directions
to improve processor performance. This
benchmarking has been used in each
generation of process technology devel-
opment since Intel’s 0.25-μm CMOS pro-
cess development and continues even to
the present. Today this cooptimization
methodology is used across the semi-
conductor industry.
I led a team of circuit designers to
overcome the analog-digital mixed-
signal circuit integration challeng­­es
in realizing 10-Gb/s high-speed se-
rial input–output (I/O) circuits on a
­processor. It was a significant achieve-
ment because these serial I/O circuits
replaced the legacy front side bus I/O ing circuits on microprocessors are
that had been the mainstay approach among the most-shipped analog cir-
for many generations of prior X86 cuit on IC chips to date.
processors and were also used to in- As a manager of static random-ac-
tegrate asynchronous cess memory design
PCI-express I/O on chip. a nd a n a log cir c u it
These high-speed se- design teams, he de-
Young received
rial I/Os enabled sig-
the IEEE Frederik
velop ed a pr o cess
nificant increases in
Philips Award
development and cir-
the performance of
“for leadership
cuit design cooptimi-
Intel processors. zation methodology, a
in research and
Since 2010, I have holistic approach to
development
focused my work on a optimize the micro-
on circuits and
new challenge, which processor performance,
processes for the
is to lead a research process density, and
evolution of mi­­
group defining the ma- yield. This integrat-
croprocessors.”
terials, devices, and ed methodology has
architecture for the been a significant con­­
beyond-CMOS IC tech- tributor toward the suc-
nology. These efforts are going to help cess of Intel microprocessor products
sustain not only Moore’s law but also since 1988. Today this cooptimization
to find the directions to make IC even methodology is used across the semi-
more capable and energy efficient. conductor industry. He lead a design
team that successfully laid the ground-
Ian Young work for the integration in a logic pro-
Ian Young is a senior fellow and director cess of analog mixed signal high-speed
at Intel Corporation. His current role is serial I/O circuits such as PCI-express
to lead the Intel research in beyond- and Intel Quick Path Interconnect on In-
CMOS devices and circuits in search tel microprocessors.
of the new semiconductor logic tech- He received the 2009 International
nology for the future energy efficient Solid-State Circuits Conference’s Jack
computing devices. Born in Melbourne, Raper Award for Outstanding Tech-
Australia, he received his bachelor’s nology Directions paper. He is a
and master’s degrees in electrical Fellow of the IEEE. He holds 74 issued
engineering from the University of Mel- patents in integrated technology
bourne, Australia, and subsequently and circuits and has published over
received his Ph.D. degree in electrical 120 technical papers. He served as
engineering from University of Califor- the Technical Program Committee
nia, Berkeley. chair of the 2005 International Solid-
He was a lead inventor of the ori­­ State Circuits Conference and was the
ginal Intel microprocessor (PLL) chair of the 1998 Symposium on VLSI
clocking circuits that drove the per- Circuits. He was a guest editor for IEEE
formance of Intel Pentium and Intel Journal of Solid-State Circuits and IEEE
Core processors from 50 MHz to over Journal of Selected Topics in Quantum
3 GHz. His innovation contributed to Electronics. He is currently the editor-
the rapid increase in the speed and in-chief of the new IEEE Journal on
performance of microprocessors Exploratory Solid-State Computational
through the 1990s while following Devices and Circuits.
Moore’s law scaling. The PLL clock- —Abira Sengupta
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 131
SSCS Vice President Bram Nauta Inducted to
the Royal Dutch Academy of Arts and Sciences

I
IEEE Solid-State Circuits Society
(SSCS) Vice President Bram Nauta was
inducted into the Royal Dutch Acad-
emy of Arts and Sciences in June.
Nauta is a professor at the Univer-
sity of Twente, heading the Integrated
Circuits Design group. His current
research interests are high-speed ana-
log complementary metal-oxide-semi-
conductor circuits, software-defined
radio, cognitive radio, and beamforming.
Academy membership is a great
honor in The Netherlands. The acad-
emy appoints a maximum of 16 new
members every year. Membership is
awarded based on an individual’s sci­­
entific and scholarly achievements.
Digital Object Identifier 10.1109/MSSC.2017.2746193
Date of publication: 16 November 2017
Bram Nauta
Once appointed, indiv iduals are
members for life. Members meet and
discuss issues of interest to science,
scholarship, and society. Academy
members represent a wide spectrum
of scientific and scholarly disciplines,
giving all members the opportu-
nity to embrace new fields in science
and scholarship.
Nauta was inducted as a result of
the work he performed throughout
his career and it was a great honor.
“It was a surprise for me,” Nauta
said, “especially because I’m an elec-
trical engineer working on the appli-
cation side of science.”
He hopes his induction will open
new doors for him, especially outside
his own scientific field.
For more information about the
Royal Dutch Academy of Arts and Sci-
ences, visit https://www.knaw.nl/nl.
—Abira Sengupta


A Circu it for All Sea sons (continued from p. 16)

+
+ VF + –
Vin +
VF − VF
– VF − VF

Flash
ADC
–
Vin + – 1.5 + –
– Vin − Vin Vin − Vin (LSB)
VF
CK1
CK2
(a) (b) (c)

Figure 10: (a) The flash stage preceded by a polarity detector and (b) the resulting characteristic and the characteristic in the presence of
comparator offset.

References Areas Commun., vol. 9, pp. 711–717, June

[1] M. E. Austin, “Decision-feedback equal-
ization for digital communication over
dispersive channels,” Tech. Rep. 437, Lin-
coln Laboratory, Aug. 1967.
[2] J. Jung and B. Razavi, “A 25 Gb/s 5.8 mW
CMOS equalizer,” IEEE J. Solid-State Cir-
cuits, vol. 50, pp. 515–526, Feb. 2015.
[3] S. Kasturia and J. H. Winters, “Tech-
niques for high-speed implementation of
nonlinear cancellation,” IEEE J. Selected
1991.
[5] R. Payne, P. Landman, B. Bhakta, S. Ra-
[4] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov,
W. Rhee, A. Rylyakov, H. A. Ainspan, B. D.
Parker, M. P. Beakes, A. Chung, T. J. Beu-
kema, P. K. Pepeljugoski, L. Shan, Y. H.
Kwark, S. Gowda, and D. J. Friedman, “A
10-Gb/s 5-tap DFE/4-tap FFE transceiver
in 90-nm CMOS technology,” IEEE J. Solid-
State Circuits, vol. 41, no. 12, pp. 2885–
2900, Dec. 2006.
maswamy, S. Wu, J. D. Powers, M. U. Er-
dogan, A. Yee, R. G. L. Wu, Y. Xie, B. Par-
thasarathy, K. Brouse, W. Mohammed, K.
Heragu, V. Gupta, L. Dyson, and W. Lee, “A
6.25-Gb/s binary transceiver in 0.13-um
CMOS for serial data transmission across
high loss legacy backplane channels,”
IEEE J. Solid-State Circuits, vol. 40, no. 12,
pp. 2646–2657, Dec. 2005.


132 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 SOC IET Y n e ws

SSCS Hosts Women in Circuits Bay Area Networking Luncheon

T
The IEEE Solid-State Circuits Society
(SSCS) hosted its first annual Women
in Circuits (WiC) Bay Area Network-
ing Luncheon on Friday, 14 July, in
Palo Alto, California. The luncheon
attracted over 30 attendees from the
Bay Area. The conversation flowed,
connections were made, and deli-
cious Italian fare was consumed at Il
Fornaio, Palo Alto.
The event began with opening
statements from Yildiz Sinangil, who
talked about the benefits of joining
the SSCS and the WiC initiative. She
spoke about the various network-
SSCS WiC member and luncheon organizer Yildiz Sinangil talks to attendees about the
ing opportunities for SSCS confer-
benefits of becoming an SSCS member.
ences and local Chapter events where
women can meet and interact with
each other and the many opportuni-
ties joining the WiC can lead to, such
as journal editorships, guiding pro-
grams at Chapters, and serving on tech-
nical program committees.
Following Sinangil’s talk, Apple
Vice President of Hardware Engineer-
ing Kate Bergeron spoke to the group,
touching on her experience as an
engineer over the past 25 years that
took her from Cambridge to a small
medical device company in Boulder
and then to Apple in Silicon Valley.
She encouraged the young women to
find what gives them satisfaction and
Apple Vice President of Hardware Engineering Kate Bergeron talked about her experience of
happiness in their careers, telling the being an engineer over the last 25 years.
audience, “I love seeing our team’s work
culminate in a product that will sur-
prise and delight our customers. That Bergeron also gave the group ad­­ nities and cha llenges that your
is what continues to inspire me and is vice on management and mentorship, employees have…Finding the bal-
the reason I come to work every day.” explaining, “As an employee, be honest ance between ‘too much’ and ‘not
with your manager. If you are strug- enough’ will be one of your most dif-
gling, ask for help. If you are crush- ficult challenges.”
Digital Object Identifier 10.1109/MSSC.2017.2746194 ing it, ask for more…As a leader, your Bergeron concluded her talk by pro-
Date of publication: 16 November 2017 job is to support both the opportu- moting communities like the SSCS

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 133

Rikky Muller, assistant professor at the University of California,
Berkeley, and cofounder of Cortera Neurotechnologies, talks Professor Tom Lee (far left) and Mojtaba Sharifzadeh (far right) with
about her career journey. luncheon attendees.

WiC luncheon organizer Yildiz Sinangil (center) with her

tablemates. Rikky Mueller (center) with luncheon attendees.

Everyone enjoyed the luncheon. SSCS Membership Chair Patrick Yue joins the WiC luncheon.

and other organizations in which women
are supported. She asked others to stay
involved and offer their support for the
broader community. “I ask that you
all carry a torch for women engineers, be
a change agent, and go forth to make a
bit more of a mess in the world. It can
actually be quite fun,” she said.
Rikky Muller, assistant profes-
sor at the University of California
Berkeley and cofounder of Cortera
Neurotechnologies Inc., discussed
her journey through the corporate,
st a r t-up, a nd a c a d e m i c w o r l d s .
Muller compared the three worlds and

134 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

talked about her lifestyle and career
for each category. She offered attend-
ees multiple pieces of advice: have
really great mentors, find your passion
and work on something you care about,
take risks, and, most importantly, do
what makes you happy.
SSCS Circuit Analysis and Design Contest
T
The IEEE Solid-State Circuits Soci-
ety (SSCS) is pleased to launch its
first Circuit Analysis and Simulation
Digital Object Identifier 10.1109/MSSC.2017.2746195
Date of publication: 16 November 2017
IEEE Solid-State Circuits Letters
A New IEEE Publication
T
The IEEE Solid-State Circuits Society is
pleased to introduce IEEE Solid-State
Circuits Letters (IEEE SSC-L), a new,
fast-turnaround publication in the
area of ICs. Aiming for a submission-
to-publication time of fewer than four
months in the first year and three
months thereafter, IEEE SSC-L invites
authors to submit papers that present
Digital Object Identifier 10.1109/MSSC.2017.2746196
Date of publication: 16 November 2017
Mojtaba Sharifzadeh, Chapter chair of
the Silicon Valley SSCS Chapter, talked
about the benefits of joining the Chap-
ter and how attendees can get involved.
In between and after each talk,
luncheon attendees had the opportu-
nity to meet and interact with each
Contest in Fall 2017. For details of this
contest, including its eligibility crite-
ria, submission procedure, submis-
sion deadline, and awards, refer to
novel ideas with experimental results
demonstrating a high performance.
The length of the papers, including fig-
ures, tables, and references, is limited
to four journal pages. The editor-in-
chief is Behzad Razavi of University of
California, Los Angeles.
The review process for papers
submitted to the publication upholds
similar standards to IEEE Journal of
Solid-State Circuits, with the excep-
tion of a shorter turnaround time.
IEEE SOLID-STATE CIRCUITS MAGAZINE
other. People from different stages of
their career were seated at each table.
Attendees swapped advice and stories
on topics such as work/life balance,
gender bias in the workplace, and mov-
ing forward in their careers.
—Abira Sengupta
https://sscs.ieee.org/education/2017-
2018-circuit-analysis-design-contest.
The submission deadline is 15 January
2018, 5 p.m. EST.
Each paper is reviewed by two peers
from an Editorial Review Board, which
consists of individuals who are com-
mitted to a fast turnaround, and a
third independent reviewer.
For more information, visit the
IEEE SSC-L website: http://sscs.ieee
.org/publications/ieee-solid-state-
circuits-letters-ssc-l.
—Behzad Razavi

fa l l 2 0 17 135
 con ference reports

2017 Symposium on VLSI Circuits

Harmonious Integration Toward Next Dimensions

T
To continue the exponential growth
that has propelled the semiconductor
industry for decades, parti­­cularly RBL BL BLB RBLB
in the face of decelerating technol- RWL WWL WWL RWL
ogy scaling, the very-large-scale-
integration (VLSI) community needs
to identify additional dimensions
for innovation. This effort was front
and center at the 2017 Symposia on
VLSI Technology and Circuits held in
Kyoto, Japan, 5–8 June 2017, the semi-
conductor industry’s premier event on Bit Cells
advances in microelectronics tech-
nology and circuits. In particular, RBL RBLB BL BLB
harmonious integration of the two
communities was a focus as the two
symposia fully overlapped for the S.A. S.A.
Write
first time. The four-day event included QB Q QB Q Buffer
joint circuits and technology focus
sessions and joint evening panels in
addition to overlapped short courses
and a new joint demo session. XOR/
OR NOT AND One-Column
Operation
Circuits for the Internet of Things
For years, the anticipated ubiquitous
ReadOut Data
deployment of connected devices,
or the Internet of Things (IoT), has Shifter
been a significant focus for many (Wiring Based)
circuit designers, and that trend
continued at this year’s symposium.
One of the circuits plenary sessions, Shift
WData

“Innovative Solutions Toward Future

Mux 64-Bit ROT
Society with AI, Robotics, and IoT”
5 to 1 Rotator
by Takeshi Yukitake of Panasonic DIN D Q
Corp., discussed the technologies be­­
hind a safe and securely networked SBOX
society. The benefit of edge devices Mux SBOX
processing data in physical space, as 16 to 1
Writ FF
opposed to the cloud, was ­illustrated

Digital Object Identifier 10.1109/MSSC.2017.2746197

Date of publication: 16 November 2017 Figure 1: A crypto-SRAM bank from the University of Michigan’s Recryptor processor.

136 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

 ­ OSRAM, a 100-MHz normally off CPU
D The second plenary s ­ ession, “In­­
was successfully demonstrated with dra- side Waymo’s Self-Driving Car: My
matically reduced power consumption, Favorite Transistors,” was delivered
94% for CPU core and 70% for memory. by Dr. Daniel Rosenband of Waymo. He
highlighted the diverse set of technolo-
Toward Autonomous Driving gies needed to enable automated driv-
Advanced drive assistance function ing functions and explained that many
systems in today’s cars will become of these technologies are built upon
partially automated systems within advanced semiconductor designs.
several years, and it is only a matter of For example, direct time-of-flight lidar
time before vehicles are fully autono- systems rely on high-speed compara-
mous. These trends are evident in the tors to accurately capture the timing of
rapid de­­­velopment of lidar, radar, and echo signals, which are then trans-
by a functionally distributed facial vision-sensing systems, which were lated into range information for a
recognition s y ste m that reduced also on display at the 2017 Cir- three-dimensional (3-D) image. Simi-
data rates by five times. cuits Symposium. larly, vision systems for self-driving
One of the many contributions
presented to the symposia from the Uni-
versity of Michigan was the Recryptor, a
compact advanced RISC-machine-M0-
based reconfigurable cryptographic
processor for IoT. This processor is ca-
pable of performing various cypher al-
gorithms with state-of-the-art efficiency
due to a programmable in-memory cal-
culation block that accelerates wide bit
width arithmetic operations (Fig­ure 1). In
40-nm complementary-metal-oxide
semiconductors (CMOS), the resulting
performance was seven times faster
Daniel Rosenband of Waymo, delivering one of two Circuits plenary ­sessions.
and had 13 times lower energy than
previous accelerated implementations.
During one of the joint Technol-
ogy–Circuits focus sessions, “Ultra-Low
SPAD and Front-End Circuit Block From Address Decoder
Power for the IoT,” researchers from
United Microelectronics Corp. dem- V_SPAD (+25.5 V) Data Line
onstrated the world’s first 100-MHz Quenching To
dynamic oxide semiconductor RAM Resistor Bias Correlation Detector
(300 kΩ)
(DOSRAM) using a new high-mobility
InGaZnO material. The un­­d erlying
technology advance, as shown in Fig- SPAD ac Couple
(5fF)
ure 2, is a nearly two-times increase
in the mobility of the indium gallium
zinc oxide (IGZO) channel. Using this Pull-Up
Address Decoder Resistor for PLL
Open Drain
Clock (600 MHz, 8 Phase)
Valid Timing
TDC
Hall Mobility (cm2/Vs)

35
30
Peak Count Control
25 New IGZO Macro Pixel Logic
20 (2 × 4 SPAD) Correlation
15 Detector
Conventional and
10 Data Address
IGZO 32 × 4 Peak Counter
5 Data Line Memory
10 10 10 10 10 1020 1021
15 16 17 18 19 Pixel Array
Carrier Concentration (/cm3) External
Read Out
Figure 2: A comparison of Hall mobility
between new and conventional IGZO. Figure 3: A block diagram of Denso’s 2-D SPAD array imager chip.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 137

cars use many high-resolution image
sensors, relying on circuit advances
to maximize throughput and decrease
power consumption. Of course, the
extensive data generated by the
mul­­titude of sensors require a very
powerful compute system. Graphics
processing units, field programmable
gate arrays, and custom application
specified integrated circuits are all
used, balancing tradeoffs in hard-
ware acceleration. The self-driving
car also has unique memory system
requirements, and very high-perfor-
mance DRAM is needed in terms of
bandwidth, but this must be balanced
with the need for low power and high
levels of integration.
The same topic was covered in one
of the Circuits short courses, “Inte-
grated Circuits for Smart Connected Cars
and Automated Driving,” which featured
seven distinguished presenters cover-
ing a wide range of topics. The ses-
sion began with an excellent overview
on automotive electronics, drawing
on the real-world experience of Bosch.
Technical talks on previously men-
tioned sensor modalities were included,
such as Prof. Kawahito from Shizuoka
Uni­­versity covering advances in image
sensors to deliver state-of-the-art
dynamic range and low-noise perfor­
20 µm∗
After Lithography
After Resist Strip
Figure 4: Micro-bumping images with pitches down to 40 μm*, from IBM Research’s neuromorphic computing paper.
138 fa l l 2 0 17
mance. Other types of sensors, including
inertial microelectromechanical sys-
tems (MEMS) and anisotropic mag-
net resistance angle sensors, were
covered as well. Connectivity was an
important topic, with Marvell covering
in-car networks to support high-speed
data interface and Intel discussing a
variety of topics that included 5G and
secure wireless platforms for interve-
hicle communication.
During one of the technical sessions,
Denso Corporation, in collaboration
with Toyota R&D, presented a single
photon avalanche detector (SPAD)
array chip targeted for automotive
lidar in Figure 3. The paper described
the world’s first two-dimensional pixel
array with a SPAD macro pixel archi-
tecture directly outputting digital
data. Time-domain statistical process-
ing is used to improve the accuracy of
time-of-flight distance measurement. The
chip is built into an imaging system
with a laser and scanning MEMS mir-
ror, and this system is capable of imag-
ing targets at ranges up to 20 m, even in
full 75-klux ambient light.
Deep Learning in Circuits
Machine learning is one of the highly
anticipated enabling technologies for
self-driving cars. In the automotive
After Lithography After IMS
IMS Strip
30 µm∗ 40 µm∗
IEEE SOLID-STATE CIRCUITS MAGAZINE
application and others, learning in cir-
cuits was another focus area for the
symposium, beginning with a short
course, “Machine Learning for Circuit
Designers.” The short course covered
the basics of machine learning as well
as state-of-the-art implementation
techniques from a range of associ­­
a­­
ted applications. For example, Prof.
Verma of Princeton University described
energy-efficient mixed-signal systems
for machine-learning algorithms. In
addition, a talk from Fujitsu focused on
large-scale neural networks utilized in
the cloud, and Qualcomm reviewed
machine-learning architectures for
mobile devices. Topics were selected to
be of interest to the circuit-level engi-
neer, including parallelization, accelera-
tors, the importance of data movement,
and memory ­management.
Advanced computing architectures,
including those specific to neuromor-
phic devices, were covered in another
joint focus session. Investigators from
IBM Research in Japan discussed neu-
romorphic device architectures with
support for new computing systems
that can learn from unstructured data.
Both static random-access memory
(SRAM) based spiking neural networks
and cross-bar structures were explored
as well as advances in solder bumping
After Stripping
50 µm∗
SAC305
Cu Pilar
50 µm
 B M Synapse Synapse H Synapse H–1 Synapse 1 Upper
B M W B M W B M W Column
0 0 A1 FFs
W×A
Addend (3H Bits)
0 1 Dec.
No Conn.

log2(2L+1)+1
+ + +
1 0
W × A –1
Sign Sign Sign
1 1
W × A +1 OPNE
A2 Act. FFs
B M W
A IPNE Sign
W×A A3
Adder Tree
Bit Exp./ Addend Lower-
Select Dec.
Column
B M W B M W B M W FFs
–2, –1, 0, 1, or 2 (3H Bits)
Synapse H Synapse H–1 Synapse 1
(Real Integer)
(a) (b)

Figure 5: An extension of output and input parallel neural engines for ternarization and biasing: (a) mask (M) and bias (B) bits and addend
decode and (b) output/input parallel neural engines.

and 3-D integration technologies, sev-
eral of which are illustrated in Figure 4.
Several hardware accelerators for
deep neural networks (DNNs) were pre-
sented in a Circuits session ­dedicated
to machine and deep learning. One
of those papers, from Hokkaido Uni-
versity, focused on spatially mapping
binary and ternary DNNs into silicon. It
featured a binary DNN inference accel-
erator with an array of tightly coupled
SRAM-logic modules. The base archi-
tecture was extended by introducing
mask and bias bits, as shown in Fig­­
ure 5. This versatile implementation
accelerated fully connected, densely
connected, and sparsely connected
DNNs with varying widths and depths.
While fair comparisons between this
work and convolutional neural net-
work ac­­­celerators are difficult, the TOPS
of this work outperforms by more than
ten times.
The symposia featured a demo session
for the first time. Conference attend-
ees enjoyed 18 table-top real-time
presentations and the opportunity for
in-depth interaction with authors of out-
standing papers from both the Tech-
nology and Circuits sessions.
The day after the technical sessions
concluded, the International Forum
on Singularity: Exponential X was held,
cosponsored with the Japan Society for
the Promotion of Science. The focus was
the exchange of insight on future impli-
cations of the exponential nature to
Moore’s law, even if that growth might
not be linked to silicon in the future.
The forum included key thought lead-
ers from a wide field including Intel,
the University of California, Berkeley,
Rakuten, Yahoo Japan, KAIST, and many
others. The forum will be held again
after next year’s symposia.
Social Events
One of the social highlights of the
conference was the joint banquet. Cir-
cuits and Technology attendees came
together for food and drink and enjoyed
some traditional Japanese Nihon Buyo
dance entertainment.
In addition to the banquet and demo
sessions, there were several other social

Full Symposia Overlap

The full four-day overlap of the Sym-
posia on Technology and Circuits
resulted in many ­ opportunities for
attendees on both sides to connect and
share with each other. In addition to the
two previously mentioned joint focus
sessions, there were also sessions cov-
ering emerging reliability solutions
and advanced assembly techniques. Conference participants talking to authors at the new demo session.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 139

 a very entertaining discussion on the
most important circuits of 2037.
Also, the IEEE Solid-State Circuits Soci-
ety (SSCS) Women in Circuits group
held a networking lunch event, simi-
lar to those held at other IEEE events.
Finally, the SSCS and IEEE Electron
Devices Society held a networking event
for young p­ rofessionals.
To continue the exchanges and net-
working, conference participants
and others interested in VLSI technol-
ogy and circuit design are encouraged
to join the LinkedIn group, Symposia
on VLSI Circuits and Technology, to
participate in discussions about con-
ference topics: http://www.linkedin
.com/grp/home?gid=3037968.
The opening of the Exponential X Forum following the technical program.
Looking Forward
The annual Symposia on VLSI Tech-
nology and Circuits are regarded
as the premier midyear gatherings
for the advancement of microelectron-
ics technology and circuits —with
approximately 1,000 experts in both
fields attending and around 200 papers
being presented each year. The
VLSI Technology Symposium began
in 1981, while the VLSI Circuits Sym-
posium was added in 1987. The two
meetings have been held together
ever since, rotating annually between
Japan and Hawaii. In 2018, the sym-
A traditional Japanese dance during the joint banquet. posia will be held at the Hilton Hawai-
ian Village, Honolulu, Hawaii, United
States, 18–22 June. For further Infor-
mation, please visit www.vlsisympo
sium.org.
The Symposium on VLSI Circuits
is sponsored by the IEEE SSCS and
the Japan Society of Applied Phys-
ics, in cooperation with the Insti-
tute of Electronics, Information and
Communication Engineers and the
IEEE Electron Devices Society. The
Symposium on VLSI Technolog y
is sponsored by the IEEE Electron
Devices Society and the Japan Soci-
The most prolific authors in symposium history were recognized at the 30th ­anniversary ety of Applied Physics, in coopera-
celebration. tion with SSCS.

gatherings. The Circuits Symposium most prolific authors and most cited
celebrated its 30th anniversary with an papers. This ­celebration was followed —Ron Kapusta
evening session that recognized its by three evening panels, including VLSI Symposium Publicity Chair

140 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE

13th PRIME 2017 Conference Cosponsored by SSCS

T
The Conference on Ph.D. Research
in Microelectronics and Electronics
(PRIME) has established an important
forum where Ph.D. students and post-
docs can present their re­­search results
a nd net work w it h e x p e r t s f r o m
industry, academia, and research.
The 13th edition of PRIME was held
12–15 June 2017 in Giardini Naxos—
Taormina, Italy, and was technically
sponsored by the IEEE Solid-State Cir-
cuits Society (SSCS) Italian Chapter
and the IEEE Circuits and Systems
­S ociety (CASS).
PRIME 2017 was organized by
the University of Catania, Italy, with
General Chair Prof. Salvatore Pennisi
and General Cochair Prof. Gaetano
Palumbo. The city of Catania, home
to many semiconductor foundries Prof. Salvatore Pennisi, PRIME 2017 general chair.
located in the industrial area (such
as STMicroelectronics, Micron Semi-
conductor, Texas Instruments, and
Maxim Integrated), and its univer-
sity, the oldest in Sicily (founded in
1434), are considerably involved in
microelectronics. Giardini Naxos is
a vibrant beach resort center very
close to the world-renowned town of
Taormina (host of the G7 summit a
few days earlier) and is surrounded
by the UNESCO and natural site of

Digital Object Identifier 10.1109/MSSC.2017.2746198 The audience of Prime 2017, with special guest Dr. Carmelo Papa, chief executive officer of
Date of publication: 16 November 2017 STMicroelectronics, Italy.

A few of the Prime 2017 attendees.

IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 141

Attendees enjoying the dessert buffet at the conclusion of the gala dinner.
The company fair. The gold sponsors were Dialog Semiconductor, Micron Semiconductor, and STMicroelectronics.
The registration desk.
Mount Etna, the highest active volcano
in Europe.
PRIME was an unprecedented suc-
cess with more than 200 delegates
and 96 presented works from a total
of 136 manuscript submissions.
The conference was honored by the
presence of Prof. Franco Maloberti,
IEEE CASS president, and Prof. Andrea
Baschirotto, chair of the IEEE SSCS
Italian Chapter.
142 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE
PRIME 2017 offered a multitude of
opportunities for the attendees to
gain knowledge about relevant topics
in micro/nanoelectronics. The techni-
cal program included a preconference
workshop and a tutorial presented
by CADENCE Academic Network and
STMicroelectronics. Three keynote
speeches were given, one per day:
“System in Package Products and
Trends” (by Francesco Pulvirenti,
ST­­Microelectronics), “System in Package
Design Challenge” (by Roberto G. Mas-
solini, Texas Instruments), and “3D
NAND Memories Technology Trends”
(by Tommaso Vali, Micron Semicon-
ductor). There were also three days
of technical sessions with three oral
sessions in parallel.
As per tradition, a company fair
was promoted by PRIME where the
at­­tendees had the opportunity to
meet industrial exhibitors, such as
Dialog Semiconductor, Micron Semicon-
ductor, STMicroelectronics, CADENCE
Academic Network, Coilcraft, InvenSense,
ON Semiconductor, Texas Instruments,
and Maxim Integrated.
PRIME 2017 was colocated with
the 14th International Conference
on Synthesis, Modeling, Analysis and
Simulation Methods and Applica-
tions to Circuit Design. Additional
information and photos from PRIME
2017 can be found on its website,
http://prime2017.unisa.it.
—Salvatore Pennisi
ISSCC 2018—”Silicon Engineering a Social World”
C
Continued advances in solid-state
circuits and systems have brought
evermore powerful communication
and computational capabilities into
mobile form factors. Such ubiquitous
smart devices lie at the heart of a revo-
lution shaping how we connect, col-
laborate, build relationships, and
share information. These social tech-
nologies allow people to maintain con-
nections and support networks that
otherwise would not be possible; they
provide the ability to access informa-
tion instantaneously and from any
location, thereby helping to shape the
world’s events and culture, empower-
ing citizens of all nations, providing
social networks, and allowing world-
wide communities to develop and
bond with common interests.
The 2018 International Solid-State
Circuits Conference (ISSCC 2018) will
showcase numerous innovations that
will fuel further progress toward a
truly connected social world. ISSCC
2018 will be held at the San Francisco
Marriott Marquis from 11 to 15 Febru-
ary 2018.
The plenary session on Monday,
11 February, will feature four distin-
guished invited speakers:
■■ Vince Roche, president, chief ex-
ecutive officer, Analog Devices,
United States, will present “Semi-
conductor Innovation: Is the Party
Over or Just Getting Started?” and
explore the next paradigm for
semiconductor innovation and
what our path forward as scien-
tists, technologists, and industry
overall will be.
■■ Barbara De Salvo, chief scientist and
scientific director, CEA-Leti, France,
will give her insights in her talk,
“Brain-Inspired Technologies: To-
wards Chips That Think,” and will
illustrate a research strategy en-
compassing algorithms, circuits,
and components, all in support of
Digital Object Identifier 10.1109/MSSC.2017.2746199
Date of publication: 16 November 2017
■■ David Patterson, professor of the
The 2018 International graduate school at the University of
Solid-State Circuits California, Berkeley, will discuss “50
Conference (ISSCC 2018) Years of Computer Architecture:
will showcase numerous From Mainframe CPUs to Neural-
innovations that will Network TPUs,” reviewing a half-
fuel further progress century of computer architecture,
toward a truly from the IBM System 360 to modern
connected social world. domain-specific computer archi-
tectures such as Google’s Tensor
Processing Unit.
ISSCC 2018 will feature educational
brain-inspired technologies to meet events such as tutorials for those who
the needs of 21st century applications. wish to learn the basics of circuit top-
■■ Yukihiro Kato, senior executive di- ics and forums for experts who want
rector, Denso, Japan, will give the to be in touch with the latest trends.
talk “Future Mobility Society En- This year, the conference will feature
abled by Semiconductor Technol- ten 90-min tutorials on Sunday, 11
ogy” and discuss how the automo- February (see Table 1 for details).
tive industry is in the midst of a Of the six all-day forums, two will
once-in-a-century transformation be on Sunday, 11 February, and four
caused by electrification, automat- on Thursday, 15 February (see Table 2
ed driving, and connected vehicles. for details).
TABLE 1. TUTORIALS—Sunday, 11 February.
• Low-Jitter PLLs for Wireless Transceivers
Xiang Gao, Credo Semiconductor, Milpitas, California, United States
• Nonvolatile Circuits for Memory, Logic, and Artificial Intelligence
Meng-Fan Chang, National Tsing Hua University, Hsinchu, Taiwan
• Basics of Quantum Computing
Edoardo Charbon, EPFL, Switzerland
• Error-Correcting Codes in 5G/NVM Applications
Hsie-Chia Chang, National Chiao Tung University, Hsinchu, Taiwan
• Hybrid Design of Analog-to-Digital Converters
Seng-Pan (Ben) U, University of Macau, Macau
• Single-Photon Detection in CMOS
Matteo Perenzoni, FBK, Trento, Italy
• Basics of Adaptive and Resilient Circuits
Keith Bowman, Qualcomm, Raleigh, North Carolina, United States
• Fundamentals of Switched-Mode Power Converter Design
Hoi Lee, The University of Texas at Dallas, United States
• Digital RF Transmitters
Renaldi Winoto, Tectus, Saratoga, California, United States
• ADC-Based Serial Links: Design and Analysis
Samuel Palermo, Texas A&M University, United States
IEEE SOLID-STATE CIRCUITS MAGAZINE fa l l 2 0 17 143
 TABLE 2. FORUMS. on Monday evening, 12 February,
where companies will provide short
Sunday, 11 February “pitches” on their technology/product
• Intelligent Energy-Efficient Systems at the Edge of IoT innovation, followed by an interactive
FINFETs
•  and FDSOI—A Mixed-Signal Circuit Designer’s Perspective session with attendees at company
booths and tables.
Thursday, 15 February The conference will also continue
• Circuits and Architectures for Wireless Sensing, Radar, and Imaging the popular tradition of evening
• Circuit and System Techniques for mm-Wave Multi-Antenna Systems panels on Monday, 12 February,
and Tuesday, 13 February, where
• Advanced Optical Communication: From Devices, Circuits, and Architectures to Algorithms
experts, often of opposing views,
• Advances in Energy-Efficient Analog Design discuss topics that range from the
lighthearted to the controversial (but
always informative and entertain-
ing!). This year’s panels are “Figures-
TABLE 3. SHORT COURSE.
of-Merit on Trial,” “Lessons Learned
Hardware Approaches to Machine Learning and Inference —Great Circuits That Didn’t Work
• Introduction to Machine Learning and Inference (Oops, If Only I Had Known!),” and
Gu-Yeon Wei, Harvard University, Cambridge, Massachusetts, United States “Can Artificial Intelligence Replace
My Job?—The Dawn of a New IC
• Algorithm and Implementation Co-Design for Learning and Inference
Industry with AI.”
Marian Verhelst, KU Leuven, Leuven, Belgium
Overall, the conference will pro-
• Efficient Edge Solutions for Deep Learning Applications vide a variety of opportunities for
Vivienne Sze, Massachusetts Institute of Technology, Cambridge, Massachusetts, United States attendees to interact one on one with
• Efficient Alternatives and Extensions to Deep-learning-based Solutions authors during interviews at the end
Naveen Verma, Princeton University, New Jersey, United States of the day that their presentation is
given as well as during breakout
sessions and evening social hours.
During the evening social hours,
An in-depth all-day short course, showcase both academic- and industry- ISSCC features alumni gatherings
“Hardware Approaches to Machine led submissions, in the early evenings of particular universities as well as
Learning and Inference,” will be held of 12–13 February. book displays by various publishers
on Thursday, 15 February. This course A continuing initiative for students highlighting the latest and classical
be presented by renowned academic is the Student Research Preview, to be technical books.
researchers (see Table 3 for details). held on the evening of Sunday, 11 Feb- Correspondingly, ISSCC continues
The core of the conference will in- ruary, and consisting of short presenta- to be the premier conference of the
clude more than 25 technical sessions tions introducing an all-evening poster IEEE Solid-State Circuits Society (SSCS).
covering the latest developments in session. The same evening there will IEEE Members who are a lso SSCS
the design of circuits and systems also be a workshop on circuits for social members will receive a US$40 credit
involving silicon or other nanotech- good, which will highlight ­various ways toward conference fees applied at the
nologies in the areas of analog; data that circuits can help address some of time of registration.
converters; digital architectures the most important challenges fac- We look forward to seeing you at
and systems; digital circuits; imag- ing society today, ranging from health ISSCC 2018! For more information visit
ers, sensors, microelectromechanical care to energy conservation. The work­­ isscc.org.
systems, medical devices and dis- shop includes speakers from indus- —Denis Daly
plays; memory; power management; try, academia, and ­startups as well as ISSCC Press Coordinator
RF circuits and wireless systems; tech- interactive roundtable discussions on
nology directions; and wireline. These topics such as machine learning, medical —Laura Fujino
sessions will be held 12–14 February. devices, next-­generation communica- ISSCC Director of Publications and
Selected papers presented in the tech- tions, and security. Presentations
nical sessions will be further expanded This year, for the first time, ISSCC
during the demonstration sessions that will hold an Industry Showcase event 

144 fa l l 2 0 17 IEEE SOLID-STATE CIRCUITS MAGAZINE


CEDA Currents
T
The following is reprinted from CEDA
Currents, September 2017 issue, a pub-
lication of the IEEE Council on Elec-
tronic Design Automation (CEDA).
Please send contributions to Jose L.
Ayala (jayala@fdi.ucm.es).
SMACD 2017 EDA Competition
The 2017 edition of the Interna-
tional Conference on Synthesis,
Modeling, Analysis and Simulation
Methods and Applications to Cir-
cuit Design (SMACD 2017) was held
in Giardini Naxos-Taormina, Italy,
12–15 June 2017, with the technical
sponsorships of IEEE, IEEE Circuits
and Systems Society (CASS) and IEEE
Council on Electronic Design Auto-
mation (CEDA).
Since several editions, SMACD
organizes an EDA students’ competi-
tion, where M.Sc. and Ph.D. students
can compete with their best ideas,
methodologies, flows, and tools
with one unique but challenging
goal: improving design automation
for integrated circuits and systems.
Every year the number of papers and
live demos proposed for the com-
petition is increasing as well as the
quality and the potentiality of the
proposed solutions. A US$1,000 prize
has been granted to the winner of the
competition. IEEE CEDA has also pro-
moted the event, funding US$500 of
the total prize.
The 2017 edition of the competi-
tion has been coorganized by Rafael
Castro-Lopez (CSIC and University
of Seville, Spain) and Ralf Sommer
(Ilmenau University of Technology,
Germany). In two dedicated sessions
of the conference, the best six pro-
posals and ideas were presented
Digital Object Identifier 10.1109/MSSC.2017.2746200
Date of publication: 16 November 2017
by the students. A committee of
experts from academia and industry
interacted with the students during
the sessions and selected the win-
ner of the competition based on the
quality of the paper, its presenta-
tion, and its live demo. The compe-
tition prize was granted to Axel Hald,
from Automotive Electronics Robert
Bosch GmbH, Germany. His paper,
titled “A New Method for the Analysis
of Movement Dependent Parasitics in
Full Custom Designed MEMS Sensor,”
(coauthors: J. Seelhorst, P. Herzo-
genrath, J. Scheible and J. Lienig)
was awarded during the SMACD 2017
gala dinner.
More details on the competition
are available at http://smacd2017
.unisa.it/?id=callcomp.
Recipient of the Accellera Systems
Initiative 2017 Leadership Award
Congratulations to Shishpal Rawat,
president of CEDA, as recipient of
Upcoming Conferences
(Yao-Wen Chang,
ywchang@ntu.edu.tw)
•• FMCAD
TU Wien, Vienna, Austria
October 2–6
•• ESWEEK
Seoul, Korea
October 15–20
•• NOCS
Seoul, Korea
October 19–20
IEEE SOLID-STATE CIRCUITS MAGAZINE
IEEE N E WS
the Accellera Systems Initiative
2017 Leadership Award. The award
recognizes the vision, leadership,
and contribution to standards develop-
ment, governance, and promotional
activities of an Accellera member
on behalf of the organization. The
award was presented to Shishpal at
the 54th Design Automation Confer-
ence (DAC) during the Accellera Break-
fast and Portable Stimulus Town Hall
on Tuesday, June 20.
“Shishpal has had a profound im-
pact on the advancement of Accellera’s
mission and its growth worldwide,”
stated Lu Dai, Accellera Systems
Initiative chair. “We are grateful for
his years of leadership and dedica-
tion. Among his many accomplish-
ments during his tenure as chair of the
Board of Accellera from 2010 to 2016,
15 members were added worldwide,
three standards were published, and
two of those standards were success-
fully delivered to the IEEE Standards
Association (SystemC AMS and UVM).
He is very deserving of this award, and
I am proud to honor him among his col-
leagues at DAC.”
“I am deeply honored by this rec-
ognition from Accellera,” stated Dr.
Shishpal Rawat. “With the help of key
leaders in Accellera, we were able to
expand the technical scope of Accel-
lera and also market its standards
across the globe at multiple DVCon
IEEE Embedded Systems Letters is open for
submissions. Visit mc. manuscriptcentral
.com/les-ieee.
IEEE Design & Test is open for submis-
sions. Visit mc.manuscriptcentral.com/
dandt and ieee-ceda.org/publications/
d-t/paper-submission.
FA L L 2 0 17 145

Find us online at http://ieee-ceda.org.
conferences. These standards con-
tinue to have a positive impact on
the productivity of chip design and
design tools. I look forward to con-
tinued collaboration with Accellera.”
Shishpal has more than 30 years of
experience in the ­electronics industry.
He held a variety of positions at Intel
Corporation prior to his retirement
last year, most recently as director of
external EDA strategy.
Shishpal became chair of Accellera
in June 2010. As chair of Accellera, he
2.0 and oversaw the move toward
standardization of the Universal Veri-
fication Methodology (UVM) standard
to IEEE 1800.2. The Verilog AMS stan-
dard also moved under the SystemVer-
ilog AMS standard. The deployment
of Accellera standards via the DVCon
brand of conferences expanded to
Europe and India, and the planning
and development for DVCon China was
initiated during his term of leadership.
Most recently, the emerging Portable
Stimulus standard made significant
strides since work began in 2015 while
Shishpal was chair of Accellera.
Papers in IEEE Embedded
Systems Letters
The top-five accessed articles from
IEEE Embedded Systems Letters in
June 2017 were as follows:
■■ “Testing Autonomous Vehicle Soft-
ware in the Virtual Prototyping
Environment,” by B. Kim et al.
IEEE COUNCIL ON ELECTRONIC
DESIGN AUTOMATION
President: Shishpal Rawat
President-Elect: David Atienza
Past President: Sani Nassif
Secretary: Eli Bozorgzadeh
VP Conferences: Yao-Wen Chang
VP Finance: Gi-Joon Nam
VP Publications: Helmut Graeb
VP Publicity: Jose Ayala
VP Activities: Peng Li
Strategy Chair: David Atienza
Awards Chair: Hidetoshi Onodera
ble Dev ices,” by K. Ozcan and
S. Velipasalar.
Papers in IEEE Design and Test
The top-five accessed articles from
IEEE Design and Test in June 2017
were as follows:
■■ “Recent Technology Advances of

oversaw the consolidation of stan- ■ ■ “Energy Efficient Outdoor Light Emerging Memories,” by Y. Chen et al.
dards bodies, namely the merger Monitoring and Control Architec- ■■ “Security and Privacy in Cyber-Phys-

with OSCI, as well as the acquisition ture Using Embedded System,” by ical Systems: A Survey of Surveys,”
of the OCP standard. He also helped Z. Kaleem, T.M. Yoon, and C. Lee by J. Giraldo et al.
to extend the relationship with the ■■ “Public Key Authentication and Key ■■ “Computing in the Dark Silicon

IEEE Standards Association’s IEEE Get Agreement in IoT Devices With Era: Current Trends and Research
Program for an additional ten years, Minimal Airtime Consumption,” by S. Challenges,” by M. Shafique et al.
ensuring continued public access Sciancalepore et al. ■■ “Post-Silicon Validation in the SoC

to view and download current EDA ■■ “Arduino Debugger,” by J. Dolinay Era: A Tutorial Introduction,” by P.
standards at no charge, courtesy of et al. Mishra et al.
Accellera. He managed the relicensing ■■ “Wearable Camera- and Accelerome- ■■ “Approximate Computing: A Sur-

of SystemC contributions to Apache ter-Based Fall Detection on Porta- vey,” by Qiang Xu et al.

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 Con ference Calen dar

2018 IEEE Symposium on VLSI Circuits
SSCS-SPONSORED http://www.vlsisymposium.org/
CONFERENCES 18–22 June
Honolulu, Hawaii, United States
Paper due date: 29 January 2018
2018
2018 IEEE International Solid-State Circuits
Conference (ISSCC)
http://isscc.org/ SSCS Technically
11–15 February CoSponsored Conferences
San Francisco, California, United
States
Paper due date: passed 2018
2018 IEEE Custom Integrated Circuits 2018 International Symposium on VLSI
Conference (CICC) Design, Automation, and Test (VLSI-DAT)
http://ieee-ciccc.org http://expo.itri.org.tw/2018vlsidat
8–11 April 16–19 April
San Diego, California, Hsinchu, Tawain
United States Paper due date: passed
Paper due date: passed
2018 IEEE Radio Frequency Integrated
Circuits Symposium (RFIC)
http://rfic-ieee.org
10–12 June
Philadelphia, Pennsylvania,
Digital Object Identifier 10.1109/MSSC.2017.2746218 United States
Date of publication: 16 November 2017 Paper due date: 12 January 2018
2018 IEEE Symposium on VLSI Technology
http://vlsisymposium.org/
18–22 June
Honolulu, Hawaii, United States
Paper due date: 29 January 2018
2018 IEEE BiCMOS and Compound
Semiconductor Integrated Circuits and
Technology Symposium (BCICTS)
14–17 October
San Diego, California, United States
Paper due date: 11 May 2018
2018 IEEE Biomedical Circuits and Systems
Conference (BioCAS)
http://bioscas2018.org
17–19 October
Cleveland, Ohio, United States
Paper due date: TBD
For more information on upcoming
conferences, please visit: http://
sscs.ieee.org/conferences.


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