Synopsys and Arm Collaboration

Faster Bring-Up of Next-Generation Designs

Thomas Li
VP, Applications Engineering, Synopsys
November 2023
Synopsys & Arm Enabling Mutual Customer Success
Collaborating for more than 3 decades

1997 Today
Reference Methodologies Full Span Collaborations

Optimized Hardware Design

Implementation and Verification

synopsys.com/arm
Arm7™ & Arm9™
Software
1stSynthesizable Cores, System Compliance
Development and
Reference Methodologies and Validation
HW/SW Integration

Continued collaboration across design phases to deliver solutions for Arm-based SoCs

© 2023 Synopsys, Inc. 2

 Silicon IP
IP supporting Arm AMBA interconnects:
Interface IP, Logic Libraries, Embedded
Optimized Implementation Memories, NVM, AMBA Bus Fabric and High Performance Verification
Synopsys Design Tools, Peripherals, coreAssembler tool VCS ® RTL Verification & Verdi ® Debug,
QuickStart Implementation Kits (QIKs) VC Formal™, VC SpyGlass™ RTL
High Performance Core Centers, Signoff, VIP for AMBA Interconnect,
Low Power Methodology, VC LP™ & Verification Methodology,
Synopsys.ai – Full Stack EDA Suite ZeBu ® HW-Assisted Verification
Optimized Hardware Design
Implementation and Verification

synopsys.com/arm Hybrid Emulation

AMBA Transactors
Software
System Compliance
Development and
and Validation
HW/SW Integration

FPGA Prototypes Virtual Prototypes

HAPS ® Support for Arm Cores, Virtualizer™ Development
Connection to Juno Arm Development Hybrid Prototypes Kits (VDKs) for Pre-RTL SW Dev.
Platform, Prototyping Methodology AMBA Transactors Using Arm Fast Models,
Arch. Design with Platform Architect,
Coverity and Defensics SW Signoff
© 2023 Synopsys, Inc. 3
 Silicon IP
IP supporting Arm AMBA interconnects:
Interface IP, Logic Libraries, Embedded
Optimized Implementation Memories, NVM, AMBA Bus Fabric and High Performance Verification
Synopsys Design Tools, Peripherals, coreAssembler tool VCS ® RTL Verification & Verdi ® Debug,
QuickStart Implementation Kits (QIKs) VC Formal™, VC SpyGlass™ RTL
High Performance Core Centers, Signoff, VIP for AMBA Interconnect,
Low Power Methodology, VC LP™ & Verification Methodology,
Synopsys.ai – Full Stack EDA Suite ZeBu ® HW-Assisted Verification
Optimized Hardware Design
Implementation and Verification

synopsys.com/arm Hybrid Emulation

AMBA Transactors
Software
System Compliance
Development and
and Validation
HW/SW Integration

FPGA Prototypes Virtual Prototypes

HAPS ® Support for Arm Cores, Virtualizer™ Development
Connection to Juno Arm Development Hybrid Prototypes Kits (VDKs) for Pre-RTL SW Dev.
Platform, Prototyping Methodology AMBA Transactors Using Arm Fast Models,
Arch. Design with Platform Architect,
Coverity and Defensics SW Signoff
© 2023 Synopsys, Inc. 4
Synopsys.ai™: Industry’s First Full-Stack, AI-Driven EDA Suite
For design, verification, testing & manufacturing of digital and analog chips

Achieve power, performance and

Design Space
area (PPA) targets, and boost
Optimization productivity with DSO.ai

Verification Faster functional testing closure,

Space higher coverage and predictive
Optimization bug detection with VSO.ai

Automated test generation

Test Space
resulting in fewer, optimized
Optimization test patterns with TSO.ai

Rapid migration of analog

Analog and
designs and development
Manufacturing of lithography models

© 2023 Synopsys, Inc. 5

Synopsys Digital Design

SYNOPSYS DIGITAL DESIGN FAMILY • #1 Anchors: synthesis, P&R, signoff

SYSTEM DESIGN Fusion
• Fusion of algorithms, engines, data model
3DIC Compiler Architecture • Two fusion types: test and signoff
DIGITAL DESIGN

RTL Architect
• Industry-unique Fusion Compiler
Test Fusion Innovative
• Design Compiler NXT, TestMAX, IC Validator
Design Compiler NXT Products • PrimeShield, PrimeClosure, RTL Architect
TestMAX

Fusion Compiler
• ML-enhanced tools, AI-driven apps:
IC Compiler II
Market DSO.ai and TSO.ai
Leadership • Accelerating AI, automotive, and multi-die systems
Signoff Fusion
• Cloud-ready
PrimeTime, PrimeShield StarRC
PrimePower IC Validator
PrimeLib Formality / Formality ECO
PrimeClosure RedHawk Analysis Fusion

POST SILICON

Monitor IP Silicon.da

© 2023 Synopsys, Inc. 6

QuickStart Implementation Kits (QIK) for Advanced Arm® Cores
Synopsys reference flows and guides to meet PPA targets using Arm

Synopsys Fusion QIKs

The fast path to best Arm PPA Jointly Developed With Arm
Collaboration starts early, during RTL development

Delivers Native Out-of-the-Box PPA

Achieve PPA goals faster

Flexible and complete Includes Recommended Flow and Scripts

implementation and Core configuration and constraints, RTL-to-GDSII
static-verification flows implementation, test, ECO, signoff, formal verification

Easy to Customize
Core configuration, floorplan, technology library,
Available from Arm
PPA goals
or Synopsys

© 2023 Synopsys, Inc. 7

Arm + Synopsys: Arm + Synopsys: Collaborating for close to 3 decades to enable your success
Synopsys Fusion QIK – Accelerating Customer Success
Available for the most advanced Arm cores

EFFICIENT OOTB METHODOLOGY WW 1st tapeout of Hunter ELP

• Treats Arm® flows as a core product ‘feature’ • 9M inst. With H-tree structure
– Continually refreshed, maintained • In-design PP for dynamic power
• Broad availability • DSO.ai deployed for PPA push
– used internally in Synopsys for next-gen-core
4nm • Competitive win!
development
Fast, “What-if” Automated Native Data-flow Analysis
Exploration MIB Planning and Opt.

Interconnect Fast, Adaptive

3.1
Planning Abstraction

GHz+ Fmax
Signoff validated for production T/O
© 2023 Synopsys, Inc. 8
Fusion Success on Advanced Arm Cores Across Segments

Mobile CPU Design Automotive Infrastructure CPU

Hayes Cortex A78AE/DSU-AE Poseidon

Entire CPU sub-sys QIK
Exceptional PPA Gains Differentiated Fmax
Targeting FMax/Total Pwr
• Exceeded performance targets • Hierarchical flow with MSCTS and
• MBIST, LBIST and Scan
• Met aggressive power H-tree
• Automotive design spec.
requirements • Exceeded performance targets
• Dense PG networks
• MCMM for power and runtime • Met aggressive power requirements
• Extra derate for aging
balance
modeling
• 1.77Ghz Fmax

5nm 5nm 3nm

13% Better
Leakage Power 2.2 GHz+ Fmax
Achieved 95% Target Fmax within 3 weeks
3.55
Exceed Aggressive Target
GHz+ Fmax

© 2023 Synopsys, Inc. 9

Arm Core Customer Success with Synopsys DSO.ai
PPA and productivity improvements demonstrated on latest technology node

Automotive Automotive
7nm Cortex-A510 ANANKE A78-AE
Automotive Application CORE FC+DSO.ai
14LPC FC+DSO.ai 5nm

Competitive 2x 50% 9x 9x 7%
Win Faster Lesser Less Less Lower
TAT Compute TNS DRC Power

Automotive
A78-AE CPU AI
FC+DSO.ai
5LPE

200+
8% 5% Tape-outs
Better Better
Leakage Dynamic

© 2023 Synopsys, Inc. 10

Synopsys Solutions Enabling Better Optimizations, Earlier
Common engines with Fusion Compiler delivers fast, convergent QoR
”
FUSION COMPILER
News Release Unified RTL-to-GDSII optimization engines
Maximize
unlocks new opportunities for best
Arm Leverages Synopsys’ PPA Explosion of Fusion Platform usage inside Arm
performance, power, and area
…
Fusion Compiler to Enable Best PPA
”
for Latest Neoverse Platforms
MOUNTAIN VIEW, Calif., Apr 28, 2021 Single Shell
Single, integrated data model architecture
for unmatched capacity, scalability, and
BRENT MCKANNA
productivity
Our collaboration with Synopsys and the
deployment of Fusion Compiler delivers
”
SENIOR PRINCIPAL DESIGN ENGINEER, ARM

Built-in signoff timing, parasitic extraction,

accelerated access to this highly optimized Golden
and power
Impressive analysis
results fromeliminate design Being
RTL Architect...
technology, enabling our mutual customers to Signoff iterations
deployed on three projects, with the fourth
design and deploy market-shaping solutions
planned …
into the fast-expanding hyperscale space
JONATHAN TONG
JEFF KEHL DIRECTOR OF ENGINEERING, ARM
VICE PRESIDENT OF CPU ENGINEERING, ARM

© 2023 Synopsys, Inc. 11

Synopsys-Arm Success Stories on Wide Application Areas
Arm SNUG presentations
Multi-Die Design Electromigration Analysis

Silicon Lifecycle Management Functional Safety

© 2023 Synopsys, Inc. 12

 Silicon IP
IP supporting Arm AMBA interconnects:
Interface IP, Logic Libraries, Embedded
Optimized Implementation Memories, NVM, AMBA Bus Fabric and High Performance Verification
Synopsys Design Tools, Peripherals, coreAssembler tool VCS ® RTL Verification & Verdi ® Debug,
QuickStart Implementation Kits (QIKs) VC Formal™, VC SpyGlass™ RTL
High Performance Core Centers, Signoff, VIP for AMBA Interconnect,
Low Power Methodology, VC LP™ & Verification Methodology,
Synopsys.ai – Full Stack EDA Suite ZeBu ® HW-Assisted Verification
Optimized Hardware Design
Implementation and Verification

synopsys.com/arm Hybrid Emulation

AMBA Transactors
Software
System Compliance
Development and
and Validation
HW/SW Integration

FPGA Prototypes Virtual Prototypes

®
HAPS Support for Arm Cores, Virtualizer™ Development
Connection to Juno Arm Development Hybrid Prototypes Kits (VDKs) for Pre-RTL SW Dev.
Platform, Prototyping Methodology AMBA Transactors Using Arm Fast Models,
Arch. Design with Platform Architect,
Coverity and Defensics SW Signoff

© 2023 Synopsys, Inc. 13

Early RTL Verification for Arm IPs to SoCs
Close collaboration to bring Industry First Verification IPs for Arm Interfaces

+ Early Access to Arm IPs and Specifications

Synopsys AMBA VIP gets early access to Arm specifications (CHI
Issue F/G, CMN-700/800, IPs (CCI, CCN, CMN, Cortex) and Tools
(AMBA Designer, Arm Socrates)

Co-validated with Arm IPs

Ability to generate and regress against variety of Interconnect
configurations in-house (CCI-400, CCI-550, NIC-400/450, CMN-
600/700, etc)

Close Technical Collaboration

Dedicated channel for technical support and direct access to
Synopsys Protocol Verification Solutions architects and key leads

Verification IP Test Suite Transactors

System Verification Solutions Virtual/Hybrid
Software Development and System Validation
Protocol Verification Solutions for all Use-cases
IP to SoC Level RTL Verification Solutions with Arm Reference setups
Software development, System Verification/Validation and Compliance
solutions for Arm SoCs

© 2023 Synopsys, Inc. 14

 Early Modeling and Rapid Software Development
Architectural Exploration, Emulation, Software Development and System Validation

Architecture Exploration HW-Assisted Verification SW Dev. & System Validation

HAPS

ZeBu

• Early, model-based architectural
exploration of multi-die systems
• Dynamic analysis of latency and
bandwidth
• Optimized connectivity & interconnects
• Fast hardware and software verification
• Early software bring-up, hybrid,
hardware/software debug
• Simulation acceleration, performance
validation, Architectural compliance
and in-circuit emulation
• Multiple, high-performance engines
with protocol connectivity
• Early chiplet virtual models for SW
teams
• Models, transactors, speed adaptors,
prototyping kits

© 2023 Synopsys, Inc. 15

Synopsys Verification Solution for Arm BSA
Compliance Testing and Performance Analysis Arm BSA Compliance
Test Suites (ACS)
User Test and Performance
Parameters
Synopsys Platform Abstraction Layer (PAL)
SoC Boot Code / UEFI / BareMetal
• Developed using Arm reference designs and elemental kits
BSA PCIe EP Models and Infrastructure

• Includes compliance Arm ACS test suites, C-models for system

2:00.1

Bridge, NVMe and DMA, NIC, Tx/Rx Ring Root

1:00.0 2:00
Fct

2:00.0

Bridge Device Fct

Basic MMIO PCIe Buffers and Queues Port

2:01 2:01.0

Device Fct

components, and performance validation capabilities EP Device

MSI/MSI-X Error
2:02

Bridge
3:00

Device
3:00.0

Fct

3:00.1

C-Models Fct

Injection Delay Injection 3:00.2

Fct

• Measures key performance metrics (Channel throughput, Models Tester Functions User Topology

RD/WR/Interrupt latency, Bandwidth utilization etc) AXI4 VIP/ PCIe VIP/

Clock and Transactor Transactor
reset ctrl
• Built to natively support ZeBu® Emulation and VCS® simulation
Sideband interface

DMA PCIe RC sub

-
• ACS support over UEFI and Bare metal GIC system

ZeBu Emulation
System
CPU CPU GPUs SMMU control
• Early and low risk path to Arm SystemReady
Interconnect

DMC DMC Peripherals On-chip

controller controller memory
SoC

Memory Messaging
Memory Tube
SNPS
Arm
SiP
Performance Metrics © 2023BSA
Synopsys, Inc. 16
Reporting & Analysis Report
Optimization of Coherent Multi-Die Systems +
2023 webinar presented by Synopsys and Arm • A multi-die architecture based on
Arm’s coherent CMN-700
interconnect

• Analysis & optimization using

CMN-700 performance model

• In context of workload with HBM

and DDR models

• Root-cause analysis to debug

performance bugs

• Parameter sweeps and sensitivity

analysis to find optimal design
configuration

© 2023 Synopsys, Inc. 17

 +
Multi-Die System Performance Analysis
Analyze effective bandwidth and latency of coherent Arm CMN-700 multi-die interconnect

Multi-die HW platform
workload
AI
workload
CPU

© 2023 Synopsys, Inc. 18

Synopsys HAV Platforms Support High Value Use Cases
Solutions leverage Synopsys Verification Tools and Arm IP
+
Early RTL Compliance &
SW
Verification Certification
Synopsys Hardware-Assisted PHY IP Card
HW
Verification (HAV) Platforms
Verdi
ZeBu Server 5 HAPS-100
ZeBu Empower
RTL Performance/
Regression ZeBu EP1 Power Analysis

Platform Architect

SW/HW
SW Bring-up Validation Protocol Interface Card
Virtualizer
Speed Adaptor

Unified Core Technologies: Compile, Debug, Hybrid, Transactors

© 2023 Synopsys, Inc. 19
Hybrid Accelerates SoC Software Bring-Up
System boot execution accelerated from hours to minutes

Performance
• Fastest software bring up on emulation • Fastest Engines
• Transactors
• Fast Memory
• Checkpoint/Restore
• Earliest availability with largest model library Productivity
ZeBu Virtualizer
• Auto config
• Auto testbench

• Proven Virtualizer plug & play integration System Debug

• SW
• HW
• Protocols

• System-level debug across SoC SW and HW HAPS Virtualizer

Models
• Cortex A-, M-, R-

“The issue found running SoC software, investigated and narrowed down with ZeBu Hybrid and solved by the design team
was really a bug. This would have been a fatal one.” Leading 5G Networking Company

© 2023 Synopsys, Inc. 20

Accelerating Software-Defined Vehicle Validation
SYNOPSYS’ VIRTUAL-SOCS
INCLUDING Arm CORES
Automotive Electronics Digital Twins for
SW Development and System Testing Renesas R-CAR Gen3
& Gen4
NXP S32 Automotive
Virtual E/E Architecture Platform G/K/Z/E

Virtual ECU ST Stellar MCU

Virtual SoC Infineon TraveoTM T2G

Arm
NVIDIA DRIVE Orin

Qualcomm
SnapDragon 8xxx

+ Samsung KITT 1

© 2023 Synopsys, Inc. 21

 Silicon IP
IP supporting Arm AMBA interconnects:
Interface IP, Logic Libraries, Embedded
Optimized Implementation Memories, NVM, AMBA Bus Fabric and High Performance Verification
Synopsys Design Tools, Peripherals, coreAssembler tool VCS ® RTL Verification & Verdi ® Debug,
QuickStart Implementation Kits (QIKs) VC Formal™, VC SpyGlass™ RTL
High Performance Core Centers, Signoff, VIP for AMBA Interconnect,
Low Power Methodology, VC LP™ & Verification Methodology,
Synopsys.ai – Full Stack EDA Suite ZeBu ® HW-Assisted Verification
Optimized Hardware Design
Implementation and Verification

synopsys.com/arm Hybrid Emulation

AMBA Transactors
Software
System Compliance
Development and
and Validation
HW/SW Integration

FPGA Prototypes Virtual Prototypes

HAPS ® Support for Arm Cores, Virtualizer™ Development
Connection to Juno Arm Development Hybrid Prototypes Kits (VDKs) for Pre-RTL SW Dev.
Platform, Prototyping Methodology AMBA Transactors Using Arm Fast Models,
Arch. Design with Platform Architect,
Coverity and Defensics SW Signoff
© 2023 Synopsys, Inc. 22
Arm-Optimized Synopsys Interface IP
Arm/Synopsys Collaboration Delivers Proven Interoperability & Performance
Synopsys IP includes performance & Arm reference designs utilize Synopsys IP
latency features unique to Arm platforms • Arm completes interoperability
• Arm uses Synopsys IP for pre-silicon • Arm executes performance analysis
interoperability testing & performance analysis & • Results published in Arm analysis reports
in-silicon demo systems
• PCIe: Local Translation Interface (LTI) & MSI-GIC
• LTI lowers area and latency
• DDR5: Coherent Hub Interface (CHI), Memory SNPS

Partitioning and Management (MPAM) & End-to-

End QoS
• CXS: Credited eXtensible Stream; enabling CCIX
over CXL, Arm native interfaces for PCIe, XSR &
UCIe controllers SNPS

Example: Arm Neoverse N2 reference design

© 2023 Synopsys, Inc. 23
 Seamless Die-to-Die and Chiplet Solution for Arm
Synopsys Die-to-Die UCIe Solution with Native, Low Latency Arm Interface

Application Layer (Data Upper Link)

CHI/CXS RX CHI/CXS TX
• Low latency interface to Arm NoC
• Aligns to UCIe Specs – 1.0/1.1
TX Arm Native Bridge RX
Bridge

Link Init FLIT Protocol • Supports coherent & non-coherent traffic

Synopsys UCIe IP

Link Retry Handling ID

• Available across multiple vendors & nodes
FDI
• Synopsys 3DIC Compiler references
Controller

D2D Adapter in Streaming Mode

Link management, Parameter negotiation • Built-in lane signal integrity monitor for
CRC/Retry
Automotive and high reliability use-cases
RDI
D2D Physical Layer - UCIe
PHY

Link initialization, Training, Power states

Lane mapping and remapping, Scrambling, Lane reversal
Sideband Electrical / AFE

© 2023 Synopsys, Inc. 24

 Synopsys SLM Monitor, Test & Repair IP
High Speed Access and Test
• Enables testing through entire silicon life-cycle
• High-bandwidth testing reduces test time
• Reduced pin count & test hardware saves cost
UCIe Monitor, Test & Repair
• Health check of UCIe D2D interface
• Interface signal timing margin monitoring
• BIST & Repair of PHY in-test or in-field
XLBIST
• Enables non X-tolerant & X-tolerant logic
BIST
• Power-aware pattern generation supported
• MISR signature analyzer supported in
diagnosis for manufacturing mode
Star Memory System (SMS)
• Supports Synopsys and 3rd party SRAM/RF/ROM,
CAM, eMRAM and DRAM
• High Performance core support
• FinFET specific memory test algorithm
programmability – via JTAG and in-field (via APB)
Star Hierarchical System (SHS)
• Automated hierarchical test
• Automated test integration of all IP/cores with in-
system scheduling
• Pre-validated ready ATE patterns with pattern porting
PVT Monitors
• Maximizes performance, power,
reliability
• Highly accurate, distributed sensing
throughout the die
• Complete subsystem with s/w driver
Path Margin Monitor
• Real time reporting for analytics
• Monitor test or functional paths
• Optimize silicon performance based
on actual timing margins available
Clock & Delay Monitor
• Clock duty cycle quality check
• Memory access time tracking with BIST
• Digital delay line test characterization
© 2023 Synopsys, Inc. 25
Synopsys SLM PVT Monitor IP
Widely adopted, well established solution

140+
Global Customers

600+
Design-Ins

28-3nm Widely adopted across node

Advanced Node Advanced
Support multiple applications
solutions to 3nm

Modular Synopsys SLM PVT IP Monitoring IP for Advanced Node Process Technology
© 2023 Synopsys, Inc. 26
In-Chip Monitoring for SoC Visibility for Secure HW Architectures
Synopsys SLM PVT Monitor IP used in Arm Morello SoC

Enabling the Future of Security Applications

• Arm Morello SoC integrates Synopsys SLM PVT monitor IP

• Temperature Sensor: Measures the temperature and issues
alarm, or shuts down the system when beyond the user-
defined thresholds
• Process Detector: Judges the process skew of each device
relative to the population
• PVT controller: Monitors and manages the subsystem of
monitors, relieving the system control processor of many
associated tasks

https://www.arm.com/architecture/cpu/morello

© 2023 Synopsys, Inc. 27

 Silicon IP
IP supporting Arm AMBA interconnects:
Interface IP, Logic Libraries, Embedded
Optimized Implementation Memories, NVM, AMBA Bus Fabric and High Performance Verification
Synopsys Design Tools, Peripherals, coreAssembler tool VCS ® RTL Verification & Verdi ® Debug,
QuickStart Implementation Kits (QIKs) VC Formal™, VC SpyGlass™ RTL
High Performance Core Centers, Signoff, VIP for AMBA Interconnect,
Low Power Methodology, VC LP™ & Verification Methodology,
Synopsys.ai – Full Stack EDA Suite ZeBu ® HW-Assisted Verification
Optimized Hardware Design
Implementation and Verification

synopsys.com/arm Hybrid Emulation

AMBA Transactors
Software
System Compliance
Development and
and Validation
HW/SW Integration

FPGA Prototypes Virtual Prototypes

HAPS ® Support for Arm Cores, Virtualizer™ Development
Connection to Juno Arm Development Hybrid Prototypes Kits (VDKs) for Pre-RTL SW Dev.
Platform, Prototyping Methodology AMBA Transactors Using Arm Fast Models,
Arch. Design with Platform Architect,
Coverity and Defensics SW Signoff
© 2023 Synopsys, Inc. 28
 Thank You

Synopsys Confidential Information