(UNIT PRocrammaste Locic pevicks AND s CMOS Testinc PROGRAMMABLE LOGIC DEVICES : Design Approach = PLA, PAL, Standard Cells, FPGAs, CHLDs CMOS TESTING : CMOS Testing, Test Principles, Design Str for test, Chip level Test Techniques. LEARNING OBJECTIVES Concept of high level design approach of various programmable logic devices Basic idea about PLA ond implementation of various logic function using PLAS, Basic idea about PAL ond implementation of various logic functions using PALS Concept of standard cells Basic idea about CPLD and implementation of varous combinational and sequential logic circuits vsing PROMS Concept of CMOS testing and its need Various test principles used for testing CMOS circuits Various design strategies for test 99499999999 Brief Idea about di rent chip level test techniques This unit deals with the design approach of various programmable logic devices and study of architecture of PLA, PAL, FPGAs and CPLDs, which are the basi building blocks inthe design of various systems. This unt also describes about testing of CMOS circuts Even though, a component Is manufactured using correct design, it may have foults and defects that may occur during fabrication, doplag levels, stress, short circuit and ether Factors. To tenure proper functioning of ‘component, different testing methods are carrled out. ‘SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS5.2 VLSI DESIGN LINTUHyp, —_——— BR (PART-A) SHORT QUESTIONS WITH SOLUTIONS” XX, Q1. Why low powor VLSI circults aro noodod?: Ans: re 1 Dreaty, __- Inrecent times, power dissipati ng the design process of VLSI circuits, Wit he increase in spegg 5M, jninimization of VLSI cireuits the power constimption became an important design fel. Especially the battery i bi 9 is decided by the power consumption, Hence, the designs, users and ecological factors insist on reduction of poyee atone in VLSI circuits, Hence, the low power VLSI circuits are required. 2, What are the types of programmable dovicos? An: (ode 7 5) May, Based on the arrangement of programmable gates, programmable logie devices are divided into three types. They are, "ty 1. Programmable Read Only Memory (PROM) : Programmable Logie Array (PLA) 3.___ Programmable Array Logic (PAL). Q3.” What is programmable logic array? Peet, oT 5 (or) Explain the principle of PLA. Ans: i binational logi A programmable Logic Array (PLA) is a programmable device used to implement combinational logic ci PLA has a set of programmable AND planes, which link to a set of programmable OR planes and which can be Condi? complemented to produce an output. | J PLA has 2" AND gates for V input variables and there should be MOR gates for Moutputs, oe Prosiamabi itp from all of the AND gates. This layout allows for a large number of logic functions to be synthesized i im of Products ‘sometimes product of sums) canonical forms. Qé. What are the advantages and disadvantages of PLAs? An: Advantages 1.’ If two or more output functions have a common product term that can be shared by different OR gates, the PLA ateara, be reduced. 2. These offer enhanced flexibility in the design of complex systems, Disadvantage ‘The propagation delay of the gate will cause the inverted input to change for a short time after the application of ras inverted signal. : G5. Write the advantages and disadvantages of FPGAs. Ans: : ‘The advantages of FPGAs include, 1. Shorter time to market. . 2. ‘Ability to reprogram in the field to fix bugs. 3. Lower non-recurring engineering costs. , ‘The disadvantages of FPGAs include, 1. FPGAs are slower compared to ASIC counter parts. 2. They cannot handle complex designs. i 3. Consume more power for any semiconductor process. Q6._ Write the comparisch between FPGA and GPLD. May-47, (R190 Ans: ‘The comparison between FPGA and CPLD is shown in table. =>) WARNING i: Xerox/Photocopying of his books a CRIMINAL act: Anjone found gui is ABLE to face LEGAL proceedings.Fe _ unit S (Programmable Logic Devices and CMOS Testing) . 5.3 Complex Programmable Logie Devices (CP »» Pi able Gate Arrays (FPGA) Tage CPLD's have on-chip nom Tleld Programm i Volatile memory. 7] Small FPGA do not have on-chip non-volatile memory. ‘The density area of CPLD range: | is upto sat eas niges from low to medium ic, | 2. | The density arca of FPGA is medium to igh. Ii upt CPLD's interconnects are cross bar that | CPL a s bar that gives the intercon- | 3, | FPGA's interconnects are routin sect etn Various paths to execute the desired output. | | of logical functions. ‘The speed of operation is fast and predictable. 4.| The speed of operation in FPGA is dependent on application and varies from application to application. 1 million gates. that allows the flow _ Table Ac Wmploment 2:1 MUX using PAL, = pnst ‘Apia, (R13), 10) ‘The block schematic of 2 * 1 multiplexer is shown in figure (1), x axN Mux. Ss Figure (1) From figure (1), the output of 2 x 1 multiplexer can be expressed as, Z= 3X +SY From the above expression, the 2 1 mux using PAL can be implemented as shown in figure (2). spo a Figure (2) x. @8. Compare PLAs and PALs. 7 eos, (R16), 1G) (or) O) Explain difference between PLA and PAL. Ans: . . ‘The differences between PLA and PAL are mentioned in table. PAL PLA May-16, (R13), a1) 1. | Programmable Array Logic (PAL) consists of a] 1. [Programmable Logic Array (PLA) consists of a programmable AND array and fixed OR array. programmable AND array and a programmable OR array. 2,| The AND (or product) terms cannot be shared among] 2. |The AND (or product) terms can be shared among two two or more gates. or more gates, 3.| Basic configuration of PAL is shown in figure (1). | 3. | Basic configuration of PLA is shown in figure (2). Inputs | Programmable| Fixed [Outputs Inputs] Programmable|__[ Programmable] Outputs AND army OR array AND array OR aray Figure (1) : Figure (2) Tablex What te the need of Tonting? S (or) a What isthe neod for tenting of 16? Ana 9 general the position of a particular IC is Ene 0 war may mat be operate eet ae “PP 8 dhe to miniature defer it the processing sep The atove mentioned all reasons are responsible metioning of chip. Thus, the aim of ates Procedure ig, Ae Eui0e andl use a poo he (chin a = S20. Detine controtabity and observablly with rospact to toating, Ana: “eng Controttapiity 7 ‘Controllability is defined as the ability of setting a particul logic signal to +9» or‘T’, Seating 8 harticulr cit Thee vale ating am be done bythe Input Pas ‘estan the controllable nos. So it is easy to contol by using IPs, Observabitity Nis used to analyze the yi 3! The min tan don "asy observation of gate Exquired to measure output node value. O11. Whatis the difference between verification and validation? Ans: 0 The differences between verification : APA RID, on and validation are mentioned in table, I Verification {tis the static procedure of auditing the data such as documents, program, code etc. Validation 13s the dynamic, procedure of validating and testing the actual product, 2, [It is done manually, 2. | Itis done using simulators, 3. [This process does not include code execution, | 3, ‘This process includes code execution. Table ‘Q12. What type of faults can be reduced by improving layout design? Ans: May, (R19, 019 Open circuit type and short circuit type faults can be reduced by improving layout design: Itis done by us algorithm and layout synthesis tools such as routers, Q13. What are the different chip-level techniques? An: sing competion ‘The different chip level test techniques are, 1. IDDQ testing 2. Built-in-self test 3. Automatic Test Pattern Generation (ATPG). WARNING: Xerox/Photocopying ofthis bok sa CRIMINAL ect. Anjon find guilty i LIABLE to tace LEGAL proceedings.5 (Programmable Logic Devices and CMOS: Tosting) (PART-B) Essay questions WiTH sorUrions aay PROGRAMMABLE Losic Devices M1 Design Approach bites 4. Cleatly explain each stop of high lovel dosigh flow of an ASIC, oma Mosel Ppa 148) Figure illustrates the steps involved in high level design flow of an ASIC. unt cu) 4) poe Toga Di Petar | Fae design entry ‘simulation | FL ore ® Ky sat syn OF" system rita | f} ao oer Povkea] SR : oe ming [| seme | SRE ‘ol Phere bows} | | ciecut rt Logie j Rowing |} extraction st I rau ; igure ‘The steps involved in high level design flow of an ASIC are described as, Step 1: Design Entry In this step, the design is entered into an ASIC design system by using a Hardware Description Language (HDL) or a schematic entry. Step 2: Logic Synthesis Inthis step, «netlist is produced with he help of an HDL (.c, VHDL or verilog) and a logic synthesis tool, Netlist isthe description of the logic cells and their connections. Step 3: System Partitioning . In this step, a large system is divided into ASIC sized pieces. Step 4: Pre-layout Simulation . In this step, itis verified that the design functions properly. , Step 5: Floor Planning In this step, the blocks of netlist are arranged on the chip. Step 6: Placement Inthis step, the locations of standard cels are decided within each block, Step 7: Routing Tn this step, the electrical connections are made between the cells and blocks, . ‘Step 8: Extraction In this step, resistance and capacitance of he interconnects deterined, b Step 9: Post-layout Simulation Tathisstpa final verification is made to see that the design still functions properly with the added loads ofthe interconnect. | SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS, BRAN'mic/Behavioural RTL levevData tows ate Tew ¥Atworitnee Steuetural hm / Rehavi his nt / Behaviourat rte enti that i, i 2 specitien it bithest level of abstraction. At this level, the abt tion desrbes the futons” f 2 the eye level of abstaton. At hs level, se abt ery Level Dan nshiP Between the input and ott teas Gn ata Flow : every RTL TRTL Level, the daten soar design il eee ae Fic sists ofa en a How between the registers and data processing of Me CET ocks. or the BO it, Stebel clock is aia oe and operations will be performed in specified number ‘ate Level / Strnenaay l/ Structural nected 10 pert ate level absrcton descids an ent a a ollectn af es ad compoens ta fe TTT citianres Specify pabttetion describes an entity as a coleton af gts a Ae Wihnat ee Ti a phyiea desrnin ofthe en Ans: grammable devices? How It differs from ROM? we (9) am) ° ofcombinational and sequenti ss.an 1 which canbe fogrammed to cary-outa broad MEE CCRT AY scp gam tes pen hen gana oro AP mH Pass a few flipflops and registers. 4 , Figure i . igure illustrates the basic block diagram of a programmable logic device. ee A pd L—s, A Ee] = ano 2 ES cee ae oe oot 5 | puter [FF - prot mal eee Butter | * pe] Me alec: a ie Block Diagram of PLD Figur ‘The input buffer generates complement for each of the digital code applies their complements are applied to the AND matrix, which can handle 2" input combi _ to produce the desired result. In certain type of PLDs, the OR matrix s also programmed to produce result. Then, these are passed to the output terminals via the output buffers. ‘The differance between PLDs and ROM ere, In a PLD, we can program both AND and OR arrays, whereas in a ROM, we can program only the OR array. 1 |) 2). ‘A PLD uses a programmable address matrix whereas the ROM uses an address decoder. 3A PLD allows the programming of simplified boolean equations, whereas to program’ a ROM, it is essential to have x honical form boolean expression. As a result, a PLD can have greater inputs than a ROM. te the basic types of programmable elements of PLDs. dat its input. The input code words along with ‘nations. Then, the AND matrix is programmed specific combinations of the Qi7._Demonstrat ‘octiNov.20, (R16), 80) An: ‘A programmable logic device is an integrated logit cireuit, which is wer programmable. Iti bascall sed of programmable gates arranged inthe form of AND array and OR aray. Se arrangement of programmable gates, the basic types of programinable elements of PLDs are di Based on the .¢ types. They are, te Te programmable Read Only Memory (PROM) . ‘Array (PLA) | programmable Logic FA Programmable Array Logie (PAL). WARNING: Xerox/Phatocopying ofthis books @ CRIMINAL act. Anyone found guy is LIABLE to face LEGAL j ; proceedings.th yNIT-6 (Programmable Logie Devices and CMOS Tosting) 7 ‘Read Only Memory (PROM): PROM isa Sta Pail PLD with fixed AND array and programmable OR array as shown in figure (I). The fixed AND array is constructed as a decoder, whereas the programmable OR array provides the implementation ‘of boolean functions in the form of sum-of-mintetms, Fleed AND i —— rogram a ey DeseerA——| a Figuro (1) 2, Programmable Logie Array (PLA): A programmable logic array is. combination of programmable AND array and programmable OR array as shown in figure (2). In this device, the product terms of AND array can be shared with OR array for SOP (Sum of Products) implementation, (Zaz — "oy roganinahe Co AND aay Okey Figure (2) Programmable Array Logie (PAL): A programmable Array Logic (PAL) formed by combining a programmable AND array anda fixed OR arrray as shown in figure (3). ‘The programming of AND array provides the product terms for boolean functions. ir j—rowpae jb ouipus 3B Programmable ‘AND amy Fixed a —>—| ORamy 4} routs igure (3) aE pa ences ies bate Q18, Draw the schematic for PLA and explain the principle. What are the advantages of PLAs? (or) Withaneat sketch clearly explain thearchitecture ofa PLA. Ans: Programmable Logic Array (PLA) Aprogrammable Logic Array (PLA) isa programmable device used to imptement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a setof programmable OR planes and which can be conditionally complemented to produce an output. ; ‘PLA bas 2" AND gates for N input variables and there should be MOR gates for M outputs, each with programmable inputs from all of the AND gates. This layout allows for a large nurnber of logic functions to be'synthesized in the sium of products (and sometimes product of sums) canonical forms, Figuie shows the architecture of 4-input and 5-oulput SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS) © 8.7 24 16 Programmable son a Figure In the figure, the 4-input variables i.e., A, B, C, D are applied to,24=/16 programmable AND gates and with the ‘outputs from each of these gates, S-programmable OR gates are used to prodyce the required number of outputs. In. this PLA implementation, a single line is drawn to represent all the inputs to.a gate and a cross is used to indicate those inputs lines that are connected to that gate. Advantages — - 1. Iftwo or more output functions have a common product term that can be shared by different OR gates, the PLA area can be reduced. 2. These offer enhanced flexibility in the design of complex 4 systems. Disadvantage ‘The propagation delay of the gate will cause the inverted input to change for a short time after the application of non-inverted signal, Applications 1 a ‘These are used to implement control over a data path. ‘The regular structure of PLAs with programmable AND and OR arrays is used in complex systems involving ‘many variables, 3, PLAS are used to perform programmable logic sequencing and finite state machine operations with the registers at input and outpitt Ty TES5B 919. What aro the draw backs of PLAs? How PLAS Sro used to Implomont combinational and nay Aantal logle elrculte? Drawbnck of PLA For answer refer Unit, Q18, Topic: Disadvantage. Implementation of Combinational Logle Cireult Using PLA. The implementation of combinational logic circuit using PLA can be clearly understood by consider the following example. Consider the circuit symbol and truth table of «two input XOR are shown in figure (1) and table (1). Letx and yar inputs and Z is the output of XOR gate. May, (R43), 1040) x ¥ VLSI DESIGN [JNTU-HYDERABAD, Ton of Sequential Logic Cireult Using PL UitS usin PLA can be clearly understood by consider the followine cxample, Consider the logic diagram of JK Aip-Aop is shoye ax Figure (3) Figuro(t) Here, J and K are the inputs with a clock pulse “CL x» ‘and Q isthe output. Then, the characteristic table or truth table (of JK fip-flop is shown in table (3). Qo Ts [KT eee o fofo| o o fofi] -o Tablet) o fifo} 1 ‘The output Boolean expression of atwo input XOR gate ofalil 4 is piven by, _ mealtsd (Roll ment eae i 1 fofil o “Then: the above Boolean expression can be easily imple- mented using PLA by preparing a PLA programming table for a the above Boolean function. The function Zcontains two product 1 fifa} o terms ie..xy and: y. Table 2) shows the PLA programming Tat table for Boolean function Z. + Product Inputs Output eee term |x y z a xy-l 0 1 pau, o| o ° a y-2 | 0 1 L in Table (2 aa aa ° o| of Figure (2) shows the implementation of two input XOR te PLA. a x y Fire” ‘Thus, the corresponding characteristic equation for JK flip-flop is obtained as, Ott 1)= JO+KOQ ‘Thus, we have two product terms JQ and KQ and single output i., O(¢+ 1). Then, the PLA programming table for JK flip-flop is shown in the following table (4). [ WARNING: Xerox/Photocopying of this book is a CRIMINAL act Anyone found guilty is LIABLE to face LEGAL proceedings. | Product Toputs ‘Output Term eT s TK |at+n IQ o 1 = 1 Ko2 1 - 0 1 Table (4)Bar nib (Programmable Logic Devices and CMOS Testing) plementation of JK flip-flop using PLA Ts shown FQ e+ = +FO | Figure 4) sASPAL OG i 20. Draw the typical architecture of PAL and explain the operation of it. (or) With neat sketches explain the architecture of PAL. Anst 2 Programmable Array Logic (PAL) ‘The Programmable Array Logic (PAL) describes a family of programmable logic device semiconductors used tn implement logic functions in digital circuits. PAL device consists of a small PROM (programmable read-only memory) care ad additional output logic used to implemént particular desired logic functions with few components. * Using specialized machines, PAL devices were sfeld-programmable”. Each PAL device was “One-Time Programmable” (OTP), meaning that it could not be updated ‘nd eused after is initial programming. : Architecture of PAL ‘The programmable elements connect both the true and conplemeited inputs to the AND gates. TheseAND gates, also inown as product terms, are ORed together to form a sum-of-) products logi array, The basic architecture of array logic is, Stow in figue (1). ; 5 Japs & Fp slop Feedbacks i SPECTRUM ALLAN ONE JOURNAL FOR ENGINEERING STUDENT: 5.9 ‘consists of two main components. ‘The PAL architecture: They are, . 1. Programmable logic plane. 2, Output logic macro cells. 1. Programmable Logle Plane Figure (2) shows the internal implementation of @ programmable logic plan * ty at L 7 Progamatie Conecten vA ees QO eo Ree] x oy 2 =” Figure (2k: 24nput, 3-Output PAL + ‘The programmable logic plane is a programmable read- ‘only memory (PROM) array that allows the signals present on the devices pins (or the logical complements of those signals) to’be routed to an output logic macrocell. "PAL devices have arrays of transistor cells arranged in a “fixed-OR, programmable-AND” plane used to implement *sum-of-products” binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs. 2. Output Logie Macro cells Figure (3) shows the intemal implementation of an output ‘macrocell. The outputs were active low and could be registered ‘or combinational. Members of the PAL family were available ‘with various output structures called Output Logic Macro Cells ‘or OLMCs. The types of OLMCs available in each PAL were fixed atthe time of manufacture, before the introduction of V (variable) series. Even though-each output could have up to, 8 product terins, the combinational outputs used one of:the terins to contro! a bidirectional output buffer. There were other ‘combinations that had fewer outputs with more product term per output and were available with active high outputs. The fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because ‘output structures of different types were often required by their application, This leds the introduction of PAL V series, in which the number of product terms allocated to an output are varied from 8 to 16, This one device could replace all of the 24 pins fixed function PAL devices, Each macrocell could be configured “by the ser to be combinational or registered. CORA AFiguro (3) CIN Pi . Q21. Draw and explain the antifuse structure for programming the An: a device. An alternative itchit responsible for program x 3s in characteristics of switching element are resp iaees lading eye pantogrephy, Te vould Seo eT AA hn ee donlonind bm tae of cine a Sacer 5 ing approaches are represented by prods from Actl, Quicklogie and o coal ee re (Proammable Low Inpetce Cie Element) sa basic lene for Atel Field pr rn le Gate Arye Normals eter oe heh tn 100M) ene Ts anti i charged permanent vies ee aioe (200-500 2) by the application of appropriate programming voltages. Figt : antifse. ‘The characteristics of 2V10 PAL CMOg device are as follows, 1. Thas 12 input tines, 2. Itinelude 1010 cells, 3. The availabe product erms are, 9, 10,13; 14, 16, 14, 12, 10,8, 4. This 22V10 PAL.CMOs is 224 5. The typical speeds for 22v19 @ CLK to outputis 8 nsec Gi) Input to combinational output is 15 nice, 6 Typical toggle frequencies with feedback. arg pin package, inhigh speed CMOS are, ‘around 40 MHz, WARNING: Xerox/Photocopying of this book is CRIMINAL act: Anyone found put ig UABLE : ‘01958 LEGAL proceedin ws. Eo(Programmable Logie Dovicos and CMOS Tosting) 5.11 For Fit ys way “PMG For F2: i mt val ane | te 1 , “(al igure 2 Paley BPE Explain the methods of programming of PAL (CMOS device. ‘Ans: , There are three methods for programming PAL CMOS. devices. They are, 1. _ Fusible links method 2., UVerasable EPROM method 3. EEPROM method. 1. Fusible Links Method Fusible links makes use of metal like titanium tungsten or platinum silicide to form the links. These links are [ater on blown away by exceeding the current. A laser can also be used to cutdown the fuse. 2 UVErasable EPROM Method ‘The control gate is provided with voltage around 13 10| 14V and the drain is held at around 12'V. This negatively charges the floating gate and increases the threshold of the transistor. Hence; this circuit will be OFF for normal , voltages around 5 to 6 volts. Finally, the gate is focussed with UV light. 3, EEPROM Method EEPROM technology is the most widely used technol ogy. Access transistor and programmed transistor is used. in ROM cell. Programmed transistor is built with a two- poly sandwich. The electrons tunnel in or out from the floating gate through a thin oxide presence between the floating gate and the drain. This will tum OFF and ON the cell purposely. The series-access transistor allows programming of cells. Q24, Realize the following function using PAL, FA(x, y, 2) = 2(1, 2, 3, 4, 5, 7) F2{x, y, 2) = £(0, 4, 3, 5, 7) (Model Pape, Q10() | May-19, (R15), 10a) ‘The given boolean functions aré, ' FUG, y,2)= 21,24, 57) F(x, y, (0, 1,3, 5,7) ‘The above functions can be simplified by using 3-variable Ans: kemap as, ‘GURL TSPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTS From the above simplified boolean expressions, the PAL programming table is obtained as shown in table. Product |__!puts Outputs term [x | y xyz | o [fo rat F(a, ys 2) = 397+ 09 + Fat x w | 1 [ole yz | - [of] x [1 f-|1 Fx, ¥,2) = RY +Z xy | o [ol- zp ='fP-fa Table ‘Then, the implementation of given boolean function using PAL is obtained with the help of table as shown in figure. Fly?) Freya) FigureQ25. Design tho following function using PAL Yo x'y'w zw! tor Ans: b PAL is neronym for Programmable Array Li the commonly used Programmable Logie Deviee (PLD). APAL- ‘has programmable AND array and fixed OR array. ‘The given boolean functio (RA), 10) fe and is Y=s'pwt? thas three AND term's and only one OR term. The realization of} azusing PAL isns shown in figure. Figure Q26. Design a PAL to realize a full adder ‘Ans: ec.48, (RES), 1012) ‘Acombinational circuit that performs the addition of vo binary inputs and a carry input is called as full adder. Ittakes two inputs.X and ¥ and a carry input C,, and generates two outputs. ‘One output is the sum (S) of the three inputs, while the other is a carry (C,,) generated after performing the addition. ‘The block schematic of full adder is shown in figure (1). x sum (9) of Y ——_ FlllAdder Ourputs Ce Carry (©) . are (1) S The truth table for one bit full adder is shown in table (1). Tapats Outputs x] vlog] s [ou ofofofofo ofolififo of 1rfofa fo ofrfafofa 1} ofo}1]o rfolafo}a rf afof}o fa 11h ata] 1 Table (1) | WARNING: Xerox/Photocopying ofthis book s @ CRIMINAL act: Anyone found guilty is LIABLE to facé LEGAL proceedings. © " proceedings. IGN [JNTU-TTVENABA, implified express = K-map 05 (s) , n 10 Wry of _ O7— xv XYCn [P. 1 [x Ty TPo]o]|o] oo ofifo}o]o |r ofo}i}o] 1 fol olofojitits Tabla (1) From the characteristic table itis clear that the 4-1o-2 encoder is having 4-inputs and 2-outputs i., Dy D,, Dy, D, and x, -ysespectively. Thus we need an 4-input, 2-output PROM to implement 4 to 2 encoder. ‘The basic block diagram of PROM is shown in figure (2) and the required input, 2-output PROM block diagram is shown infigure (3). ie 2™xn : ins PROM aoe ‘ Figure (2) D, —>| D>] wx] e D, >| PROM : Figure (3) Thus, 16 x2 PROM can be implemented using a 4 * 16 decoder and two OR gates. Figure (4) shows the implementation of 4 to 2 encoder using 16 x 2 PROM.visi DESIGN | SAD) 5.22 ‘Q37."Implomont 2-bit comparator using PROM. An es ther relative magning, i 1A As «2 pasatoris shown in Figure (1 ‘The output of any comparator is specified by three binary variables sm of 21 je block dingra indicates each number is considered with two bits ic, 4, and B, By ‘pnd determi bs are Ai AcB aor Dy ——} Goma AcB 3, 5 Figur ambers A and B respectively. They Where dy and B, are east significant and, and 8, ae most sigifiant its of RE" the characteristic or truth table of 2-bit comparator is shown in table. Taputs Outputs AYA [moe] Ane [ASB ofofojo] o 1 v ofofofil o ° ' o}ojijo 0 0 u o}o}iji O° 0 1 o}i}ofo 1 0 a of rfofr 0 1 Q ofijafo} o 0 1 ofufafaf o 0 1 t}ofoyo} 1 ° o E r}ofofif a o 0 1}ofafo} vo 1 0 thofiulal. co ° 1 r}rfolo} 4 ° 0 é ttifo la 1 0 of ; ryitito} 0 0 rtrtriil io 1 0 Table From the characteristic table, itis c > B,A=B,AB A=B AsB Figure (2) Thus, 16 x 3 PROM can be implemented usi x of 2-bit comparator using 16 x 3 PROM. Nese IS dcoderan tree OR Bates, Fi ‘Site (4) shows the implementatio™ (erox/Photocopying ofthis book is a CRIMINAL act: An 0 pokisa CR Me found pity i 'yis UAB LE to fage LEGAL Droceatings. Jo)a UNIT-5 (Programmable Logic Devices and CMOS Testing) 5.23 oxo sot oro ‘att 10 ovat F uo ot 1o10 ‘ot 0 no m0 ut 2 52A Introduction ‘38. What is principle of testing CMOS circuit? Explain any one procedure for it. (or) A Write a short note on CMOS Testing. Dec.8, (R15, ata) (or) Why the chip testing is needed? At what levels testing a chip can occur? (May-17, (R49), Q1 | May- (t9), 21010) . (or) What is the need for testing and explain the two categories of testing. Ans: Need for Testing Tn general, the production ofa pastcular ICs the rato of number of good dies tothe total number of des Pes Wal All the dics ns wafer may not be operated correctly dve to the complexity of manufacturing process. The incorect operation of 8 chip is due to miniature defects in the processing steps. ‘The above mentioned all reasons ae responsible for malfunctioning of chip. Thus, the aim ofa test procedure isto deter mire and use a good die (chip) inthe end systems. The different levels at which testing occurs, 1. Wafer level 2, Packaged - chip level 3. Board level 4 5, ‘System level : 7 Inthe field. : ‘By knowing the defects ofa chip at wafer levels leads tothe low fabrication cost. The following information shows the relative cost to recognize the fault of their respective levels. : : Wafer level =» $0.01 - $0.1 Packaged chip level -__ $0.1 -SI1 ~ Board level = $1-s10 4 System level = $10=$100 Field level 7 $100 - $1000 = ‘SPECTRUM ALLIN-ONE JOURNAL FOR ENGINEERING STUDENTSNW JNTU-TTZENAB AD) gi DESIG! in vi scuring Tow, iF the coat are detected at wate level ; are Kept 10M, above information, he testin ers are nee the testing at the packagedschip level or board level, follawing parameters Me Expenditure to develop suitable tests at the wafer level omme electronics respectively, ~ Mixed signal conditions ~ Speed consideration, allt . ‘The wafer level and aystem levels ess can he done by component vente aid al ee Categories of Testing ‘There are two categories of testing available. They are, c 1 ytionality test 2. Manufacturing’test. eee 4 Reecarant Tet eared so cheek whether the cite iB a8 per in Functionality testing. the whole design pro ction is verified ification. = tiven fantom or mo is egies the valent se resin The specification is any one of the following, - (i) Verbal definition or explanation ; Gi) Plain - language text (ii) Pascal, C, FORTRAN Ge) VHDL, verilog ete rl 5 _ratso involves to check the equivalence to , (¥) Tables contains inputs and outputs ‘The specification which is used is comprises of any two descriptions of chi inputs and outputs at available checkpoints in time. A ‘The better exact checking is performed on a cycle-by-cycle basis. There is no B ; functional tests be written. The best solution is to stimulate the chip or system as closely as poss! real world. ‘ Its impossible in several cases due to following reasons, (i) Reluctant and slow simulation times. (ii) Very lengthy information sequence, a0 One approach isto divide the simulation hierarchy into a small modules at lower levels. 2 Manufacturing Tests ‘The manufacturing testing methods are used to detect the ‘manufacturing done by checking the operation of gates. F ‘The following are defects in manufacturing tests. i (i) Layer-to layer shorts (i-e., metal to metal) ° (ii) Discontinuous wires (iii) Thin oxide shorts to substrate or well (iv) Nodes shorted to power or ground (v)__ Nodes shorted to each other. wi To detect the above defects, manufacturing tests is needed through verifying the gate’ and registers. These tests are normally carried out at the wafer level to cull out bad dies, and then on the packaged parts. The length ofthe tests at wafer leyel might be shortened to reduce test time based on experience with test sequence, ‘of internal gates, I/O integrity is also tested through completing the following tests} ‘od theory on how to ensuite’that good oe possible to the way it will be used in defects in a chip during their fabrication. This is ‘Apart from verifica 1, WO-level test 2 Speedtest t 3. Iga test ‘The J, test checks the leakage ifthe circuit is composed of a complementary logic, Any ‘oo Be in » Any value marks ted value of a given wafer normally indicates an internal shorting failure. Water tests may be done at high peed clon speed ‘ive to possible power and ground bounce effects that may be present in the older testers, Manufacturing tests generation concludes that chip circuit function i based onall gate inputs and by control all the required gate outputs, A Q39. Compare functionality test and manufacturing test, ans: The comparison between functionality test and manufacturing (est is mentioned in table WARNING: XeroxiPhotacop/iapot his book is @ CRIMINAL at. Anyone foun uty LABLE tote LEGAL . Proceedings. |UNIT-§ (Programmable Logic Davices and CMOS Testing) 5.25 Functionality Test Manufacturing Test | This test verifies 5 1 ete ar ae snchip performs its intended func- | 1. | It is used to check the functionality of gates and registers. » these assert that all the gates in the chiy acting inconcert achiever desied factions 2 Tee Terns sually used early in the design eycle to 2. | These tes are used after the chip is manufactured to functionality of the circuit, verify that the silicon is intact. ane cas oe stuctions in a test can be merged by | 3. iis possible to check the value of egisteri.e or I and 8 postion) ' to test that exercises each bit in any adder and ensures that carry chain is not broken. 4) Functionality test generation assumes thatthe adders, | 4. Manufacturing test generation assumes that the circu imoltiplexers, gates and registers in the microprocessor |_| chip functions correctly and ways of exercising all gate latapaths operate correctly. inputs and of monitoring all gate outputs are required. ae Table 5.2.2 ‘Test Principles: : Q40. Explain what is meant by a Stuck-At-1 (SA1) fault and a Stuck-At-0 (SAO) fault. Ans: (or) paransistor gate to V,,) or metal-o-metal shorts. Ans: vOU> your Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram. Todeal with the existence of good and bad parts in CMOS cireuit, we propose a “fault model”, that is, a model for how faults occur and their impacts on circuits. The most popular model input is modeled as a “Stuck at zero” (Stuck-At-0, S-A-0, SAO) or “Stuck at one” (Stuck-At- from’board level designs, where this was determined to be an adequate set of models for modeling faults. Figure illustrates how an SAO or SAI fault might occur. These faults most frequently occur due to thin oxide shorts (the n-transistor gate to Vy, or the called the “Stuck-At” model. With this model, a faulty gate $-A-I, SAI). This model dates. our OUT Figure: CMOS Stuck at Faults Q41. Explain what Is meant by short circuit and open circuit faults. for) Explain the different kinds of physical faults that can occur on a CMOS chip, and relate them to typical circuit failures. . Figure (1) shows two shorted faults. The shoit $1 in figire (1) is modeled by an S-A-O fault at input 4, while short S2 ‘modifies the function of the gate. To ensure the most accurate modeling, faults should be modeled at the transistor level, because ‘the complete circuit structure is only known at this level. e 52 modifies Fanetn of ete Figure (1) 0707 SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS! ONopie is ilustrated 0 gurg Tn GMOS, fhult generation Is po mvert a combina 2). Itis caused due to missing connestions of souree, drain oF wate~ Jayed lay the gate ion disp ITA transistor connection is missing, then fu F= NOTA + By + (A. (NOTB). FD Figure (2k A CMOS Open Fault thot Causes Sequentil Felts ICB transistor is missing, then the function is, F=(NOT(4+8))+((NOTA).B.F,) Itany one of the p-transistor is open, the node would be charged to high tll any one of n-transistor discharge the node. In-will caaee leakage effects Due to these, research department search for new method the transistors oF switches, also exhibit ‘stuck open’ and “stuck closed” state which are founded by observing statie Vp current (Igo), Consider the gate fault shown in figure (3), where a p-tansistor in a 2-input NAND gate is shorted This could physically occur if oan etal Srerlapped the source and drain connections or ifthe source and drain diffusions shored. f we APBIY test seer oa und B input end measure the static y, curent, we will bserve that irises to some value determined by the P ratios of the n and p transistors. Figure (3): A Dofect that Causes Static lp Current WARNING: Xerox/Phatocopying of this bo 4 a IMINAL ect Anyone found pity is UABLE to face LEGAL proceedings. Ji” ings. |UNIT-5 (Programmable Logic Devices and CMOS Testing) Q42. What is'sequential fauit grading? Explain how it is analyzed. Anst : Hay-6,(R12),011(0) ‘The amount of fault coverage achieved by atest program is the measure of its goodness ie. percentage of the chip's, jnternal nodes checked for the applied vectors. The method to ‘aloulate fault coverage is described below: In this method, each circuit node is taken in sequence and held to 0 (S-A-0) arid the circuit is simulated, comparing the chip outputs with a known “good machine (ie. a circuit swith no nodes artificially set to 0 (or) 1)". When a difference jsdetected between the “faulty machine” and “good machine”, the fault is marked as detected and the simulation is stopped. ‘This is repeated for setting the node to I (S-A-1). In turn, every node is stuck at 1 and 0 sequentially. _ Whereas, the percentage of total faulty detected nodes {or applied set of test vectors represents the fault coverage of vectors, This method of fault analysis is referred as sequential fault grading, 43. Explain the terms controllabi and fault coverage. ‘Ans: Observability Observability of any internal node is a degree to which it can be observed that node at output operates correctly. It is very useful to a tester/engineer to measure the output of a gate with in'a complex circuit to check its correct operation. The ‘main goal of any design engineer is that ¢asy observation of gate outputs. Higher obsérvability indicates the less number of cycles required to measure output node value. Controllability - ‘The ‘controllability is defined as ability of setting) particular logic signal to ‘0” or ‘I’, It is used to analyze the difficulty of testing a particular circuit. These value setting ean be done by the input pads [IP's]. The main goal of any designer is to design the easily controllable nodes. $0 itis possible to control easily by using IP's. Fault Coverage Fault coverage is defined as the percentage of fat that canbe founded by the applied test vector It gives the measure of goodness of test program. The calculation involves the following steps, (i) Every individual cireuit node set to logic ‘0” one by one, (i) Then the output is compared with the ‘good machine". (iii) Ifthe output doesn’t accurate, then it comes under “faulty machine’. (iv) Then above steps are repeated by set the circuit node to logic ‘1’. ~ f (W) Percentage of fault coverage is, Number of faults detected % fault coverage = “Total nodes in the circuit wet ‘SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS - 5.27 Gad, What is ATPG? Explain a method of generation of test vector. Ans: ‘Automatic ‘Test Pattern Generation (ATPG) is defined as the mechanism which is used in semiconductor electrical testing where the appropriate input patterns are check a device for faults which are automatically generated by a program. The ctors are sequentially applied to the device under test and dhs deviee response to each set of inputs is compared with the texpected response froma good circuit. An errr" inthe response ofthe device means that itis faulty. The effectiveness of ATPG is measured pririarly by the fault coverage achieved and the cost of performing the test. ‘A cycle of ATPG can generally be distinct phases, they are, 1. Creation of the test and 2, Application of the test. During the creation of the test, appropriate models for the device circuit are developed at gate or transistor level in sucha way that the output responses of a faulty device for a ided into two J ‘given set of inputs will differ from those of a good device. This generation of testis basically a mathematical process that can be done in three ways. 1+ By ‘manual’ methods > 2. By ‘algorithmic’ methods and 3. By ‘pseuido-random’ methods. “When creating a test, the goal should be to make it as, efficient in memory space and time requirements as much as possible. As such, the ATPG process must generate the minimum ornear minimum set of vectors needed to detect all the important faults ofthe device. The main considerations for test creations are, 1... The time needed to construct the minimal test set 2. ‘The size of pattetn generator, or hardware/software system needed to properly stimulate the device under test 3... The size of the testing process itself 4. The time needed to load the test patterns and 5, The external equipment required (if any). Examples of ATPG algorithm methods that are in.wide use include the D-Algorithm, the PODEM, and the FAN. Pattern ‘generation through any of these algorithmic methods require what i known as ‘path Sensitization’. “Path sensitization” refers to finding a path in the circuit that will allow an error to show up at an observable output of a device if it is'faulty. For example, in a two input AND gate, sensitizing the path of one input requires the other input to be set to ‘1°. Most algorithmic generation methods also refer to the. notation D and: D. These.notations were introduced by the D algorithm and have been adopted by other algorithms since then D simply stands fora ‘1 in a good circuit and a ‘0" ina faulty one. On the other hand, which is the opposite of D, stands for a ‘0” in a good circuit and ‘1’ in a faculty circuit. Thus, propagating a DorD from the inputs to outputs simply means applying a set of inputs to a device to make its output exhibit an ‘error’ ifthere is @ fault within the circuit, aeAlgorithmic pattem generation basically consists of the following steps, |. Faultseletion, or choosing’ fault that needs to be detected 2.” Initial assignment, or finding an input pattern that steps upaDorD atthe output of the faulty gate Forward drive, or propagating aD or D to an observable output using the shortest path possible; Justification, or assigning of values 6 other unassigned inputs in order to justify the assignments made during the forward drive. If an inconsistency arises during Justification, back tracking or back propagation is Performed i.e., forward drive is done again using an alternate path, This recursive cycle is performed until Tight set of input pattems needed to ‘sensitize’ a path and Propagate the faultto an observable output is determined. A test algorithm is complete if it is able to propagate 4 failure to an observable output if a fault indeed exists. The D algorithm entails finding all sets of inputs to the circuit that Will bring out a fault within the cireuit. A ‘Primitive D Cube of Failure’, ot PCR, isa set of inputs that sensitizes a path for a Particular fault within a circuit. The “Propagation D Cube’, or PDG, is a set of inputs that propagates a D from the inputs to the output. The D-algorithm picks all possible PDCF's for the Circuit under test and applies them to the circuit with their corresponding PDC’s to propagate various faults to the output. ‘While the PDCF's and PDC’s are being applied, the ‘implied’ ‘Values for other circuit nodes are tested for consistency, rejecting Sets of inputs that cause a circuit violation: The application and testing of various PDCF’s and PDC’s for a circuit is done repeatedly and recursively, until the minimal set of input pattems ‘ecessary to test the circuit forthe specified faults is determined. Q45. Explain fault models of VLSI desi Dect7, (R13), 41/0) (or) Explain about different fault models in VLSI testing with examples. An: Fault Simulation Fault simulation is a process of simulation of circuit with existence of faults. That fault simulation results are analyzed - With fault free simulation results of same circuit, then respective faults are detected, ‘The fault simulation techniques are described as follows, 1, Serial and parallel fault simulation 2, Concurrent fault simulation, 1. @ Serial Fault Simulation rf — It is one of the easiest and impractical ‘simulation technique. a — Its determined by considering two versions or copies of circuit ie., good circuit and faulty circuit. => Itfirstselecta fault and include to faulty cire VLSI DESIGN [JNTU-HYDERABAD) “Then repeat the simulating process at a time” =. Ihis slow process. Mens yale Fault Simulation erin Reasi'at pera ae simulation ig multiple bits of words. Ittakes only binary (0 ang 1) values. It uses 32 bit machine word, an integer whith consists of 32 bit binary vector. It possible to simulate 32 copies at time by using parallel fault simulation. - Itis 32 times faster than serial fault simulation. Here i consider one good copy and include that into other copies, 2. Concurrent Fault Simulati Itis one of the advantageous fault simulation technique which it does not simulate the whole circuit. It sitifates only differential parts of the whole circuit. At first, it completely simulates the good circuit. After that the only faultis Simulated, Itis very critical to find the fault parts of circuit, But it is used to save memory and also possible to do concurrent simulation. Itis segmented into different modules which each module is simulated separatel Q46. Write short notes on, 4. Delay Fault Testing 2. Fault Sampling. Ans: 1. Delay Fault Testing Failures that occur in CMOS could leave the functionality of the circuit untouched, but effect the timing. For instance, consider the layout shown in figure fora high-power NAND gate composed of paralleled n and p-transistors. Ifthe link illustrated ‘was opened, the gate would still function, but with increased pull down time. In addition, the fault now becomes sequential because the detection ofthe fault depends on the pre of the gate and the simulation clock speed. & =F Figure: An Example of a Delay Fault 2. Fault Sampling Zee fault sampling technique is used to simulate only sampled group of faults at anode. The random nodes are picked id the rate of an error detection